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* x86: Remove DECLARE_GLOBAL_DATA_PTR in board filesBin Meng2015-06-041-2/+0
| | | | | | | | gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR should be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONSBin Meng2015-04-291-0/+3
| | | | | | | | | Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-291-1/+1
| | | | | | | | | For starting a Linux console on the superio serial port under interrupt mode, the IRQ number must be configured. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng2015-01-131-0/+1
| | | | | | | | Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-181-0/+6
| | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-181-0/+20
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-181-0/+5
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-184-0/+43
Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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