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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala2009-01-231-3/+3
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-10/+10
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Remove LBC_CACHE_BASE from 8544 DSAndy Fleming2008-07-141-10/+2
| | | | | | | | | | The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-261-1/+1
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8544 DS to new TLB setupKumar Gala2008-01-171-0/+99
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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