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* ARM: uniphier: drop PH1- prefix from CONFIG options and file namesMasahiro Yamada2016-03-2466-224/+213
| | | | | | | | The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add device tree for Micro Support CardMasahiro Yamada2016-03-246-0/+58
| | | | | | | Import uniphier-support-card.dtsi from Linux Kernel and make it available on the UniPhier reference boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Fix spelling of "transferred".Vagrant Cascadian2016-03-222-5/+5
| | | | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* sandbox: Avoid calling commands when not availableSimon Glass2016-03-221-1/+9
| | | | | | | Don't try to run commands when not supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-222-0/+7
| | | | | | | | Update the link script to drop this code when not needed. This is only done for two architectures at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-2211-144/+93
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| * armv8/fsl-lsch2: fix sdhc clock frequency valueYangbo Lu2016-03-211-0/+4
| | | | | | | | | | | | | | | | | | The eSDHC could select to use platform clock or peripheral clock to generate SD clock. The default selection is platform clock. So, fix the clock frequency value that's calculated for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Updating entries in Serdes TablePratiyush Srivastava2016-03-211-7/+7
| | | | | | | | | | | | | | | | | | | | | | The serdes protocol entries in Serdes table 1 for protocol 0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45 and 0x47 are updated to reflect the entries in current Reference Manual. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-211-0/+1
| | | | | | | | | | | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci/layerscape: add defines for LUTStuart Yoder2016-03-211-0/+4
| | | | | | | | | | | | | | | | | | | | The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID. Add defines for the register offsets. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: update stream ID partitioning infoStuart Yoder2016-03-211-21/+34
| | | | | | | | | | | | | | | | | | Update comments around how stream IDs are partitioned. Stream IDs allocated to PCI are no longer divided up by controller, but are instead a contiguous range Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: remove obsolete stream ID partitioning supportStuart Yoder2016-03-211-113/+0
| | | | | | | | | | | | | | | | | | | | Remove stream ID partitioning support that has been made obsolete by upstream device tree bindings that specify how representing how PCI requester IDs are mapped to MSI specifiers and SMMU stream IDs. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPATAlison Wang2016-03-211-2/+2
| | | | | | | | | | | | | | | | | | As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie2016-03-211-0/+4
| | | | | | | | | | | | | | | | | | To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha2016-03-213-0/+31
| | | | | | | | | | | | | | | | | | | | Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm64: Fix layerscape mmu setupAlexander Graf2016-03-212-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: socfpga: sr1500: Misc updates (SPI speed, env location)Stefan Roese2016-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the SR1500 board port: - Update defconfig to support SPI NOR (use make savedefconfig). - Increase SPI speed to a maximum of 100MHz for faster system bootup. - Change environment location, so that its not between SPL and main U-Boot. This way the combined SPL / U-Boot image can be used for updates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-175-29/+29
|/ | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-173-0/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for the samus chromebookSimon Glass2016-03-172-0/+629
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support a chained-boot development flowSimon Glass2016-03-171-0/+80
| | | | | | | | | | | | | | | | | | Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-171-1/+0
| | | | | | | | This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-171-311/+83
| | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common SDRAM-init codeSimon Glass2016-03-173-0/+327
| | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common PCH code into a common placeSimon Glass2016-03-176-84/+99
| | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-172-1/+247
| | | | | | | | | | | | This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-172-0/+18
| | | | | | | Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-172-0/+58
| | | | | | | | Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-174-0/+509
| | | | | | | | | Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add power-control supportSimon Glass2016-03-173-0/+220
| | | | | | | | | | Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add reference code supportSimon Glass2016-03-172-0/+114
| | | | | | | | Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add an LPC driverSimon Glass2016-03-173-0/+110
| | | | | | | | Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a northbridge driverSimon Glass2016-03-172-0/+60
| | | | | | | | Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a SATA driverSimon Glass2016-03-172-0/+270
| | | | | | | | Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-173-0/+370
| | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a PCH driverSimon Glass2016-03-174-0/+839
| | | | | | | Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support for broadwellSimon Glass2016-03-1710-0/+1246
| | | | | | | | This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for running Intel reference codeSimon Glass2016-03-172-0/+23
| | | | | | | | | | | | Intel has invented yet another binary blob which firmware is required to run. This is run after SDRAM is ready. It is linked to load at a particular address, typically 0, but is a relocatable ELF so can be moved if required. Add support for this in the build system. The file should be placed in the board directory, and called refcode.elf. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop all the old pin configuration codeSimon Glass2016-03-171-141/+0
| | | | | | | | We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-173-0/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: link: Add pin configuration to the device treeSimon Glass2016-03-171-0/+155
| | | | | | | | | | | | At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update microcode for secondary CPUsSimon Glass2016-03-175-2/+12
| | | | | | | | Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-171-1/+2
| | | | | | | | Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Record the CPU details when starting each coreSimon Glass2016-03-173-1/+20
| | | | | | | | As each core starts up, record its microcode version and CPU ID so these can be presented with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-172-26/+62
| | | | | | | | At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow I/O functions to use pointersSimon Glass2016-03-171-2/+10
| | | | | | | | | | | | | | | | | | | | | It is common with memory-mapped I/O to use the address of a structure member to access memory, as in: struct some_regs { u32 ctrl; u32 data; } struct some_regs *regs = (struct some_regs *)BASE_ADDRESS; writel(1, &reg->ctrl); writel(2, &reg->data); This does not currently work with inl(), outl(), etc. Add a cast to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-171-0/+22
| | | | | | | | | | The clrsetbits_...() macros are useful for working with memory mapped I/O. But they do not work with I/O space, as used on x86 machines. Add some macros to provide similar features for I/O. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-171-2/+0
| | | | | | | | This function was removed in the previous clean-up. Drop it from the header file also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-1710-369/+418
| | | | | | | | | | Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-173-5/+5
| | | | | | | This same name is used in USB. Add a prefix to distinguish it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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