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* x86: Drop all the old pin configuration codeSimon Glass2016-03-171-141/+0
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-173-0/+218
* x86: link: Add pin configuration to the device treeSimon Glass2016-03-171-0/+155
* x86: Update microcode for secondary CPUsSimon Glass2016-03-175-2/+12
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-171-1/+2
* x86: Record the CPU details when starting each coreSimon Glass2016-03-173-1/+20
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-172-26/+62
* x86: Allow I/O functions to use pointersSimon Glass2016-03-171-2/+10
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-171-0/+22
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-171-2/+0
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-1710-369/+418
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-173-5/+5
* x86: Move common CPU code to its own placeSimon Glass2016-03-176-76/+162
* x86: Move common LPC code to its own placeSimon Glass2016-03-176-85/+166
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-174-7/+9
* x86: Create a common header for Intel register accessSimon Glass2016-03-176-6/+22
* x86: Move microcode code to a common locationSimon Glass2016-03-176-4/+8
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-174-1/+8
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-172-0/+24
* x86: broadwell: Add a few microcode filesSimon Glass2016-03-172-0/+2272
* x86: Add comments to the SIPI vectorSimon Glass2016-03-172-0/+2
* x86: Tidy up mp_init to reduce duplicationSimon Glass2016-03-171-53/+26
* x86: Correct duplicate POST valuesSimon Glass2016-03-171-2/+2
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-171-0/+5
* x86: dts: link: Add board ID GPIOsSimon Glass2016-03-171-0/+2
* x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-171-111/+110
* x86: link: Add required GPIO propertiesSimon Glass2016-03-171-3/+9
* x86: Add some more common MSR indexesSimon Glass2016-03-173-20/+43
* x86: cpu: Make the vendor table constSimon Glass2016-03-171-1/+1
* x86: Support booting SeaBIOSBin Meng2016-03-173-0/+28
* x86: Implement functions for writing coreboot tableBin Meng2016-03-173-0/+147
* x86: Support writing configuration tables in high areaBin Meng2016-03-171-0/+11
* x86: Simplify codes in write_tables()Bin Meng2016-03-171-27/+34
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-173-6/+5
* x86: Use a macro for ROM table alignmentBin Meng2016-03-172-5/+7
* x86: Change to use start/end address pair in write_tables()Bin Meng2016-03-171-6/+12
* x86: Clean up coreboot_tables.hBin Meng2016-03-171-73/+80
* x86: Move sysinfo related to sysinfo.hBin Meng2016-03-172-4/+2
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-174-3/+1
* spl: arm: Make sure to include all of the u_boot_list entriesTom Rini2016-03-165-15/+9
* arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini2016-03-161-1/+7
* ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini2016-03-161-1/+2
* ARM: keystone2: Switch to using the poweroff commandTom Rini2016-03-164-29/+30
* ARM: keystone2: Split monitor code / command codeTom Rini2016-03-164-52/+71
* ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon2016-03-151-3/+3
* arm: Allow EFI payload code to take exceptionsAlexander Graf2016-03-151-0/+8
* arm64: Allow EFI payload code to take exceptionsAlexander Graf2016-03-151-0/+9
* arm64: Allow exceptions to returnAlexander Graf2016-03-151-0/+34
* efi_loader: Add runtime servicesAlexander Graf2016-03-154-0/+54
* arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-151-0/+9
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