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* x86: Drop asm/arch/gpio.hBin Meng2016-02-051-13/+0
| | | | | | | | | asm/arch/gpio.h is not needed anymore as we get the GPIO base from PCH driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Move struct fspinit_rtbuf definition to chipset headerBin Meng2016-01-131-0/+4
| | | | | | | | | | | | | All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that does not follow 1.0 spec (possible due to that FSP predates the 1.0 spec), and future FSP binary that is complaint to v1.1 spec defines an optional paltform-specific runtime data in the struct fspinit_rtbuf. Hence move the definition to chipset header. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Rename shared_data to fsp_config_dataBin Meng2016-01-131-0/+15
| | | | | | | | | | | | FSP has several config data like UPD, HDA verb table which can be overridden or provided by bootloader. Currently in U-Boot only UPD is handled via struct shared_data. To accommodate any platform, we rename shared_data to fsp_config_data and move the definition from common place fsp_support.h to platform-specific place fsp_configs.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Do not assert VPD_IMAGE_REV when DEBUGBin Meng2015-08-141-1/+0
| | | | | | | | | | When using different release version of Intel FSP, the VPD_IMAGE_REV is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304). Remove the asserting of this so that U-Boot does not hang in a debug build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-051-1/+2
| | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-291-1/+1
| | | | | | | | The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-063-0/+147
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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