summaryrefslogtreecommitdiffstats
path: root/arch/x86/dts/minnowmax.dts
Commit message (Collapse)AuthorAgeFilesLines
* x86: minnowmax: Drop io-base property in the pch_pinctrl nodeBin Meng2016-02-051-1/+0
| | | | | | | | IOBASE is now obtained from PCH driver, drop this <io-base> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-051-42/+44
| | | | | | | | | | | | | | | | At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-051-1/+1
| | | | | | | | | | At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Correct spi node aliasBin Meng2016-01-281-2/+2
| | | | | | | | With recent changes spi node was moved to a place as a subnode under pch, so update the alias to refer to its correct place as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-241-75/+83
| | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Convert to use driver model timerBin Meng2015-12-011-0/+1
| | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-211-0/+6
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Correct pad-offset value for host_en1Simon Glass2015-08-261-1/+1
| | | | | | | This should be 0x250, not 0x258. Fix it. Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Add access to GPIOs E0, E1, E2Simon Glass2015-08-261-0/+27
| | | | | | | These GPIOs are accessible on the pin header. Add pinctrl settings for them so that we they can be adjusted using the 'gpio' command. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Support multiple microcode copiesBin Meng2015-08-261-0/+3
| | | | | | | | | | | | Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Define and enable interrupt setupSimon Glass2015-08-141-3/+66
| | | | | | | | Set up interrupts correctly so that Linux can use all devices. Use savedefconfig to regenerate the defconfig file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-141-0/+56
| | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-281-0/+1
| | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
* dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-141-0/+10
| | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-041-0/+23
| | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable multi-core init for Minnowboard MAXSimon Glass2015-04-301-0/+20
| | | | | | | | Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This enables multi-core support in Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-291-1/+1
| | | | | | | | The SPI NOR on the minnowboard max is a MICRON N25Q064A Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-291-0/+42
| | | | | | | | | | There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add alias for SPI node in the board dtsBin Meng2015-04-291-1/+2
| | | | | | | | | Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-061-0/+45
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
OpenPOWER on IntegriCloud