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* x86: Add SD/MMC support to quark/galileoBin Meng2015-02-061-0/+11
| | | | | | | | Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SPI support to quark/galileoBin Meng2015-02-061-0/+17
| | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Initialize non-standard BARsBin Meng2015-02-061-0/+46
| | | | | | | | | Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Call MRC in dram_init()Bin Meng2015-02-061-2/+97
| | | | | | | | Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-061-0/+1
| | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add System Memory Controller supportBin Meng2015-02-062-0/+3210
| | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add utility codes needed for MRCBin Meng2015-02-064-0/+2068
| | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-061-0/+204
| | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Bypass TSC calibrationBin Meng2015-02-061-0/+5
| | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable the Intel quark/galileo buildBin Meng2015-02-061-0/+1
| | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add basic Intel Quark processor supportBin Meng2015-02-065-0/+282
| | | | | | | | Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add Cache-As-RAM initializationBin Meng2015-02-061-0/+105
| | | | | | | | | Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add routines to access message bus registersBin Meng2015-02-061-0/+77
| | | | | | | | | | | In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-067-0/+337
| | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-061-38/+0
| | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mmc: Move common FSP functions into a common fileSimon Glass2015-02-063-72/+3
| | | | | | | | | | | | Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make CAR and DRAM FSP code commonSimon Glass2015-02-053-206/+1
| | | | | | | | | For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common FSP code into a common locationSimon Glass2015-02-056-413/+5
| | | | | | Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-051-1/+2
| | | | | | | | If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-051-1/+1
| | | | | | | | | This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-241-28/+0
| | | | | | This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-241-0/+5
| | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-243-0/+410
| | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use ipchecksum from net/Simon Glass2015-01-243-60/+4
| | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix various code format issues in start16.SBin Meng2015-01-231-10/+10
| | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-231-0/+12
| | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Save mtrr support flag in global dataBin Meng2015-01-231-0/+7
| | | | | | | | CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.cBin Meng2015-01-231-0/+2
| | | | | | | | arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Configure pci memory regionsBin Meng2015-01-131-2/+28
| | | | | | | | Configure coreboot pci memory regions so that pci device drivers could work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng2015-01-131-0/+15
| | | | | | | | | | | | There are many places in the U-Boot source tree which refer to CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT that is currently defined in coreboot.h. Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch to board configuration file to build U-Boot later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Set up timer base correctlyBin Meng2015-01-131-13/+20
| | | | | | | | | | | | | | If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value of base_time in coreboot's timestamp table as our timer base, otherwise TSC counter value will be used. Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, the value of base_time in the timestamp table is still zero, so we must exclude this case too (this is currently seen on booting coreboot in qemu). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-132-7/+7
| | | | | | | | | | | These two are not worth having separate inline functions as they are really simple, so drop them. Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-133-10/+34
| | | | | | | | | | | At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Disable CAR before relocation on platforms that need itSimon Glass2015-01-131-0/+8
| | | | | | | For platforms with CAR we should disable it before relocation. Check if this function is available and call it if so. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-131-0/+46
| | | | | | | Cache-as-RAM should be turned off when we relocate since we want to run from RAM. Add a function to perform this task. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-131-0/+10
| | | | | | | | | We should use MTRRs to speed up execution. Add a list of MTRR requests which will dealt with when we relocate and run from RAM. We set RAM as cacheable (with write-back) and registers as non-cacheable. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-131-0/+7
| | | | | | | Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for MTRRsSimon Glass2015-01-134-18/+98
| | | | | | | | | | | | | | Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-131-25/+0
| | | | | | | | | | This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-131-1/+8
| | | | | | | | | | | | This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case. We could add a command to run the video BIOS later when needed, but this is not considered at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Simplify the fsp hob access functionsBin Meng2015-01-122-62/+72
| | | | | | | | | Remove the troublesome union hob_pointers so that some annoying casts are no longer needed in those hob access routines. This also improves the readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Make pci apis usable before relocationBin Meng2015-01-121-4/+4
| | | | | | | | | | | | | | Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support pci bus scan in the early phaseBin Meng2015-01-121-0/+1
| | | | | | | | | On x86, some peripherals on pci buses need to be accessed in the early phase (eg: pci uart) with a valid pci memory/io address, thus scan the pci bus and do the corresponding resource allocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng2015-01-121-0/+2
| | | | | | | | arch/x86/cpu/pci.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up the FSP support codesBin Meng2014-12-183-144/+129
| | | | | | | | | | | | | | | | | | | | | | | | | This is the follow-on patch to clean up the FSP support codes: - Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(&params) in fsp_init() cannot be removed Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SDHCI supportBin Meng2014-12-182-1/+48
| | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-181-1/+25
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-184-5/+5
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-181-0/+79
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-181-0/+1
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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