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* dm: Rename disk uclass to ahciSimon Glass2016-05-172-2/+2
| | | | | | | | This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-171-311/+83
| | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common PCH code into a common placeSimon Glass2016-03-172-31/+17
| | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-171-1/+2
| | | | | | | | Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-171-26/+1
| | | | | | | | At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-175-318/+3
| | | | | | | | | | Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common CPU code to its own placeSimon Glass2016-03-171-74/+6
| | | | | | | | Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common LPC code to its own placeSimon Glass2016-03-172-83/+6
| | | | | | | | Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-172-2/+5
| | | | | | | | This is similar to MCH in that it is used in various drivers. Add it to the common header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Create a common header for Intel register accessSimon Glass2016-03-174-3/+7
| | | | | | | | | | | | | | There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move microcode code to a common locationSimon Glass2016-03-173-168/+1
| | | | | | | This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-172-242/+0
| | | | | | | | This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some more common MSR indexesSimon Glass2016-03-171-2/+3
| | | | | | | | | Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-144-18/+10
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-211-0/+4
| | | | | | | | | This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng2016-02-212-1/+5
| | | | | | | | Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add FSP supportBin Meng2016-02-214-0/+79
| | | | | | | | | | IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
* x86: pch: Implement get_gpio_base opBin Meng2016-02-051-0/+33
| | | | | | | | Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-051-2/+2
| | | | | | | | Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pch: Remove pch_get_version opBin Meng2016-02-051-6/+0
| | | | | | | | | | | | | pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-243-12/+11
| | | | | | | | | Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Set up a shared syscon numbering schemaSimon Glass2016-01-242-4/+5
| | | | | | | | | Each system controller can have a number to identify it. It can then be accessed using syscon_get_by_driver_data(). Put this in a shared header file and update the only current user. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the SMM-locking codeSimon Glass2016-01-241-57/+0
| | | | | | | | U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop XHCI supportSimon Glass2016-01-242-33/+0
| | | | | | | This is not used on link which is the only ivybridge board. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop special EHCI initSimon Glass2016-01-243-33/+0
| | | | | | | | | | This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Sort out the calls to bridge_silicon_revision()Simon Glass2016-01-242-41/+39
| | | | | | | | This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move code from pch.c to bd82x6x.cSimon Glass2016-01-243-127/+129
| | | | | | | This code relates to the PCH, so we should move it into the same file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert pch.c to use DM PCI APISimon Glass2016-01-243-27/+39
| | | | | | | Convert this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert report_platform to DM PCI APISimon Glass2016-01-242-6/+7
| | | | | | | Convert these functions to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert SDRAM init to use driver modelSimon Glass2016-01-242-33/+55
| | | | | | | | | SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert sdram_initialise() to use DM PCI APISimon Glass2016-01-241-9/+10
| | | | | | | | Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert dram_init() to use DM PCI APISimon Glass2016-01-241-14/+25
| | | | | | | | Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass2016-01-241-17/+17
| | | | | | | | | Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-241-36/+3
| | | | | | | | Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert lpc init code to DM PCI APISimon Glass2016-01-241-63/+66
| | | | | | | | Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-242-47/+0
| | | | | | | | There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-242-12/+9
| | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-243-8/+4
| | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in sata.cSimon Glass2016-01-241-49/+45
| | | | | | | Adjust the functions in this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use the SATA driver to do the initSimon Glass2016-01-242-9/+8
| | | | | | | | Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass2016-01-242-17/+0
| | | | | | | This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-243-3/+27
| | | | | | | | | The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop unnecessary northbridge setupSimon Glass2016-01-241-20/+0
| | | | | | | This is done by default with PCI auto-config. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in bd82x6x.cSimon Glass2016-01-241-13/+7
| | | | | | | | | Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-242-46/+12
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move early init code into northbridge.cSimon Glass2016-01-243-82/+67
| | | | | | | | This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the dead MTRR codeSimon Glass2016-01-241-10/+0
| | | | | | | This is not used and MTRRs are set up elsewhere now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the thermal target correctlySimon Glass2016-01-241-11/+10
| | | | | | | | | This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move CPU init code into the driverSimon Glass2016-01-242-7/+4
| | | | | | | | Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use common CPU init codeSimon Glass2016-01-241-52/+42
| | | | | | | | | The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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