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* powerpc/mpc85xx: Fix the I2C bus speed error on p1022Tang Yuantian2013-09-091-1/+2
| | | | | | | | The source clock frequency of I2C bus on p1022 is the platform(CCB) clock, not CCB/2. The wrong source clock frequency leads to wrong I2C bus speed setting. so, fixed it. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* SPL: P1022DS: switch to new multibus/multiadapter supportYing Zhang2013-09-091-0/+5
| | | | | | | - Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds - Use the function i2c_init_all instead of i2c_init Signed-off-by: Ying Zhang <b40530@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-2117-175/+201
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| * Fix for incorrect conversion hex string to number (FMAN firmware address).Николай Пузанов2013-08-201-1/+1
| | | | | | | | | | Signed-off-by: Николай Пузанов <punzik@gmail.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/sec: Add workaround for SEC A-003571Shengzhou Liu2013-08-202-1/+13
| | | | | | | | | | | | | | | | | | Multiple read/write transactions initiated by security engine may cause system to hang. Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/t4240: add QSGMII interface supportShaohui Xie2013-08-201-7/+7
| | | | | | | | | | | | | | | | | | | | Also some fix for QSGMII. 1. fix QSGMII configure of Serdes2. 2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN. 3. fix dtb for QSGMII interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpcv2: Print hardcoded size like print_size() doesShruti Kanetkar2013-08-207-21/+21
| | | | | | | | | | | | | | | | | | Makes the startup output more consistent Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc: Use print_size() where appropriateShruti Kanetkar2013-08-204-22/+21
| | | | | | | | | | | | | | | | Makes the startup output more consistent Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc: Fix CamelCase checkpatch warningsPrabhakar Kushwaha2013-08-205-124/+127
| | | | | | | | | | | | | | | | | | | | | | 85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase". Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc: mpc85xx: Support booting from SD Card with SPLYing Zhang2013-08-202-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some ↵Ying Zhang2013-08-202-3/+6
| | | | | | | | | | | | | | | | | | | | | | functionality for common SPL 1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it. 2. Some functions were unused in the minimal SPL, but it is useful in the common SPL. So, enabled some functionality for common SPL. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | ppc4xx: Remove support for PPC405CR CPUsMatthias Fuchs2013-08-205-27/+11
| | | | | | | | | | | | | | This patch removes support for the APM 405CR CPU. This CPU is EOL and no board uses this chip. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | fsl_i2c: add workaround for the erratum I2C A004447Chunhe Lan2013-08-201-0/+5
|/ | | | | | | | | | | | | | | | | | | | | | | This workaround is for the erratum I2C A004447. Device reference manual provides a scheme that allows the I2C master controller to generate nine SCL pulses, which enable an I2C slave device that held SDA low to release SDA. However, due to this erratum, this scheme no longer works. In addition, when I2C is used as a source of the PBL, the state machine is not able to recover. At the same time, delete the reduplicative definition of SVR_VER and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16 bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro instead of hard-code value 0x10, 0x11 and 0x20. The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one version of platform has this I2C errata. So enable this errata by IS_SVR_REV(svr, maj, min) function. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* SPDX-License-Identifier: convert PIBS licensed filesWolfgang Denk2013-08-194-109/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
* powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-141-22/+0
| | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-141-3/+4
| | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2Prabhakar Kushwaha2013-08-141-0/+16
| | | | | | | | | | It is not necessary for all processor to have serdes block 1 & 2. They may have only one serdes block. So, put serdes block 1 & 2 related code under defines Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-1323-35/+247
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| * powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-121-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-091-1/+1
| | | | | | | | | | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-093-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-092-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-091-1/+0
| | | | | | | | | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-093-0/+26
| | | | | | | | | | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-096-12/+79
| | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-094-0/+11
| | | | | | | | | | | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-092-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-091-4/+19
| | | | | | | | | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
| * mpc85xx: Base emulator supportYork Sun2013-08-094-1/+19
| | | | | | | | | | | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/t4: Correct LIODN assignment for SRIOLiu Gang2013-08-091-2/+2
| | | | | | | | | | | | | | For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang2013-08-091-2/+2
| | | | | | | | | | | | | | For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* | video: Encapsulate font in video_font_data.hMarek Vasut2013-08-121-1/+0
|/ | | | | | | | | | | | This patch moves all the font configuration values into video_font_data.h so they are all in the right place with the font. The video_font.h now only includes video_font_data.h and will allow us to select and include different font once more fonts are added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> [agust: fixed build warning for mcc200] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-247-29/+9
|\ | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * i2c, ppc4xx_i2c: switch to new multibus/multiadapter supportDirk Eibach2013-07-235-15/+5
| | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
| * i2c, multibus: get rid of CONFIG_I2C_MUXHeiko Schocher2013-07-231-14/+0
| | | | | | | | | | | | | | | | | | | | | | CONFIG_I2C_MUX is replaced through the new i2c multibus/multiadapter framework, configured through CONFIG_SYS_I2C. As CONFIG_I2C_MUX is only used on the keymile boards, and they are now completely moved to the new framework, remove CONFIG_I2C_MUX. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-By: Holger Brunck <holger.brunck@keymile.com>
| * i2c: common changes for multibus/multiadapter supportHeiko Schocher2013-07-231-0/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Cc: Henrik Nordström <henrik@henriknordstrom.net>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24240-3885/+240
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPLPrabhakar Kushwaha2013-07-161-1/+3
| | | | | | | | | | CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs. CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need of disable_tlb(). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add P1023RDB board supportChunhe Lan2013-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Disable Debug TLB entry before init_tlbsPrabhakar Kushwaha2013-06-201-0/+4
| | | | | | | | | init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZEAxel Lin2013-06-2019-25/+25
| | | | | | | | If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: modify the functionality clear_bss and aligning the end ↵Ying Zhang2013-06-202-1/+3
| | | | | | | | | | | | | | | | | | | | address of the BSS There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: support application without resetvec segment in the linker ↵Ying Zhang2013-06-202-0/+22
| | | | | | | | | | | | | | | | script For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: work around erratum A-006593Scott Wood2013-06-202-0/+6
| | | | | | | | | | | | Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_ifc: add support for different IFC bank countMingkai Hu2013-06-201-1/+57
| | | | | | | | | | | | Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-202-3/+3
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: Use lower case for the core namesFabio Estevam2013-06-202-5/+5
| | | | | | | | | | | | | | | | | | Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha2013-06-201-1/+1
| | | | | | | | | | | | | | Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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