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* powerpc: ppc4xx: canyonlands: Move to generic boardSimon Glass2015-02-121-0/+2
| | | | | | Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Fix ppc4xx CONFIG_SYS_GENERIC_BOARDDirk Eibach2014-11-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I realized that with v2014.10 u-boot is not starting up on ppc4xx boards with CONFIG_SYS_GENERIC_BOARD set. I bisected it down to this: d54d7eb support blackfin board initialization in generic board_f With d29437a ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARD I set gd to a defined value for ppc4xx in cpu_init_f(). I did not realize that the gd struct has also to be memset() to zero at this point. But at least commit d54d7eb assumes it is: @@ -516,11 +528,13 @@ static int reserve_malloc(void) /* (permanently) allocate a Board Info struct */ static int reserve_board(void) { - gd->start_addr_sp -= sizeof(bd_t); - gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); - memset(gd->bd, '\0', sizeof(bd_t)); - debug("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof(bd_t), gd->start_addr_sp); + if (!gd->bd) { + gd->start_addr_sp -= sizeof(bd_t); + gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); + memset(gd->bd, '\0', sizeof(bd_t)); + debug("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof(bd_t), gd->start_addr_sp); + } return 0; } #endif This might also be an issue on other architectures, so maintainers should check. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc: ppc4xx: remove board support for bluestoneMasahiro Yamada2014-10-101-2/+2
| | | | | | | | | This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARDDirk Eibach2014-07-251-2/+2
| | | | | | | | The generic board infrastructure assumes that gd is set by arch code. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove support for PPC405CR CPUsMatthias Fuchs2013-08-201-1/+1
| | | | | | | This patch removes support for the APM 405CR CPU. This CPU is EOL and no board uses this chip. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* PPC405EX CHIP_21 erratumSteven A. Falco2011-05-121-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change tsr/tcr macros to upper caseStefan Roese2010-10-201-4/+4
| | | | | | Remove uneccessary functions to access the TCR/TSR registers as well. Signed-off-by: Stefan Roese <sr@denx.de>
* APM821xx: Add CPU supportTirumala Marri2010-10-041-2/+3
| | | | | | | | | APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Big header cleanup part 2, mostly PPC405 relatedStefan Roese2010-09-231-1/+1
| | | | | | | | | | | | | | | This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Big header cleanup, mostly PPC440 relatedStefan Roese2010-09-231-4/+4
| | | | | | | | | | | This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move gpio.h to ppc4xx-gpio.h since its ppc4xx specificStefan Roese2010-09-231-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move ppc4xx headers to powerpc include directoryStefan Roese2010-09-231-2/+2
| | | | | | | | | This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 440EPx bug in reconfigure_pll()Stefan Roese2010-09-031-9/+18
| | | | | | | | | | | | | | | | This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rupjyoti Sarmah <rsarmah@amcc.com> Cc: Victor Gallardo <vgallardo@appliedmicro.com>
* ppc4xx: Enable booting with Option E on 460EX/EXr/GTStefan Roese2010-07-011-10/+39
| | | | | | | | | This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: Stefan Roese <sr@denx.de>
* Move arch/ppc to arch/powerpcStefan Roese2010-04-211-0/+456
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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