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* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2013-07-253-8/+39
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| * nds32: Enable FPU if the version of CPU supportedken kuo2013-07-251-0/+26
| | | | | | | | | | | | | | | | | | Some version of Andes core support FPU coprocessor, if this is the case, and toolchain support FPU instruction set, we should enable it at low level initialization time. Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: Convert Makefiles to use COBJS-y styleken kuo2013-07-251-4/+4
| | | | | | | | | | Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: ag101/ag102: Fix setting lastdec and now valuesAxel Lin2013-07-241-3/+4
| | | | | | | | | | | | | | | | | | | | The timer3 counter unit for lastdesc and now values are inconsistent in current code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is second. However, CONFIG_SYS_HZ is defined as 1000 in board config file. This means the accuracy of "lastdec" and "now" should be in millisecond, thus fix the equation to set lastdec and now variables accordingly. Signed-off-by: Axel Lin <axel.lin@ingics.com>
| * nds32: Enable two banks of SDRAM on Andes boardken kuo2013-07-241-1/+5
| | | | | | | | | | | | | | | | | | The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-245-84/+5
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* nds32: split common cache access from cpu into libMacpaul Lin2012-07-201-112/+0
| | | | | | | | | | | This commit does the following updates. 1. Split the common cache access from cpu.c into lib folder. 2. Rename the following cache api to adapt common.h - dcache_flush_rang -> flush_dcache_rang - icache_inval_range -> invalidate_icache_range 3. Add invalidate_dcache_range Signed-off-by: Macpaul Lin <macpaul@gmail.com>
* nds32/ag101/watchdog.S: add linkage supportMacpaul Lin2012-02-281-2/+3
| | | | | | Add linkage support to watchdog.S. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* nds32/ag101: clean up for SoC related codeMacpaul Lin2011-11-232-10/+6
| | | | | | | | Remove unneccessary codes. 1. Clean up for cpu related code. 2. Clean up for timer related code. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* nds32/ag101: cpu and init funcs of SoC ag101Macpaul Lin2011-10-226-0/+792
SoC ag101 is the first chip using NDS32 N1213 cpu core. Add header file of device offset support for SoC ag101. Add main function of SoC ag101 based on NDS32 n1213 core. Add lowlevel_init.S and other periphal related code. This version of lowlevel_init.S also replace hardcode value by MARCO defines from the GPL version andesboot for better code quality. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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