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* MIPS: start.S: use symbol __image_copy_end for U-Boot image relocationDaniel Schwierzeck2013-02-124-16/+9
| | | | | | | | | Use the newly introduced symbol __image_copy_end as end address for relocation of U-Boot image. This is needed for dynamic relocation added in later patches. This patch obsoletes the symbols uboot_end and uboot_end_data which are removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: start.S: optimize BSS initializationDaniel Schwierzeck2013-02-123-28/+35
| | | | | | | | | | | | Get the start and end address for clearing BSS from the newly introduced symbols __bss_start and __bss_end. After GOT is relocated, those symbols are already pointing to the correct addresses. Also optimize the loop by moving the address incrementation to the delay slot to avoid the initial sub instruction. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: u-boot.lds: introduce symbol __image_copy_endDaniel Schwierzeck2013-02-121-0/+2
| | | | | | | This symbol is used in later patches as end address for relocation of the U-Boot image into RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: u-boot.lds: merge all BSS sections and introduce symbols __bss_[start|end]Daniel Schwierzeck2013-02-121-5/+6
| | | | | | | These symbols are used in later patches for as addresses for clearing the BSS area in the relocated U-Boot image. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: compute num_got_entries from .got section's sizeGabor Juhos2013-02-121-4/+2
| | | | | | | | | | | | The '__got_start' and '__got_end' symbols are used only in the linker script to compute the value of the 'num_got_entries' symbol. Remove the symbols and use the SIZEOF(.got) command to get the size of the .got section. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start.S: unify and simplify reset vector handlingDaniel Schwierzeck2013-02-122-176/+57
| | | | | | Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: start.S: remove obsolete 64 bit handling in setup_c0_statusDaniel Schwierzeck2013-02-121-9/+1
| | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: xburst: fix broken access to global_dataDaniel Schwierzeck2013-02-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix access to global_data which is broken since commits: commit 035cbe99cd2fd4adf9d7fd95aeebb5f814e37eb9 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:49:08 2012 +0000 mips: Move per_clk and dev_clk to arch_global_data Move these field into arch_global_data and tidy up. The other CONFIG_JZSOC fields are used by various architectures, so just remove the #ifdef bracketing for these. Signed-off-by: Simon Glass <sjg@chromium.org> commit 582601da2f90b1850aa19f7820b1623c79b3dac6 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:35 2012 +0000 arm: Move lastinc to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> commit 66ee69234795c0596f84b25f06b7fbc2e8ed214c Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:34 2012 +0000 arm: Move tbl to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* arm: Move lastinc to arch_global_dataSimon Glass2013-02-011-6/+6
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Move tbl to arch_global_dataSimon Glass2013-02-011-6/+6
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* MIPS: add unified u-boot.lds fileGabor Juhos2013-01-311-0/+84
| | | | | | | | | | | | The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Stefan Roese <sr@denx.de>
* MIPS: remove OUTPUT_FORMAT from linker scriptsGabor Juhos2013-01-302-0/+12
| | | | | | | | | | | | | | | | The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* MIPS: xburst: simplify relocation offset calculationGabor Juhos2013-01-301-9/+3
| | | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* MIPS: simplify relocated _G_O_T_ address calculationGabor Juhos2013-01-303-12/+3
| | | | | | | | | | | | | | | The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* MIPS: start.S: don't save flush_cache parameters in advanceGabor Juhos2013-01-272-20/+4
| | | | | | | | | | | | | | | | Saving the parameters in advance unnecessarily complicates the code. The destination address is already saved in the 's2' register, and that register is not clobbered by the copy loop. The size of the copied data can be computed after the copy loop is done. Change the code to compute the size parameter right before calling flush_cache, and set the destination address parameter in the delay slot of the actuall call. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start.S: simplify relocation offset calculationGabor Juhos2013-01-272-18/+6
| | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start.S: save reused arguments earlier in relocate_codeGabor Juhos2013-01-272-4/+6
| | | | | | | | | Save the reused parameters at the beginning of the 'relocate_code' function. This makes the function a bit more readable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start.S: set sp register directlyGabor Juhos2013-01-272-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses two instructions to load the stack pointer into the 'sp' register. This results in the following assembly code: 468: 3c088040 lui t0,0x8040 46c: 251d0000 addiu sp,t0,0 The first instuction loads the stack pointer into the 't0' register then the value of the 'sp' register is computed by adding zero to the value of the 't0' register. The same issue present on the 64-bit version as well: 56c: 3c0c8040 lui t0,0x8040 570: 659d0000 daddiu sp,t0,0 Change the code to load the stack pointer directly into the 'sp' register. The generated code is functionally equivalent to the previous version but it is simpler. 32-bit: 468: 3c1d8040 lui sp,0x8040 64-bit: 56c: 3c1d8040 lui sp,0x8040 Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start.S: fix boundary check in relocate_codeGabor Juhos2013-01-273-3/+3
| | | | | | | | | | | | | The loop code copies more data with one than necessary due to the 'ble' instuction. Use the 'blt' instruction instead to fix that. Due to the lack of suitable hardware the Xburst specific code is compile tested only. However the change is quite obvious. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: start{, 64}.S: fill branch delay slots with NOP instructionsGabor Juhos2013-01-222-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: fix a latent bug on initialize $gpZhi-zhou Zhang2012-12-081-1/+6
| | | | | | | | | If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned. then the following ld insntrustion generates a Adel exception. So here make _gp be always aligned in 8 bytes. Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-11-272-2/+0
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| * MIPS: do not initialize timestamp variable before relocate_codeZhi-zhou Zhang2012-11-252-2/+0
| | | | | | | | | | | | | | | | | | Because timestamp is declared as `static', we needn't initialize it by writing it a zero. If we do it before relocate_code, we will write into a flash address(0xffffffffbfc0xxxx). Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | usb: use linux/usb/ch9.h instead of usbdescriptors.hIlya Yanok2012-11-201-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | Linux usb/ch9.h seems to have all the same information (and more) as usbdescriptors.h so use the former instead of the later one. As a consequense of this change USB_SPEED_* values don't correspond directly to EHCI speed encoding anymore, I've added necessary recoding in EHCI driver. Also there is no point to put speed into pipe anymore so it's removed and a bunch of host drivers fixed to look at usb_device->speed instead. Old usbdescriptors.h included is not removed as it seems to be used by old USB device code. This makes usb.h and usbdevice.h incompatible. Fortunately the only place that tries to include both are the old MUSB code and it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute on musb_regs structure but this attribute seems to be unneeded (old MUSB code doesn't support any DMA at all). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-10-1711-17/+819
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| * MIPS: add board qemu-mips64 supportZhi-zhou Zhang2012-10-167-0/+802
| | | | | | | | | | | | | | | | | | | | | | | | | | Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: don't use camel-case styleZhi-zhou Zhang2012-10-164-17/+17
| | | | | | | | | | | | Replace camel-case style with upper-case style globally. Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
* | split AU1X00 specific code from cmd_ide.cPavel Herrmann2012-10-172-1/+33
| | | | | | | | | | | | move special case of ide_swap_read() for AU1X00 SoC into SoC-specific directory. Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
* | serial: Use default_serial_puts() in driversMarek Vasut2012-10-173-23/+3
|/ | | | | | | | | | Replace the in-place ad-hoc implementation of serial_puts() within the drivers with default_serial_puts() call. This cuts down on the code duplication quite a bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* usb: lowlevel interface change to support multiple controllersLucas Stach2012-10-151-2/+2
| | | | | | | | | | | Carry an index in the lowlevel usb functions to make specify the respective usb controller. Also pass through an controller struct from lowlevel_init to the creation of the root usb device of this controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
* serial: Remove CONFIG_SERIAL_MULTI from serial driversMarek Vasut2012-10-153-96/+0
| | | | | | | | | | | | Remove the support for not-CONFIG_SERIAL_MULTI part from serial port drivers and some board files. Since CONFIG_SERIAL_MULTI is now enabled by default, that part is a dead code. Remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* serial: mips: Implement CONFIG_SERIAL_MULTI into JZ serial driverMarek Vasut2012-10-151-6/+61
| | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into JZ serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the JZ driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* serial: mips: Implement CONFIG_SERIAL_MULTI into asc serial driverMarek Vasut2012-10-151-6/+61
| | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into asc serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the asc driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* serial: mips: Implement CONFIG_SERIAL_MULTI into au1x00 serial driverMarek Vasut2012-10-151-10/+64
| | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into au1x00 serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the au1x00 driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefilesDaniel Schwierzeck2012-08-242-0/+4
| | | | | | Prepare for upcoming MIPS64 CPU support. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: factor out endianess flag handling to arch config.mkDaniel Schwierzeck2012-08-242-20/+2
| | | | | | This is CPU independent and should be configured architecture-wide. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* dm: mips: Fix lb60 timer codeMarek Vasut2012-08-171-6/+6
| | | | | | | | | | | | | | | | | | | | The timer code contains more halfword writes which trigger gcc errors. The registers are again 32bit, yet written by 16bit writes, fix this: timer.c: In function ‘reset_timer_masked’: timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘get_timer_masked’: timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘timer_init’: timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* dm: mips: Fix lb60 WDT controlMarek Vasut2012-08-171-1/+1
| | | | | | | | | | | Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* net: Fix remaining API interface breakageJoe Hershberger2012-05-231-1/+2
| | | | | | | | | | | These are all the files which use the API incorrectly but did not get built using MAKEALL -a powerpc|arm. I have no compiler for them, but the remaining issues should be far less than without this patch. Any outstanding issues are left to the maintainers of boards that use these drivers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* MIPS: fix endianess handlingDaniel Schwierzeck2012-04-021-6/+15
| | | | | | | | | | | | | | | | | Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* MIPS: fix inconsistency in config option for cache operation modeDaniel Schwierzeck2012-04-021-1/+5
| | | | | | | | | | Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* usb: replace wait_ms() with mdelay()Mike Frysinger2012-03-191-14/+14
| | | | | | | | | | | | | | | | | | | | | | | Common code has a mdelay() func, so use that instead of the usb-specific wait_ms() func. This also fixes the build errors: ohci-hcd.c: In function 'submit_common_msg': /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1519:9: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1816:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1827:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1844:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1563:11: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1583:9: sorry, unimplemented: called from here make[1]: *** [ohci-hcd.o] Error 1 Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Marek Vasut <marex@denx.de>
* consolidate mdelay by providing a common function for all usersAnatolij Gustschin2011-10-221-1/+0
| | | | | | | | | There are several mdelay() definitions in the driver and board code. Remove them all and provide a common mdelay() in lib/time.c. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* MIPS: Ingenic XBurst Jz4740 processor supportXiangfu Liu2011-10-107-0/+920
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: mips32: fix wrong loop bound in flush_cache()Yao Cheng2011-09-031-0/+4
| | | | | | | | | | | The issue is found when calling flush_cache() with zero "size" argument. The bound of loop is miscalculated in this case and flush_cache() enters a wrong flushing loop. Signed-off-by: Yao Cheng <saturdaycoder@gmail.com> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: make cache operation mode configurableDaniel Schwierzeck2011-07-311-1/+5
| | | | | | | | | | | Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFGDaniel Schwierzeck2011-07-311-3/+10
| | | | | | | | | This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* Timer: Remove reset_timer() for non-Nios2 archesGraeme Russ2011-07-261-6/+0
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* Timer: Remove set_timer completelyGraeme Russ2011-07-261-6/+0
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* MIPS: Move timer code to arch/mips/cpu/$(CPU)/Shinya Kuribayashi2011-05-102-1/+99
| | | | | | | | | | | | | | Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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