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* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-1017-22/+62
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM64: zynqmp: Sync zynq_sdhci_init() declarationMichal Simek2015-11-071-1/+1
| | | | | | | | | | | | | | | This patch fix compilation error: drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for ‘zynq_sdhci_init’ int zynq_sdhci_init(phys_addr_t regbase) ^ In file included from drivers/mmc/zynq_sdhci.c:14:0: ./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration of ‘zynq_sdhci_init’ was here int zynq_sdhci_init(unsigned long regbase); ^ Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* compat: Remove is_power_of_2() definitionFabio Estevam2015-11-051-1/+1
| | | | | | | | | | Use the is_power_of_2() definition from log2.h to align with the kernel implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: Use the generic bitops headersFabio Estevam2015-11-051-0/+5
| | | | | | | | | | The generic bitops headers are required when calling logarithmic functions, such as ilog2(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge git://git.denx.de/u-boot-samsungTom Rini2015-11-0513-24/+100
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| * arm: exynos: clean up checkpatch issuesMinkyu Kang2015-11-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will fix these checkpatch issues. ERROR: Macros with complex values should be enclosed in parentheses +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex0->concontrol); ^ ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex1->concontrol); ^ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos4412: pinmux: disable pull for MMC pinsPrzemyslaw Marczak2015-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 8 pins for SD card in Exynos, but the MUX was configured only for 7, since the one was used for card detection. This caused the pin's pull wrong configuration. This commit fixes this and the card detect can work properly, after call this function. Tested-on: Odroid U3 and Odroid X2. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Odroid-XU3: dts: enable ADC, with request for pre-reloc bindPrzemyslaw Marczak2015-11-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | This ADC is required for Odroid's board revision detection. The pre-reloc request is enabled, since board detection will be done in one of early function call. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos54xx: dts: add ADC nodePrzemyslaw Marczak2015-11-021-0/+7
| | | | | | | | | | | | | | | | | | | | This commit adds common ADC node, which is disabled as default. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Odroid-XU3: enable s2mps11 PMIC supportPrzemyslaw Marczak2015-11-021-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * dm: adc: add Exynos54xx compatible ADC driverPrzemyslaw Marczak2015-11-021-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds driver for Exynos54xx ADC subsystem. The driver is implemented using driver model, amd provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() The basic parameters of ADC conversion, are: - sample rate: 600KSPS - output the data as average of 8 time conversion ADC features: - sample rate: 600KSPS - resolution: 12-bit - channels: 10 (analog multiplexer) Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5422/5800: set cpu id to 0x5422Przemyslaw Marczak2015-11-027-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back. Changes: - set cpu id to 0x5422 instead of 0x5800 - remove macro proid_is_exynos5800() - add macro proid_is_exynos5422() - change the calls to proid_is_exynos5800() with new macro Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Peach-Pi: dts: add cpu-model stringPrzemyslaw Marczak2015-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This platform is based on Exynos5800 but the cpu id is 0x5422. This doesn't fit the common Exynos SoC name convention, so now, the CPU name is defined by device tree string, to be printed properly. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-021-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-052-4/+4
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| * | arm: dts: socfpga: Increase the spi-max-frequency for QSPI flashChin Liang See2015-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen2015-11-031-3/+3
| | | | | | | | | | | | | | | | | | | | | The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | ARM: zynq: Remove zc70x targetMichal Simek2015-11-041-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | Remove zc70x target which was one setting for zc702 and zc706. Currently zc702 and zc706 are separated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | arm: zynq: Move serial driver to driver modelSimon Glass2015-11-041-0/+1
| | | | | | | | | | | | | | | | | | | | | Update this driver to use driver model and change all users. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: zynqmp: Enable DM and OF bindingMichal Simek2015-11-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | SPI requires DM and OF that's why enable DM for ZynqMP and start to use configuration based on embedded OF. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | arm: zynq: dts: Add U-Boot device tree additionsSimon Glass2015-11-0411-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mark some device tree nodes so that they are available before relocation. This enables driver model to find these automatically. In the case of SPL it ensures that these nodes will be retained in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | dm: arm: zynq: Enable device tree control in SPLSimon Glass2015-11-042-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | Move to using device tree control in SPL so that we can use the same driver code in both SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | arm: zynq: Support the debug UARTSimon Glass2015-11-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | arm: zynq: Drop unnecessary code in SPL board_init_f()Simon Glass2015-11-041-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to the new way of starting up SPL. Clearing of BSS and calling board_init_r() is now handled by crt0.S. Also tidy up the header include order. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: zynqmp: Add DTS for ep108 boardMichal Simek2015-11-044-0/+963
| | | | | | | | | | | | | | | | | | | | | Add DTS for ep108 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot
* | | mmc: atmel: Add atmel sdhci supportWenyou Yang2015-11-031-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: clock: Add the generated clock supportWenyou Yang2015-11-033-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some peripherals may need a second clock source that may be different from the system clock. This second clock is the generated clock (GCK) and is managed by the PMC via PMC_PCR. For simplicity, the clock source of the GCK is fixed to PLLA_CLK. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: Change the Chip ID registers' addressesWenyou Yang2015-11-034-7/+10
|/ / | | | | | | | | | | | | | | Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: simplify spl board_init_f functionJosh Wu2015-11-011-5/+0
|/ | | | | | | | | crt0.S do both memset the bss section and call board_init_r for us, so remove them from board_init_f(). Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-3051-620/+2361
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| * arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-295-0/+93
| | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Enable secondary coresHou Zhiqiang2015-10-292-0/+15
| | | | | | | | | | | | | | | | | | | | After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-291-1/+21
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-293-0/+41
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-292-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-293-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| * armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-2913-0/+1221
| | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-2931-509/+690
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-291-21/+82
| | | | | | | | | | | | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: enable snooping for CAAM transactionshoria.geanta@freescale.com2015-10-292-0/+4
| | | | | | | | | | | | | | | | | | | | | | Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Data types defined for 64 bit physical addressAneesh Bansal2015-10-292-5/+9
| | | | | | | | | | | | | | | | Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang2015-10-291-1/+1
| | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | dts: zed: Enable zynq qspi controller nodeJagan Teki2015-10-251-0/+5
| | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zed board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | dts: zc770-xm010: Enable zynq qspi controller nodeJagan Teki2015-10-251-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc770-xm010 board. => sf probe 0 -- bus1 for selecting qspi controller => sf probe 1 -- bus0 for selecting spi controller Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | dts: zc706: Enable zynq qspi controller nodeJagan Teki2015-10-251-0/+5
| | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc706 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | dts: zc702: Enable zynq qspi controller nodeJagan Teki2015-10-251-0/+5
| | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc702 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | dts: microzed: Enable zynq qspi controller nodeJagan Teki2015-10-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | dts: zynq: Add zynq qspi controller nodesJagan Teki2015-10-251-0/+12
|/ | | | | | | | | | This patch adds zynq qspi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* arm, powerpc: select SYS_GENERIC_BOARDMasahiro Yamada2015-10-241-1/+0
| | | | | | | | | | | We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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