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| | * | | am335x: Enable RTC 32K OSC clockVaibhav Hiremath2012-10-254-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * | | am33xx: Enable DDR3 for DDR3 version of beagleboneJoel A Fernandes2012-10-231-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK. Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Jason Kridner <jdk@ti.com>
| * | | | ARM : Remove unused CONFIG_DRIVER_SMC91111, CONFIG_DRIVER_LAN91C96Ashok2012-10-221-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused CONFIG_DRIVER_SMC91111,CONFIG_DRIVER_LAN91C96, if required implement smc_set_mac_addr() in board init. Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by: Tom Rini <trini@ti.com>
| * | | | common: Discard the __u_boot_cmd sectionMarek Vasut2012-10-225-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command declaration now uses the new LG-array method to generate list of commands. Thus the __u_boot_cmd section is now superseded and redundant and therefore can be removed. Also, remove externed symbols associated with this section from include/command.h . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
| * | | | common: Convert the U-Boot commands to LG-arraysMarek Vasut2012-10-221-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts the old method of creating a list of command onto the new LG-arrays code. The old u_boot_cmd section is converted to new u_boot_list_cmd subsection and LG-array macros used as needed. Minor adjustments had to be made to the common code to work with the LG-array macros, mostly the fixup_cmdtable() calls are now passed the ll_entry_start and ll_entry_count instead of linker-generated symbols. The command.c had to be adjusted as well so it would use the newly introduced LG-array API instead of directly using linker-generated symbols. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
| * | | | common: Add .u_boot_list into all linker filesMarek Vasut2012-10-226-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add section for the linker-generated lists into all possible linker files, so that everyone can easily use these lists. This is mostly a mechanical adjustment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
| * | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-10-1913-3337/+23
| |\ \ \ \ | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial_lh7a40x.c Signed-off-by: Tom Rini <trini@ti.com>
| | * | | arm: fdt: Relocate fdt along with other dataSimon Glass2012-10-191-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than leave the fdt down next to the code/data, we really should relocate it along with everything else. For CONFIG_OF_EMBED this happens automatically, but for CONFIG_OF_SEPARATE it does not. Add code to copy the fdt and point to the new copy after relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
| | * | | dm: Move s3c24xx USB driver to a proper placeMarek Vasut2012-10-184-2240/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: David Müller <d.mueller@elsoft.ch> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| | * | | dm: wdt: arm: Move tnetv107x into drivers/watchdog/Marek Vasut2012-10-182-181/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Oliver Brown <obrown@adventnetworks.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| | * | Remove lh7a40x cpu and serial driverAlbert ARIBAUD2012-10-166-916/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | arm: Change global data baudrate to intSimon Glass2012-10-192-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This does not need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | | mx25: Place common functions into sys_proto.hFabio Estevam2012-10-262-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | imx-regs.h is meant to contain SoC register definitions. Common SoC funtions should go to sys_proto.h instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | MX35: add support for woodburn boardStefano Babic2012-10-263-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The woodburn board is based on the MX35 SOC. Support for both external (NOR) and internal (SD Card) boot mode are added. It uses the generic SPL framework to implement the internal boot mode. The following peripherals are supported: - Ethernet (FEC) - SD Card - NAND (512 MB) - NOR Flash In the internal boot mode, a simple imximage header is generated to set the address in internal RAM where the SOC must copy the SPL code. The initial setup is then demanded to the SPL itself. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | ARM: Add SPL target to arm1136Stefano Babic2012-10-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds SPL for the arm1136 architecture and inserts SPL (the produced binary) to clobber target in the main Makefile. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | MX35: Add soc_boot_mode and soc_boot_device to MX35Stefano Babic2012-10-264-0/+206
| | | | | | | | | | | | | | | | | | | | | The functions are required to use the generic SPL Framework. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORKStefano Babic2012-10-261-0/+2
| | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | ARM: Fix start.S when used with SPL in arm1136Stefano Babic2012-10-261-11/+20
| |/ |/| | | | | | | | | | | | | This patch modifies start.S for the arm1136 to make it conform to start.S in armv7 architecture, to make it usable if the SPL framework is used. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | MX5: fix warning in clock.cStefano Babic2012-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | Patch fix warnings compiling with ELDK-4.2: clock.c: In function 'get_standard_pll_sel_clk': clock.c:341: warning: 'freq' may be used uninitialized in this function Reported-by : Marek Vasut <marex@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de>
* | mx5: Add workaround for ARM erratum ID 468414Fabio Estevam2012-10-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-172-33/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx5: lowlevel_init.S: Split init_clock macroFabio Estevam2012-10-171-30/+65
| | | | | | | | | | | | | | | | | | | | | | init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx25: Clean up imx-regs.hBenoît Thébaudeau2012-10-161-3/+3
| | | | | | | | | | | | | | | | | | | | Clean up i.MX25 imx-regs.h: - Update mx31 imx-regs.h filename. - Test for __KERNEL_STRICT_NAMES just in case. - Define internal RAM size. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | i.MX6: add HDMI transmitter register declarations from kernel WIP.Eric Nelson2012-10-161-0/+1053
| | | | | | | | | | | | | | | | Original source from Pengutronix HDMI driver work: http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commitdiff;h=72c31cd67ac880bd90785af86f8e46f8ea7b3bb0 Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: set drive strength for parallel RGB padsEric Nelson2012-10-161-29/+29
| | | | | | | | | | | | Default drive strength is disabled and won't function. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX: iomux: input pad array can be constEric Nelson2012-10-162-3/+5
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
* | mx6qsabreauto: Pass the board revision to the kernelFabio Estevam2012-10-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | The kernel from Freescale expects that the bootloader passes the board revision. Read the board revision and pass it via get_board_rev(). Without passing the board revision the kernel does not operate properly as the initialization of peripherals are different in revA versus revB boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx35: Fix eSDHC clocksBenoît Thébaudeau2012-10-162-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Each eSDHC instance has a dedicated clock. gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx35: Clean up lowlevel_initBenoît Thébaudeau2012-10-161-96/+95
|/ | | | | | | | | | | | Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. - Use macro parameters with default values instead of #define'd configs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'agust@denx.de-next' of git://git.denx.de/u-boot-stagingTom Rini2012-10-151-0/+3
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| * bootstage: Store boot timings in device treeSimon Glass2012-10-021-0/+3
| | | | | | | | | | | | | | | | Add an option, CONFIG_BOOTSTAGE_FDT to pass boot timings to the kernel in the device tree, if available. To use this, you must have CONFIG_OF_LIBFDT defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mx25: Clean up lowlevel_initBenoît Thébaudeau2012-10-151-22/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up mx25 lowlevel_init: - Add comments. - Do not use write32 repeatedly with the same value in order not to increase code size. - Make register values configurable. - Use macro parameters with default values instead of literal constants. - Use defined macros instead of duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Matthias Weisser <weisserm@arcor.de>
* | mx31: Fix PDR0_CSI_PODFBenoît Thébaudeau2012-10-151-2/+4
| | | | | | | | | | | | | | | | | | | | The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx35: Define MAX and AIPS registersBenoît Thébaudeau2012-10-152-1/+84
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx31: Add more CCM access macrosBenoît Thébaudeau2012-10-151-0/+10
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5: Optimize lowlevel_init code sizeBenoît Thébaudeau2012-10-151-53/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx25: Fix eSDHC supportBenoît Thébaudeau2012-10-151-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do with mxcmmc. Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx25: Define cpu_eth_init() only if neededBenoît Thébaudeau2012-10-151-4/+6
| | | | | | | | | | | | | | | | The FEC is the only SoC Ethernet support available on i.MX25, so define cpu_eth_init() only for it instead of returning a misleading success code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clocks APIBenoît Thébaudeau2012-10-152-9/+6
| | | | | | | | | | | | | | | | Use the standard mxc_get_clock() instead of exporting internal functions and using literal constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-152-3/+2
| | | | | | | | | | | | | | | | | | | | mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock. Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG clock, so remove the duplicated code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Define more standard clocksBenoît Thébaudeau2012-10-152-0/+15
| | | | | | | | | | | | | | Define AHB, IPG and CSPI clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clock calculationsBenoît Thébaudeau2012-10-151-4/+4
| | | | | | | | | | | | | | | | Avoid possible overflow in clock calculations, and do not waste calls to lldiv() to divide simple ulongs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Fix decode_pllBenoît Thébaudeau2012-10-151-3/+6
| | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-153-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx51: Fix I2C clock ID checkBenoît Thébaudeau2012-10-151-1/+5
| | | | | | | | | | | | | | There are only 2 I²C instances on i.MX51, but 3 on i.MX53. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-151-3/+2
| | | | | | | | | | | | | | | | | | The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Simplify imx_get_cspiclk()Benoît Thébaudeau2012-10-151-20/+3
| | | | | | | | | | | | | | | | | | The code handling the dividers was duplicated for each possible input clock, and this function can benefit from the newly introduced get_standard_pll_sel_clk() function instead of duplicating this mux handling code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_uart_clk()Benoît Thébaudeau2012-10-151-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_ipg_per_clk()Benoît Thébaudeau2012-10-151-3/+7
| | | | | | | | | | | | | | | | | | | | | | This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case CCM.CBCMR.perclk_lp_apm_sel is set. It also fixes I²C support. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_periph_clk()Benoît Thébaudeau2012-10-151-20/+22
| | | | | | | | | | | | | | | | | | | | In the case periph_clk comes from periph_apm_clk, the latter is selected by the CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in this case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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