talos-obmc-uboot - Talos™ II U-Boot sources for OpenBMC

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper	Masahiro Yamada	2015-03-24	1	-0/+5
\| \| \| \| \| \| \| \| \| \| \| \|	The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
*	ARM: UniPhier: add empty lowlevel_init to U-boot proper	Masahiro Yamada	2015-03-24	1	-0/+12
	To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>