| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ARM: uniphier: insert dsb barrier to ensure visibility of store | Masahiro Yamada | 2016-06-09 | 1 | -2/+2 |
| | | | | | | | | | | | | | I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> | ||||
| * | ARM: uniphier: add PH1-LD20 SoC support | Masahiro Yamada | 2016-04-24 | 6 | -0/+167 |
| This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> | |||||
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index : talos-obmc-uboot | |
| Talos™ II U-Boot sources for OpenBMC | Raptor Computing Systems |
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