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* rockchip: Add basic support for jerrySimon Glass2015-09-021-0/+10
| | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-021-0/+10
| | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add core SoC start-up codeSimon Glass2015-09-026-0/+421
| | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SDRAM initSimon Glass2015-09-022-0/+879
| | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add a simple syscon driverSimon Glass2015-09-022-0/+26
| | | | | | Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SoC reset driverSimon Glass2015-09-022-0/+54
We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
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