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* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-141-1/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: correct sdram settingChris Zhong2016-03-101-7/+7
| | | | | | | | | | | | | | | The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, and it expects uboot to store the value using a same protocol. But now the ddr setting value is different with DMC, so if you enable the DMC, system would crash in kernel. Correct the sdram setting here, according to the requirements of kernel. [0] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c Signed-off-by: Chris Zhong <zyw@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add support for Raxda Rock 2Simon Glass2016-01-211-0/+10
| | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-212-0/+45
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-211-14/+3
| | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-211-2/+2
| | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: reset: Use the rk_clr/setreg() interfaceSimon Glass2016-01-211-2/+2
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use the rk_clr/setreg() interfaceSimon Glass2016-01-211-4/+3
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "rockchip: Add max spl size & spl header configs"Jeffy Chen2015-12-131-6/+0
| | | | | | | This reverts commit 10b4615f9d7e177ec7fe644fbb2616e0e0956f6e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add max spl size & spl header configsJeffy Chen2015-12-011-0/+6
| | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-011-0/+3
| | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for jerrySimon Glass2015-09-021-0/+10
| | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-021-0/+10
| | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add core SoC start-up codeSimon Glass2015-09-021-0/+6
| | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SDRAM initSimon Glass2015-09-022-0/+879
| | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add a simple syscon driverSimon Glass2015-09-022-0/+26
| | | | | | Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SoC reset driverSimon Glass2015-09-022-0/+54
We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
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