| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rockchip: Add a simple 'clock' command | Simon Glass | 2016-01-21 | 1 | -0/+24 |
| | | | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org> | ||||
| * | rockchip: Don't skip low-level init | Simon Glass | 2016-01-21 | 1 | -0/+4 |
| | | | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> | ||||
| * | rockchip: rk3036: Add core Soc start-up code | huang lin | 2015-12-01 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288 | ||||
| * | rockchip: Add core SoC start-up code | Simon Glass | 2015-09-02 | 1 | -0/+46 |
| Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org> | |||||
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index : talos-obmc-uboot | |
| Talos™ II U-Boot sources for OpenBMC | Raptor Computing Systems |
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