summaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm
Commit message (Collapse)AuthorAgeFilesLines
* mx5: fix get_reset_causeStefano Babic2015-03-051-1/+0
| | | | | | | | | | | | commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets get_reset_cause() as static, but this conflicts with mx5 where its prototype is in sys_proto.h. Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco, factorizing the call for this board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org>
* imx6: Added DEK blob generator commandRaul Cardenas2015-03-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02120-10045/+239
|\
| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-258-3/+157
| |\
| | * arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-242-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm/ls102xa: use a array to define pexmscportsrMinghuan Lian2015-02-241-2/+1
| | | | | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm/ls102xa: create TLB to map PCIe regionMinghuan Lian2015-02-241-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * arm: ls102xa: Define default values for some CCSR macrosAlison Wang2015-02-241-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: Enable erratum workround for A008514York Sun2015-02-241-0/+1
| | | | | | | | | | | | | | | | | | Erratum A008514 appleis to ls2085a. Signed-off-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: Enable workaround for A008336York Sun2015-02-241-0/+4
| | | | | | | | | | | | | | | | | | Erratum A008336 applied to LS2085A. Signed-off-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: Add support for second DDR clockYork Sun2015-02-242-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
| | * driver/ddr/fsl: Add workaround for A008336York Sun2015-02-241-0/+5
| | | | | | | | | | | | | | | | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
| | * armv8/fsl-lsch3: Change normal memory shareabilityYork Sun2015-02-241-1/+2
| | | | | | | | | | | | | | | | | | | | | According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| | * fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accessesBhupesh Sharma2015-02-241-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: remove tnetv107x board supportMasahiro Yamada2015-02-243-504/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chan-Taek Park <c-park@ti.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: remove a320evb board supportMasahiro Yamada2015-02-241-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Po-Yu Chuang <ratbert@faraday-tech.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: remove cm4008 and cm41xx board supportMasahiro Yamada2015-02-241-294/+0
| | | | | | | | | | | | | | | | | | | | | | | | These are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Greg Ungerer <greg.ungerer@opengear.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: remove dkb board supportMasahiro Yamada2015-02-245-207/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Lei Wen <leiwen@marvell.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: remove jadecpu board supportMasahiro Yamada2015-02-242-614/+0
| |/ | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>
| * Merge git://git.denx.de/u-boot-sunxiTom Rini2015-02-211-0/+9
| |\
| | * sunxi: Fix sun5i mbus speed when booting old kernelsHans de Goede2015-02-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, halving the mbus frequency, so set it to 300 MHz ourselves and base the mbus divider on that. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | rpi: add support for Raspberry Pi 2 model BStephen Warren2015-02-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | USB doesn't seem to work yet; the controller detects the on-board Hub/ Ethernet device but can't read the descriptors from it. I haven't investigated yet. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | bcm2836 SoC support (used in Raspberry Pi 2 model B)Stephen Warren2015-02-215-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bcm2835 and bcm2836 are essentially identical, except: - The CPU is an ARM1176 v.s. a quad-core Cortex-A7. - The physical address of many IO controllers has moved. Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH), update the existing bcm2835 code to handle the minor differences, and plumb it into the ARMv7 CPU architecture. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | bcm2835/rpi: add SPDX license tags for some filesStephen Warren2015-02-213-33/+3
| | | | | | | | | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | ARM: keystone: move SoC headers to mach-keystone/include/machMasahiro Yamada2015-02-2115-1279/+0
| | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-keystone/* -> arch/arm/mach-keystone/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
| * | ARM: orion5x: move SoC headers to mach-orion5x/include/machMasahiro Yamada2015-02-213-334/+0
| | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-orion5x/* -> arch/arm/mach-orion5x/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | ARM: nomadik: move SoC headers to mach-nomadik/include/machMasahiro Yamada2015-02-212-76/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-nomadik/* -> arch/arm/mach-nomadik/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> Cc: Alessandro Rubini <rubini@unipv.it>
| * | ARM: kirkwood: move SoC headers to mach-kirkwood/include/machMasahiro Yamada2015-02-217-761/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-kirkwood/* -> arch/arm/mach-kirkwood/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | ARM: davinci: move SoC headers to mach-davinci/include/machMasahiro Yamada2015-02-2116-1587/+0
| | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-davinci/* -> arch/arm/mach-davinci/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
| * | ARM: at91: move SoC headers to mach-at91/include/machMasahiro Yamada2015-02-2144-4295/+0
| |/ | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-at91/* -> arch/arm/mach-at91/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-02-174-26/+31
| |\
| | * sunxi: Normalise FEL supportSimon Glass2015-02-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove these. This series is available at u-boot-dm, branch sunxi-working. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * arm: spl: Provide for a board-specific loaderSimon Glass2015-02-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a special way of loading U-Boot that does not fit with the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot is loaded over USB. Add a CONFIG option and boot mode for this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * arm: Allow lr to be saved by board codeSimon Glass2015-02-161-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * sunxi: dram: Un-inline dram helper functionsHans de Goede2015-02-161-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the dram helper functions to a separate C file, rather then having them as inline helpers in dram.h. This saves 144 bytes in the .text segment for sun6i builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: lpc3250: config: add generic board supportVladimir Zapolskiy2015-02-161-1/+3
| | | | | | | | | | | | | | | | | | | | | The only LPC3250 board works fine with enabled generic board support, add CONFIG_SYS_GENERIC_BOARD right into the arch config header. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| * | keystone2: ddr3: eliminate using global ddr3_size variableVitaly Andrianov2015-02-161-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table. This patch removes the global ddr3_size variable and uses local one instead. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
| * | clock_am43xx:Set the MAC clock to /5 for OPP100Steve Kipisz2015-02-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
| * | ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register valueLokesh Vutla2015-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | Merge git://git.denx.de/u-boot-samsungTom Rini2015-02-131-0/+4
| |\ \
| | * | Exynos542x: Add and enable get_periph_rate supportAkshay Saraswat2015-02-131-0/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: at91: Drop use of ATMEL_PIO_PORTS in the header fileSimon Glass2015-02-121-8/+4
| |/ | | | | | | | | | | | | | | With driver model the number of PIO ports is defined by platform data, so remove it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | imx: mx6sl: Extend USDHC SD2 pins to support 8-wire useOtavio Salvador2015-02-231-0/+5
| | | | | | | | | | | | This adds the DATA[4-7] and RST pin definitions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | imx:mx6sl add I2c pad settingsPeng Fan2015-02-231-0/+5
| | | | | | | | | | | | A few pad settings are I2C1 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | ARM: i.MX: provide access to reset cause through get_imx_reset_cause()Eric Nelson2015-02-171-0/+2
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-171-0/+2
|/ | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-02-1010-217/+83
|\
| * arm, at91: add reset controller status registerHeiko Schocher2015-02-071-0/+2
| | | | | | | | | | | | | | add reset controller status register Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: cleanup: remove at91cap9 related codeBo Shen2015-02-075-217/+3
| | | | | | | | | | | | | | | | | | | | | | As the at91cap9adk board is removed by commit: b5508344 (ARM: remove broken "at91cap9adk" board), so the at91cap9 code is not used anymore, and also the document for at91cap9 can not be found on www.atmel.com, so remove the at91cap9 related code. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
OpenPOWER on IntegriCloud