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* sunxi: dram: Configurable DQS gating window mode and delaySiarhei Siamashka2014-08-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware DQS gate training is a bit unreliable and does not always find the best delay settings. So we introduce a 32-bit 'dqs_gating_delay' variable, where each byte encodes the DQS gating delay for each byte lane. The delay granularity is 1/4 cycle. Also we allow to enable the active DQS gating window mode, which works better than the passive mode in practice. The DDR3 spec says that there is a 0.9 cycles preamble and 0.3 cycle postamble. The DQS window has to be opened during preamble and closed during postamble. In the passive window mode, the gating window is opened and closed by just using the gating delay settings. And because of the 1/4 cycle delay granularity, accurately hitting the 0.3 cycle long postamble is a bit tough. In the active window mode, the gating window is auto-closing with the help of monitoring the DQS line, which relaxes the gating delay accuracy requirements. But the hardware DQS gate training is still performed in the passive window mode. It is a more strict test, which is reducing the results variance compared to the training with active window mode. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'Siarhei Siamashka2014-08-121-3/+0
| | | | | | | | It is going to be useful in more than one place. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Improve DQS gate data training error handlingSiarhei Siamashka2014-08-121-1/+3
| | | | | | | | | | | The stale error status should be cleared for all sun4i/sun5i/sun7i hardware and not just for sun7i. Also there are two types of DQS gate training errors ("found no result" and "found more than one possible result"). Both are handled now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)Siarhei Siamashka2014-08-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed. Allwinner A13 uses only 16-bit data bus width to connect the external DRAM, which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so it does not make much sense to clock a wider internal bus at a very high speed. The Allwinner A13 manual specifies 300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer sun7i hardware (Allwinner A20) has a full width 32-bit external memory interface again, but still keeps the MBUS clock speed configurable. Clocking MBUS too low inhibits memory performance and one has to find the optimal MBUS/DRAM clock speed ratio, which may depend on many factors: http://linux-sunxi.org/A10_DRAM_Controller_Performance This patch introduces a new 'mbus_clock' parameter for the 'dram_para' struct and uses it as a desired MBUS clock speed target. If 'mbus_clock' is not set, 300 MHz is used by default to match the older hardcoded settings. PLL5P and PLL6 are both evaluated as possible clock sources. Preferring the one, which can provide higher clock frequency that is lower or equal to the 'mbus_clock' target. In the case of a tie, PLL5P has higher priority. Attempting to set the MBUS clock speed has no effect on sun4i, but does no harm either. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Re-introduce the impedance calibration ond ODTSiarhei Siamashka2014-08-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM controller allows to configure impedance either by using the calibration against an external high precision 240 ohm resistor, or by skipping the calibration and loading pre-defined data. The DRAM controller register guide is available here: http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0 The new code supports both of the impedance configuration modes: - If the higher bits of the 'zq' parameter in the 'dram_para' struct are zero, then the lowest 8 bits are used as the ZPROG value, where two divisors encoded in lower and higher 4 bits. One divisor is used for calibrating the termination impedance, and another is used for the output impedance. - If bits 27:8 in the 'zq' parameters are non-zero, then they are used as the pre-defined ZDATA value instead of performing the ZQ calibration. Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS lines individually. Enabling ODT for both DQ and DQS means that the 'odt_en' parameter needs to be set to 3. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: add defines to control USB Host clocks/resetsRoman Byshko2014-07-311-0/+4
| | | | | | | | | | | The commit adds three defines which will be used in the EHCI driver to enable USB clock and assert reset controllers of the corresponding PHYs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-311-4/+7
| | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: add gpio driverIan Campbell2014-07-181-0/+2
| | | | | | | | | | | | | | | This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well as providing the common gpio API (gpio_request/free, direction in/out, get/set etc). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Henrik Nordström <henrik@henriknordstrom.net> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add i2c supportHans de Goede2014-07-181-0/+15
| | | | | | | | | | | | | Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
* sunxi: Implement reset_cpuHans de Goede2014-07-061-0/+5
| | | | | | | There is no way to reset the cpu, so use the watchdog for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* arm: spl: fix include guardJeroen Hofstee2014-07-051-1/+1
| | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* sunxi: mmc supportIan Campbell2014-05-251-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote: > > + case 1: > > +#if CONFIG_MMC1_PG > Are you sure that this is correct and shouldn't be: > > +#ifdef CONFIG_MMC1_PG > > ? It's "correct" in so far as it works (the boards.cfg config stuff #defines things to 1), but I think you are right that it isn't the preferred style. But... > A quick scan through this patch series shows that this define > is not set at all. Perhaps its outdated? Or is it used to support > some other sunxi SoC? Not sure, perhaps it should be removed for > now. ...I had thought that it was to support some other board which wasn't being upstreamed right now, so eventually useful and harmless for now, but I've just checked and it isn't actually used by any of the boards in u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it. Rather than resend the entire series, here is v5.1 of this patch. > Other than this please add my: > > Reviewed-by: Stefan Roese <sr@denx.de> Thanks! 8<--------------------------------- >From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001 From: Ian Campbell <ijc@hellion.org.uk> Date: Fri, 7 Mar 2014 04:29:39 +0000 Subject: [PATCH v5.1 7/8] sunxi: mmc support This adds support for the MMC controller on the Allwinner A20 (sun7i) processor. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Cc: Aaron Maoye <leafy.myeh@allwinnertech.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: Tom Rini <trini@ti.com>
* sunxi: add sun7i cpu, board and start of day supportIan Campbell2014-05-252-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson <ats@offog.org> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luc Verhaegen <libv@skynet.be> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Patrick Wood <patrickhwood@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* sunxi: add sun7i dram setup supportIan Campbell2014-05-251-0/+179
| | | | | | | | | | | | | | | | | | | | This patch adds DRAM initialisation support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* sunxi: add sun7i pinmux and gpio supportIan Campbell2014-05-251-0/+147
| | | | | | | | | | | | | | | | | | This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* sunxi: add sun7i clocks and timer support.Ian Campbell2014-05-254-0/+389
This patch adds the basic clocks and timer support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Some of the code here is common to multiple sunxi subarchtectures, hence files are named sun4i which is the earliest similar variant. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
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