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* ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-101-257/+0
| | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-101-28/+0
| | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-111-5/+0
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-111-45/+0
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-111-478/+46
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: DPLL core lock for OMAP5432Lokesh Vutla2012-07-071-0/+5
| | | | | | | No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: palmas: Configure nominal opp vdd valuesSRICHARAN R2012-05-151-0/+1
| | | | | | | | | | | The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.html Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3+: Introduce generic logic for OMAP voltage controllerNishanth Menon2012-05-151-15/+0
| | | | | | | | | | | | | | | | | | | | OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* omap4_panda: Initialize the USB phyChris Lalancette2011-12-191-0/+63
| | | | | | | | | | During misc_init_r, make sure to setup the clocks properly for the USB hub on the pandaboard. With this in place, the USB hub and the ethernet works on the pandaboard. Signed-off-by: Chris Lalancette <clalancette@gmail.com> Acked-by: Aneesh V <aneesh@ti.com>
* omap4/5: Add support for booting with CH.Sricharan2011-11-151-0/+1
| | | | | | | | | | | | | | | | Configuration header(CH) is 512 byte header attached to an OMAP boot image that will help ROM code to initialize clocks, SDRAM etc and copy U-Boot directly into SDRAM. CH can help us in by-passing SPL and directly boot U-boot, hence it's an alternative for SPL. However, we intend to support both CH and SPL for OMAP4/5. Initialization done through CH is limited and is not equivalent to that done by SPL. So U-Boot has to distinguish between the two cases and handle them accordingly. This patch takes care of doing this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: clocks: Add clocks support for omap5 platform.Sricharan2011-11-151-0/+22
| | | | | | | | | | | | Adding the correct configurations required for dplls, clocks, for omap5 Soc. Also changes are done to retain some part of the code common for OMAP4/5 and move only the remaining to the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: fix build warning due to signed unsigned comparisonAneesh V2011-09-041-6/+6
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4: clock init support for omap4460Aneesh V2011-08-031-1/+11
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: support TPS programmingAneesh V2011-08-031-0/+16
| | | | | | | | | | | TPS62361 is the new power supply used in OMAP4460 that supplies vdd_mpu. VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies vdd_iva. VCORE3 is not used in OMAP4460. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add sdram init supportAneesh V2011-08-031-4/+4
| | | | | | | Add support for the SDRAM controller (EMIF). Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add clock supportAneesh V2011-08-031-0/+664
Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules 3. Setting up the right voltage on voltage rails This work draws upon previous work done for x-loader by: Santosh Shilimkar <santosh.shilimkar@ti.com> Rajendra Nayak <rnayak@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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