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path: root/arch/arm/include/asm/arch-mx5/clock.h
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* arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-031-0/+1
| | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* usb: ehci-mx5: Use 'bool' instead of 'unsigned char'Fabio Estevam2013-08-261-3/+3
| | | | | | | The 'enable' argument can be better expressed as boolean. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* arm: mx5: Add NAND clock handlingMarek Vasut2013-05-051-0/+1
| | | | | | | | | | | | | Augment the MX5 clock code with function to enable and configure NFC clock. This is necessary to get NFC working on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-151-0/+4
| | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-151-1/+2
| | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-151-0/+14
| | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-151-0/+1
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Undeclare imx_decode_pll()Benoît Thébaudeau2012-09-011-2/+0
| | | | | | | The imx_decode_pll() function does not exist for mx5, so remove its declaration. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: add i2c.c for bus recovery supportTroy Kisky2012-07-311-0/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx5: Add clock config interfaceFabio Estevam2012-05-151-1/+4
| | | | | | | | | | | mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX53: add function to set SATA clock to internalStefano Babic2012-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | The MX53 SATA interface can use an internal clock (USB PHY1) instead of an external clock. This is an undocumented feature, but used on most Freescale's evaluation boards, such as MX53-loco. As stated by Freescale's support: Fuses (but not pins) may be used to configure SATA clocks. Particularly the i.MX53 Fuse_Map contains the next information about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) '00' - 100MHz (External) '01' - 50MHz (External) '10' - 120MHz, internal (USB PHY) '11' - Reserved Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: Add definitions for SATA controllerStefano Babic2012-05-151-0/+1
| | | | | | | | | Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com>
* USB: MX5: add helper functions to enable USB clocksWolfgang Grandegger2011-12-111-0/+5
| | | | | | | | | | Signed-off-by: Wolfgang Grandegger <wg@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Remy Bohmer <linux@bohmer.net> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Jason Liu <r64343@freescale.com> V2: Fix spacing in crm_regs.h
* MX5: rename mx51 to mx5Jason Liu2010-10-181-0/+43
Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343@freescale.com>
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