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path: root/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
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* armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-201-0/+110
| | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha2015-07-201-0/+4
| | | | | | | | | call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu2015-04-231-0/+7
| | | | | | | This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Use correct compatible for serial clock fixupScott Wood2015-04-231-1/+1
| | | | | | | | The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodesBhupesh Sharma2015-02-241-0/+5
| | | | | | | | This patch adds the fdt-fixup logic for the clock frequency of the NS16550A related device tree nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARMv8/fsl-lsch3: Patch cpu node properties in DT for online coresArnab Basu2015-02-241-9/+14
| | | | | | | | U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-251-0/+58
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
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