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* arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese2014-12-061-2/+2
| | | | | | | | | | | As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add socfpga_spim_enable() to reset_manager.cStefan Roese2014-11-071-0/+9
| | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: reset: Add function to reset FPGA bridgesMarek Vasut2014-10-061-0/+38
| | | | | | | | | | | | | | | | Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: reset: Add EMAC reset functionsMarek Vasut2014-10-061-0/+17
| | | | | | | | | | | | | | | Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add watchdog disable for socfpgaPavel Machek2014-10-061-0/+12
| | | | | | | | | | | | | | | | This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
* socfpga: Creating driver for Reset ManagerChin Liang See2013-09-061-0/+39
Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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