Commit message (Collapse) | Author | Age | Files | Lines | |
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* | socfpga: Fix SOCFPGA build error for Altera dev kit | Chin Liang See | 2014-08-29 | 1 | -1/+0 |
| | | | | | | | | | | | | | To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> | ||||
* | socfpga: fix clock manager register definition | Pavel Machek | 2014-08-29 | 1 | -56/+56 |
| | | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de> | ||||
* | socfpga: Adding Clock Manager driver | Chin Liang See | 2014-04-07 | 1 | -0/+361 |
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de> |