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* arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specifiedTim Harvey2015-05-191-1/+2
| | | | | | | | | | | | | Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* arm: mx6: ddr3: Remove dead codeNikolay Dimitrov2015-05-151-22/+0
| | | | | | | imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling higher data rates. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
* arm: mx6: Clamp MMDC and DDR3 clocks for timing calculationsNikolay Dimitrov2015-05-151-7/+23
| | | | | | | | | | | | | | | | This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed. Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
* arm: mx6: ddr: add pd_fast_exit flag to system informationTim Harvey2015-04-221-1/+6
| | | | | | | | | | | DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit. In slow-exit mode the DLL is off but in some quiescent state that makes it easy to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK). In fast-exist mode the DLL is maintained such that it is ready again in about 3tCK. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx:mx6sx add dram io configure for mx6sxPeng Fan2015-01-221-14/+82
| | | | | | | | | | | Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-241-20/+20
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov2014-09-091-3/+1
| | | | | | | | | | | | | | | | Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov2014-09-091-0/+1
| | | | | | | | | | | | | | | | According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
* arm: mx6: ddr: do not write into reserved bitNikita Kiryanov2014-09-091-1/+1
| | | | | | | | | Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: ddr: cleanupNikita Kiryanov2014-09-091-141/+137
| | | | | | | | | No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* ARM: mx6: Handle the MMDCx_MDCTL COL field capricesMarek Vasut2014-08-201-1/+7
| | | | | | | | | The COL field value cannot be easily calculated from the desired column number. Instead, there are special cases for that, see the datasheet, MMDCx_MDCTL field description, field COL . Cater for those special cases. Signed-off-by: Marek Vasut <marex@denx.de>
* mx6: add mmdc configuration for MX6Q/MX6DLTim Harvey2014-06-061-0/+490
- add function for configuring iomux based on board-specific regs - add function for configuring mmdc based on board-specific and chip-specific data Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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