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* arm: bugfix: replace ble with blo in start.S filesAlbert Aribaud2010-10-111-4/+4
| | | | | | | | | | | Generalized misuse of ble within relocation and bss initialization loops caused one iteration too many. Instead of ble ('branch if lower or equal'), use blo ('branch if lower'). While we're at it, fix all 'addreee' typos. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* ARM: implement relocation for ARM11Heiko Schocher2010-09-192-1/+214
| | | | | | | | | | | | Change the implementation for ARM11 to relocate the code to an arbitrary address in RAM. Tested on the qong board. Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM (ARM11): add data cache support, test on Qong boardHeiko Schocher2010-09-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Add data cache support for arm1136 systems. Enable "cache" command on Qong board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 177s 95s 43s = x 4.1 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 1.54s 0.95s 0.18s = x 8.6 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM: Align stack to 8 bytesVitaly Kuzmichev2010-06-221-0/+1
| | | | | | | | | | | | | The ARM ABI requires that the stack be aligned to 8 bytes as it is noted in Procedure Call Standard for the ARM Architecture: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html Unaligned SP also causes the problem with variable-length arrays allocation when VLA address becomes less than stack pointer during aligning of this address, so the next 'push' in the stack overwrites first 4 bytes of VLA. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
* ARM1136: Fix cache_flush() error and correct cpu_init_crit() commentsGeorge G. Davis2010-06-012-2/+3
| | | | | | | | | | | | | | | The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com>
* ARM: */timer.c: fix spelling and vertical alignmentWolfgang Denk2010-05-212-12/+12
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* arm: Move cpu/$CPU to arch/arm/cpu/$CPUPeter Tyser2010-04-1312-0/+1282
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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