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* arc: significant cache reworkAlexey Brodkin2015-07-014-138/+295
| | | | | | | | | | | | | | | | | | [1] Align cache management functions to those in Linux kernel. I.e.: a) Use the same functions for all cache ops (D$ Inv/Flush) b) Split cache ops in 3 sub-functions: "before", "lineloop" and "after". That way we may re-use "before" and "after" functions for region and full cache ops. [2] Implement full-functional L2 (SLC) management. Before SLC was simply disabled early on boot. It's also possible to enable or disable L2 cache from config utility. [3] Disable/enable corresponding caches early on boot. So if U-Boot is configured to use caches they will be used at all times (this is useful in partucular for speed-up of relocation). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: implement slave cores kick-start for Linux kernelAlexey Brodkin2015-07-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | With new SMP-enabled CPUs with ARC HS38 cores and corresponding support in Linux kernel it's required to add basic SMP support in U-Boot. Currently we assume the one and only core starts execution after power-on. So most of things in U-Boot is handled in UP mode. But when U-Boot is used for loading and starting Linux kernel right before jumping to kernel's entry point U-Boot: [1] Sets all slave cores to jump to the same address [kernel's entry point] [2] Really starts all slav cores In ARC's implemetation of SMP in Linux kernel all cores are supposed to run the same start-up code. But only core with ID 0 (master core) processes further while others are looping waiting for master core to complete some initialization. That means it's safe to un-pause slave cores and let them execute kernel - they will wait for master anyway. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com>
* arc: fix separate compilation of start.oAlexey Brodkin2015-04-101-0/+1
| | | | | | | | | | | | | | | While testing "arc: make sure _start is in the beginning of .text section" I haven't done proper clean-up of built binaries and so missed another tiny bit that lead to the following error: --->8--- LD u-boot arc-linux-ld.bfd: cannot find arch/arc/lib/start.o Makefile:1107: recipe for target 'u-boot' failed make: *** [u-boot] Error 1 --->8--- Fix is trivial: put "start.o" in "extra-y". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: make sure _start is in the beginning of .text sectionAlexey Brodkin2015-04-101-1/+1
| | | | | | | | | | | | | | This is important to have entry point in the beginning of .text section because it allows simple loading and execution of U-Boot. For example pre-bootloader loads U-Boot in memory starting from offset 0x81000000 and then just jumps to the same address. Otherwise pre-bootloader would need to find-out where entry-point is. In its turn if it deals with binary image of U-Boot there's no way for pre-bootloader to get required value. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: add support for SLC (System Level Cache, AKA L2-cache)Alexey Brodkin2015-04-032-0/+50
| | | | | | | | | | | | | | ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATAAlexey Brodkin2015-04-031-0/+8
| | | | | | | | | | As discussed on mailing list we're drifting away from CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem() for global data. So do this for ARC architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: clean-up init procedureAlexey Brodkin2015-04-035-77/+63
| | | | | | | | | | | | | | | | Intention behind this work was elimination of as much assembly-written code as it is possible. In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc. It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86. Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
* arc: move low-level interrupt and exception handlers in a separate fileAlexey Brodkin2015-04-033-144/+152
| | | | | | | | This separation makes maintenance of code easier because those low-level interrupt- or exception handling routines are pretty static and usually require not much care while start-up code is a subject of modifications and enhancements. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: merge common start-up code between ARC and ARCv2Alexey Brodkin2015-04-032-0/+242
| | | | | | | | | | Even though ARCompact and ARCv2 are not binary compatible most of assembly instructions are used in both. With this change we'll get rid of duplicate code. Still IVTs are implemented differently so we're keeping them in separate files. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: cache - build invalidate_icache_all() and invalidate_dcache_all()Alexey Brodkin2015-04-031-4/+8
| | | | | | | | | | | | | | | | | always Make both invalidate_icache_all() and invalidate_dcache_all() available even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or CONFIG_SYS_ICACHE_OFF. This is useful because configuration of U-Boot may not match actual hardware features. Real board may have cache(s) but for some reason we may want to run U-Boot with cache(s) disabled (for example if some peripherals work improperly with existing drivers if data cache is enabled). So board may start with cache(s) enabled (that's the case for ARC cores with built-in caches) but early in U-Boot we disable cache(s) and make sure all contents of data cache gets flushed in RAM. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: build libgcc in U-BootAlexey Brodkin2015-02-094-0/+521
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This way we may have very limited set of functions implemented so we save some space. Also it allows us to build U-Boot for any ARC core with the same one toolchain because we don't rely on pre-built libgcc. For example: * we may use little-endian toolchain but build U-Boot for ether endianess * we may use non-multilibbed uClibc toolchain but build U-Boot for whatever ARC CPU flavour that current GCC supports Private libgcc built from generic C implementation contributes only 144 bytes to .text section so we don't see significant degradation of size: --->8--- $ arc-linux-size u-boot.libgcc-prebuilt text data bss dec hex filename 222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt $ arc-linux-size u-boot.libgcc-private text data bss dec hex filename 222361 24912 214820 462093 70d0d u-boot.libgcc-private --->8--- Also I don't notice visible performance degradation compared to pre-built libgcc (where at least "*div*" functions are had-written in assembly) on typical operations of downloading 10Mb uImage over TFTP and bootm. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: select cache settings via menuconfigAlexey Brodkin2015-02-091-0/+1
| | | | | | | | | | | This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: define and use PTAG AUX regs for MMUv3 onlyAlexey Brodkin2015-02-091-3/+3
| | | | | | DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: memcmp - fix zero-delay loop utilizationIgor Guryanov2015-02-091-0/+2
| | | | | | | | It's prohibited to put branch instruction in the very end of zero-delay loop. On execution this causes "Illegal instruction" exception. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* arc: move common sources in libraryAlexey Brodkin2015-01-156-0/+406
| | | | | | | | | | | | | | | | | | | "reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* arc: relocate - minor refactoring and clean-upAlexey Brodkin2015-01-151-11/+4
| | | | | | | | | | * use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* arc: introduce separate section for interrupt vector tableIgor Guryanov2015-01-152-2/+4
| | | | | | | | | | | | | | | | | | Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* arc: fix relocation for big-endian targetAlexey Brodkin2014-02-211-0/+4
| | | | | | | | | | | | | | | In case of little-endian ARC700 instructions (which may include target address) are encoded as middle-endian. That's why it's required to swap bytes after read and ten right before write back. But in case of big-endian ARC700 instructions are encoded as a plain big-endian. Thus no need for byte swapping. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Noam Camus <noamc@ezchip.com>
* arc: add library functionsAlexey Brodkin2014-02-0711-0/+846
These are library functions used by ARC700 architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
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