summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* ARM: uniphier: add ProXstream2 and PH1-LD6b supportMasahiro Yamada2015-09-2532-1/+733
| | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-Pro5 supportMasahiro Yamada2015-09-2526-1/+445
| | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: allow to enable multiple SoCsMasahiro Yamada2015-09-2580-478/+1070
| | | | | | | | | | | | | | | | | | | | Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove kernel parameter settings from environmentMasahiro Yamada2015-09-251-16/+6
| | | | | | | | | | | | Currently, console=ttyS0 is hard-coded in CONFIG_EXTRA_ENV_SETTINGS and it replaces the bootargs in the chosen node of the device tree passed to the kernel. This is not preferable because I am going to add some boards whose console is not ttyS0. Drop bootargs settings from U-Boot's environment and use the one in device tree by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: unify low-level debug init codeMasahiro Yamada2015-09-2511-152/+115
| | | | | | | Move init code of low-level debug into a single file. This is helpful to create an image that runs on multiple SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix glitch signal problem for low-level debugMasahiro Yamada2015-09-254-20/+20
| | | | | | | | | | | | | | | | | | | Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: delete unneeded input enable for low-level debugMasahiro Yamada2015-09-251-5/+0
| | | | | | | The UART I/O ports for PH1-Pro4 has no input enable controlling. This code is useless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-2510-32/+32
| | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARDMasahiro Yamada2015-09-251-0/+4
| | | | | | Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local fileMasahiro Yamada2015-09-253-16/+12
| | | | | | | It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally. Move them to a C file as local macros. Also, rename the C file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor LED functionMasahiro Yamada2015-09-259-128/+96
| | | | | | | | | | The macro, led_write(), is now only used in C sources. There is no more reason to keep the tricky assembly macro. Replace it with a new C function led_puts(). Also, rename board.h to micro-support-card.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove useless wrapper functionsMasahiro Yamada2015-09-253-17/+10
| | | | | | | | | | The wrapper functions, uniphier_board_*, are just making function calls complex. Remove them. Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD is disabled, so that prototype checking works. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused header fileMasahiro Yamada2015-09-251-24/+0
| | | | | | | This has been unused since commit f4e190e317b8 ("ARM: uniphier: enable SPL_OF_CONTROL"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: parse device tree to determine DRAM base and sizeMasahiro Yamada2015-09-253-26/+48
| | | | | | | Device tree specifies the available memory ranges in its "/memory" node. Use it to simplify the CONFIG defines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.hMasahiro Yamada2015-09-2511-119/+109
| | | | | | | To achieve the complete run-time configuration by device trees, ifdef conditionals in header files are not preferable. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: change the external bus address mappingMasahiro Yamada2015-09-255-20/+25
| | | | | | | | | | | | | | | | In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces 0x00000000 - 0x0fffffff 0x40000000 - 0x4fffffff are both mapped to the external bus (also called system bus), so either was OK. In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is assigned for the serial NOR interface. Going forward, use the latter for the external bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: enable setexpr commandMasahiro Yamada2015-09-254-4/+0
| | | | | | | This command will be used in the next commit to calculate base-offseted addresses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop DCC micro support card supportMasahiro Yamada2015-09-2516-311/+29
| | | | | | | | | | Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: drop ad-hoc input enable settingsMasahiro Yamada2015-09-257-51/+7
| | | | | | | | | | These input enable settings are handled by the pinctrl drivers. Because the external bus pins are input-enabled by default, on-board devices such as LED still work fine even with this delayed input enabling. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop ad-hoc early pin-muxing settingsMasahiro Yamada2015-09-256-82/+7
| | | | | | | | | As the UniPhier serial driver had already switched to Drive Model and the pinctrl drivers are now enabled, these pin-muxing settings are properly handled by the pinctrl drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: enable PINCTRL and SPL_PINCTRLMasahiro Yamada2015-09-253-0/+6
| | | | | | Now, UniPhier SoCs are ready to enable pinctrl drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: prepare device trees to use pinctrl in SPLMasahiro Yamada2015-09-254-4/+60
| | | | | | | | | | | | | | | Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB (spl/u-boot-spl.dtb). The "soc" node (this is simple-bus node) also needs the property to bind the pinctrl node located under it. I am collecting this U-Boot specific hack to the bottom of board DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI. My goal is to sync DTSI with Linux for easier maintenance. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodesMasahiro Yamada2015-09-253-0/+3
| | | | | | | | | | | | | | | | | | In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc" (simple-bus) nodes in UniPhier device trees. But, before that, CONFIG_SYS_MALLOC_F_LEN must be increased. Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind all of its child nodes. (See simple_bus_post_bind() function) Actually, I want only UART0 and pinctrl to be bound in SPL and before relocation in U-boot proper. But, with "u-boot,dm-pre-reloc" in the simple-bus node, all the other unwanted nodes are also bound. The default value for CONFIG_SYS_MALLOC_F_LEN, 0x400, is not enough for that. Increase the pre-reloc malloc size to 0x2000, hoping the root cause will be fixed later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable simple-bus driver for SPLMasahiro Yamada2015-09-253-0/+3
| | | | | | | | | In UniPhier device trees, pinctrl device nodes are located under the simple-bus (AMBA). This is needed to bind pinctrl devices in SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-09-253-0/+140
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-09-253-0/+147
| | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-09-253-0/+151
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-09-253-0/+148
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-09-253-0/+137
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-09-253-0/+141
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier pinctrl core supportMasahiro Yamada2015-09-236-0/+278
| | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: move dm_scan_fdt_node() out of pinctrl uclassMasahiro Yamada2015-09-192-6/+17
| | | | | | | | | | | | | | | | | | | | | Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-09-1711-70/+400
|\
| * x86: quark: Configure MTRR to enable cacheBin Meng2015-09-163-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: doc: Add DMI to the TODO listBin Meng2015-09-161-0/+2
| | | | | | | | | | | | | | | | Desktop Management Interface (DMI) is not supported by U-Boot now. Add it to the TODO list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: doc: Document some porting hints about Intel QuarkBin Meng2015-09-161-0/+24
| | | | | | | | | | | | | | | | Document porting considerations for Intel Quark based board, including MRC parameters and PCIe initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-161-0/+12
| | | | | | | | | | | | | | | | Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize thermal sensor properlyBin Meng2015-09-162-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Thermal sensor on Quark SoC needs to be properly initialized per Quark firmware writer guide, otherwise when booting Linux kernel, it triggers system shutdown because of wrong temperature in the thermal sensor is detected by the kernel driver (see below): [ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down [ 5.128997] Failed to start orderly shutdown: forcing the issue [ 5.135495] Emergency Sync complete Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-162-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When Linux kernel boots, it hangs at: [ 0.829408] Intel Quark side-band driver registered This happens when Quark kernel Isolated Memory Region (IMR) driver tries to lock an IMR register to protect kernel's text and rodata sections. However in order to have IMR function correctly, HMBOUND register must be locked otherwise the system just hangs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-161-51/+21
| | | | | | | | | | | | | | Change existing codes to use clrbits, setbits, clrsetbits macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add clrbits, setbits, clrsetbits macros for message port accessBin Meng2015-09-161-0/+31
| | | | | | | | | | | | | | | | | | On Intel Quark, lots of registers on the message port need be programmed. Add handy clrbits, setbits, clrsetbits macros for message port access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable random mac address for QuarkBin Meng2015-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | Not like other Intel Ethernet controllers (e.g.: E1000), Intel Quark SoC integrated designware Ethernet controller does not have a chipset defined way to store/restore mac address. Enable random mac address so that we can use Ethernet even without 'ethaddr'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-163-0/+87
| | | | | | | | | | | | | | | | | | This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-162-20/+1
| | | | | | | | | | | | | | | | Convert to use DM version of Designware ethernet driver on Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * net: designware: Add support to PCI designware devicesBin Meng2015-09-161-0/+42
| | | | | | | | | | | | | | | | The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-162-2/+13
| | | | | | | | | | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-09-171-0/+1
|\ \
| * | dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrlMasahiro Yamada2015-09-161-0/+1
| |/ | | | | | | | | | | | | | | These properties are necessary to use full-featured pinctrl drivers in SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra114: Clear IDDQ when enabling PLLCThierry Reding2015-09-162-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra124: Clear IDDQ when enabling PLLCThierry Reding2015-09-162-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
OpenPOWER on IntegriCloud