summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* rpi: BCM2837 and Raspberry Pi 3 32-bit supportStephen Warren2016-04-017-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with the CPU complex swapped out for a quad-core ARMv8. This can operate in 32- or 64-bit mode. 32-bit mode is the current default selected by the VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of U-Boot for the Raspberry Pi 3. >From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a change in usage of the SoC UARTs. On all previous Pis, the PL011 was the only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a UART to connect to the SoC. By default, the PL011 is used for this purpose since it has larger FIFOs than the other "mini" UART. However, this can be configured via the VideoCore firmware's config.txt file. This patch hard-codes use of the mini UART in the RPi 3 port. If your system uses the PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot port instead. A future change might determine which UART to use at run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed together. The mini UART has some limitations. One externally visible issue in the BCM2837 integration is that the UART divides the SoC's "core clock" to generate the baud rate. The core clock is typically variable, and under control of the VideoCore firmware for thermal management reasons. If the VC FW does modify the core clock rate, UART communication will be corrupted since the baud rate will vary from the expected value. This was not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To work around this, the VideoCore firmware can be told not to modify the SoC core clock. However, the only way this can happen and be thermally safe is to limit the core clock to a low/minimum frequency. This leaves performance on the table for use-cases that don't care about a UART console. Consequently, use of the mini UART console must be explicitly requested by entering the following line into config.txt: enable_uart=1 A recent version of the VC firmware is required to ensure that the mini UART is fully and correctly initialized by the VC FW; at least firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: expand Kconfig target descriptionsStephen Warren2016-04-011-1/+27
| | | | | | | | This adds an explanation of which Raspberry Pi models each target option supports. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* rpi: add Raspberry Pi 3 board IDStephen Warren2016-04-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | This allows U-Boot to known the name of the board. The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3 in 32-bit mode /if/ you have configured the firmware to use the PL011 UART as the console UART (the default is the mini UART). This requires two things: a) config.txt should contain dtoverlay=pi3-miniuart-bt b) You should run the following to tell the VC FW to process DT when booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card as the kernel image: path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img This works as of firmware.git commit 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* rpi: use constant "unknown board" DT filenameStephen Warren2016-04-011-5/+1
| | | | | | | | | | | To simplify support for new SoCs, just use a constant filename for the unknown case. In practice this case shouldn't be hit anyway, so the filename isn't relevant, and certainly doesn't need to differentiate between SoCs. If a user has an as-yet-unknown board, they can override this value in the environment anyway. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: move CONFIG_BCM283* to KconfigStephen Warren2016-04-013-3/+11
| | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* doc: clarify openssl-based key and certificate generation processAndreas Dannenberg2016-04-011-4/+4
| | | | | | | | Add some basic clarification that the dev.key file generated by OpenSSL contains both the public and private key, and further highlight that the certificate generated here contains the public key only. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* doc: fix file extension for flattened image tree blobAndreas Dannenberg2016-04-011-1/+1
| | | | | | | | Different sections in the document suggest flattened image tree blob files have a file name extension of .itb. Fix the list of file extensions to reflect that. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* README: Specify the full path for README.displaying-bmpsFabio Estevam2016-04-011-1/+1
| | | | | | | It is clearer to specify the full path to access the doc/README.displaying-bmps file. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* ARM: keystone2: Add missing privilege ID settingsNishanth Menon2016-04-012-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing Privilege ID settings for KS2 SoCs. Based on: K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013) http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99) K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015) http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71) K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015) http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75) K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016) http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238) Overall mapping: -------+-----------+-----------+-----------+--------- PrivID | KS2H/K | K2L | K2E | K2G -------+-----------+-----------+-----------+--------- 0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved -------+-----------+-----------+-----------+--------- NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state. Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact). By marking these segments as shared, we also ensure SoC wide coherency is enabled. Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Refactor MSMC macros to avoid #ifdefferyNishanth Menon2016-04-014-23/+53
| | | | | | | | | | | | | | | MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* smsc95xx: fix operation on 64-bit systemsStephen Warren2016-04-011-2/+2
| | | | | | | | | | | | smsc95xx_read_reg() should calculate sizeof(*data) not sizeof(data) since data is a pointer, and the value pointed at is being transferred over USB, not the value of the pointer. This fixes operation of the driver in 64-bit builds, such as the Raspberry Pi 3. Reported-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Drop command-processing code when CONFIG_CMDLINE is disabledSimon Glass2016-04-014-1/+44
| | | | | | | | Command parsing and processing code is not needed when the command line is disabled. Remove this code in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* fastboot: allow retrieving fastboot variables from envRob Herring2016-04-011-2/+10
| | | | | | | | | | | | | | | | | | | | Some boards need to expose device specific variable through fastboot (to adpat the flashing script depending on hardware revision for example). Provide a way to expose custom fastboot variables. Note that all variables meant to be exposed through fastboot should be be prefixed with 'fastboot.', the variable should not exceed 32 bytes (including the prefix and the trailing '\0') and the variable content should fit in the response buffer (60 bytes excluding the 'OKAY' prefix and the trailing '\0'). Signed-off-by: Rob Herring <rob.herring@linaro.org> [Boris Brezillon: add a commit message] Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Steve Rae <srae@broadcom.com>
* arm: clang: Update support slightlyTom Rini2016-04-013-9/+15
| | | | | | | | | | | - Move most of the flags required into LLVM_RELFLAGS to test at build time instead of requiring them to be passed in. - Update doc/README.clang to reflect this - Switch to rpi_2 as the example as it's closer to working out of the box than rpi is. Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-04-0164-103/+1275
|\
| * sunxi: Reserve ATF memory space on A64Alexander Graf2016-04-011-0/+9
| | | | | | | | | | | | | | | | | | | | On the A64 we usually boot with ATF running in EL3. ATF as it is available today resides in the first 16MB of RAM. So we should make sure we reserve that space in our memory maps. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add Pine64+ supportSiarhei Siamashka2016-04-016-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of running AArch64 code and thus is the first of its kind for the sunxi target. This patch adds a defconfig and device tree chunks for it. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: Change patch description] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-0117-20/+694
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-014-5/+5
| | | | | | | | | | | | | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Depend SPL configs on SUPPORT_SPLAlexander Graf2016-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | We currently depend SPL config options on specific machine types which doesn't scale. Fortunately there's already a kconfig variable that tells us whether we want to build SPL code at all, so just depend them on this. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Move cpu independent code to mach directoryAlexander Graf2016-04-0123-37/+52
| | | | | | | | | | | | | | | | | | | | | | | | Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB nodes for H8Homlet v2Chen-Yu Tsai2016-04-011-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB on Cubietruck PlusChen-Yu Tsai2016-04-011-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsiChen-Yu Tsai2016-04-011-0/+34
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfigChen-Yu Tsai2016-04-011-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck Plus uses all 3 USB controllers: - USB OTG functions are provided by the musb USB OTG controller - Onboard SATA is provied by a USB-SATA bridge connected to USB1 - The USB host ports on the board are provided by an HSIC USB hub FLDO1 is set to 1.2V for HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfigChen-Yu Tsai2016-04-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | The h8_homlet_v2 has 2 USB host ports, one connected to the OTG controller, one connected to the EHCI/OHCI pair. Also provide the card detect pin for MMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ohci: Add A83T compatibleChen-Yu Tsai2016-03-311-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: ehci: Add A83T compatibleChen-Yu Tsai2016-03-311-0/+1
| | | | | | | | | | | | | | | | We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: clk: Fix USB PHY clock macros for A83TChen-Yu Tsai2016-03-311-3/+3
| | | | | | | | | | | | | | | | | | The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: usb_phy: Add support for A83T USB PHYsChen-Yu Tsai2016-03-312-2/+48
| | | | | | | | | | | | | | | | | | The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Set DLDO4 to 3.3VChen-Yu Tsai2016-03-311-0/+1
| | | | | | | | | | | | | | | | | | DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY / composite video encoder. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)Chen-Yu Tsai2016-03-311-1/+0
| | | | | | | | | | | | | | | | | | | | | | The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some Allwinner-based boards set it to 3.0V to conserve power. Since the h8_homlet_v2 is a set-top box board with external power, there is no such requirement. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Add support for FLDOsChen-Yu Tsai2016-03-315-0/+69
| | | | | | | | | | | | | | | | | | The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Fix DCDC5 default voltageChen-Yu Tsai2016-03-312-3/+1
| | | | | | | | | | | | | | | | | | | | | | DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3, 1.35V for DDR3L, and 1.2V for LPDDR3. Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp: Support VBUS drive GPIO on AXP818Chen-Yu Tsai2016-03-311-1/+5
| | | | | | | | | | | | | | | | | | AXP818 supports VBUS drive function, even though the manual does not mention it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: axp: Generalize register macros for VBUS drive GPIOChen-Yu Tsai2016-03-312-15/+18
| | | | | | | | | | | | | | | | | | VBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * musb: sunxi: Add support for A83TChen-Yu Tsai2016-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | Like the Allwinner A33 SoC, the A83T is missing the config register from the musb USB DRD hardware block. Use a known working value for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * power: axp818: Remove undefined axp818_init()Chen-Yu Tsai2016-03-311-2/+0
| | | | | | | | | | | | | | | | axp818_init() is declared, but never defined. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable LDO3 and LDO4 at 2.8V on OLinuxIno Lime boardsHans de Goede2016-03-313-0/+6
| | | | | | | | | | | | | | LDO3 and LDO4 are used to power port E resp. port G, which are exposed on gpio headers, so enable them at 2.8V as specified in the schematic. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: A20-OLinuXino-Lime2: Force 8211CL to masterMichael Haas2016-03-311-0/+1
| | | | | | | | | | | | | | | | | | Force master mode on the A20-OLinuXino-Lime2. This change is required to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas <haas@computerlinguist.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: A20-Olimex-SOM-EVB: Force 8211CL to masterMichael Haas2016-03-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Force master mode for 1000BASE-T operation on the A20-Olimex-SOM-EVB. Karsten Merker reports that this change is necessary to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas <haas@computerlinguist.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * net: phy: Optionally force master mode for RTL PHYMichael Haas2016-03-312-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Print soc-id from sram controller for sun8i boardsHans de Goede2016-03-311-5/+19
| | | | | | | | | | | | | | | | | | As the need for various magic sram pokes has shown this maybe useful info to have. e.g. this shows one of my a23 tablets having an id of 1661 rather then the usual 1650 for the a23. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add conditional magic sram poke for A33Hans de Goede2016-03-311-4/+16
| | | | | | | | | | | | | | | | | | I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | ARM: uniphier: remove CONFIG_ARP_TIMEOUT defineMasahiro Yamada2016-04-011-8/+0
| | | | | | | | | | | | | | | | | | I no longer see the problem claimed in the comment block. Rather, the 0.5 msec timeout seems too short for some TFTP servers. Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | cosmetic: Fix typos "privide"Masahiro Yamada2016-04-018-8/+8
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada2016-04-0151-193/+197
| | | | | | | | | | | | | | Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3Masahiro Yamada2016-04-011-0/+23
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: enable eMMC on PH1-sLD3 reference boardMasahiro Yamada2016-04-011-0/+4
| | | | | | | | | | | | | | On PH1-sLD3, eMMC and NAND are assigned to different I/O pins. Both devices can be enabled at the same time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64Masahiro Yamada2016-04-011-10/+35
| | | | | | | | | | | | | | | | | | | | | | Currently, these functions assume #address-cells and #size-cells are both one. Fix them to support 64bit DTB. Also, I am fixing a buffer overrun bug while I am here. The array size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of iteration in the loop should be limited by that CONFIG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
OpenPOWER on IntegriCloud