diff options
Diffstat (limited to 'include')
111 files changed, 2183 insertions, 3506 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index a63a87a287..c918049386 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif -#if defined(CONFIG_MPC5xxx) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) unsigned long bi_mbar_base; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) @@ -66,10 +66,15 @@ typedef struct bd_info { #if defined(CONFIG_MPC512X) unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ #endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif +#if defined(CONFIG_EXTRA_CLOCK) + unsigned long bi_inpfreq; /* input Freq in MHz */ + unsigned long bi_vcofreq; /* vco Freq in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ +#endif #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ diff --git a/include/axp221.h b/include/axp221.h index a20e25c2f8..be6058e439 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -14,6 +14,9 @@ #define AXP223_RUNTIME_ADDR 0x2d /* Page 0 addresses */ +#define AXP221_POWER_STATUS 0x00 +#define AXP221_POWER_STATUS_VBUS_AVAIL (1 << 5) +#define AXP221_POWER_STATUS_VBUS_USABLE (1 << 4) #define AXP221_CHIP_ID 0x03 #define AXP221_OUTPUT_CTRL1 0x10 #define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0) @@ -59,6 +62,9 @@ /* Page 1 addresses */ #define AXP221_SID 0x20 +/* We support vbus detection */ +#define AXP_VBUS_DETECT + /* We support drivebus control */ #define AXP_DRIVEBUS @@ -77,5 +83,6 @@ int axp221_set_aldo3(unsigned int mvolt); int axp221_set_eldo(int eldo_num, unsigned int mvolt); int axp221_init(void); int axp221_get_sid(unsigned int *sid); +int axp_get_vbus(void); int axp_drivebus_enable(void); int axp_drivebus_disable(void); diff --git a/include/common.h b/include/common.h index 77c55c6f26..6df05b8bb1 100644 --- a/include/common.h +++ b/include/common.h @@ -553,7 +553,9 @@ static inline int cpumask_next(int cpu, unsigned int mask) iter++, cpu = cpumask_next(cpu, mask)) \ int cpu_numcores (void); +int cpu_num_dspcores(void); u32 cpu_mask (void); +u32 cpu_dsp_mask(void); int is_core_valid (unsigned int); int probecpu (void); int checkcpu (void); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 07a0b3b234..73f093f9ea 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -10,6 +10,22 @@ #ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H #define _CONFIG_CMD_DISTRO_BOOTCMD_H +/* + * A note on error handling: It is possible for BOOT_TARGET_DEVICES to + * reference a device that is not enabled in the U-Boot configuration, e.g. + * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given + * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor + * at compile time, it's not possible to detect and report such problems via + * a simple #ifdef/#error combination. Still, the code needs to report errors. + * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to + * reference a non-existent symbol, and have the name of that symbol encode + * the error message. Consequently, this file contains references to e.g. + * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the + * prevalence of capitals here, this looks like a pre-processor macro and + * hence seems like it should be all capitals, but it's really an error + * message that includes some other pre-processor symbols in the text. + */ + /* We need the part command */ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h deleted file mode 100644 index 802e9cce1f..0000000000 --- a/include/configs/BC3450.h +++ /dev/null @@ -1,541 +0,0 @@ -/* - * -- Version 1.1 -- - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2005 - * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de. - * - * History: - * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ - -#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ -#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */ -#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */ -#define CONFIG_BC3450_USB 1 /* + USB support */ -# define CONFIG_FAT 1 /* + FAT support */ -# define CONFIG_EXT2 1 /* + EXT2 support */ -#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */ -#undef CONFIG_BC3450_CAN /* + CAN transceiver */ -#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */ -#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */ -#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */ -#define CONFIG_BC3450_FP 1 /* + enable FP O/P */ -#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration with room for - * max 64 MByte Flash ROM) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * AT-PS/2 Multiplexer - */ -#ifdef CONFIG_BC3450_PS2 -# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -# define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_BC3450_PS2 */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -/* - * Video console - */ -# define CONFIG_VIDEO -# define CONFIG_VIDEO_SM501 -# define CONFIG_VIDEO_SM501_32BPP -# define CONFIG_CFB_CONSOLE -# define CONFIG_VIDEO_LOGO -# define CONFIG_VGA_AS_SINGLE_DEVICE -# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */ -# define CONFIG_VIDEO_SW_CURSOR -# define CONFIG_SPLASH_SCREEN -# define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* - * Partitions - */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * USB - */ -#ifdef CONFIG_BC3450_USB -# define CONFIG_USB_OHCI -# define CONFIG_USB_STORAGE -#endif /* CONFIG_BC3450_USB */ - -/* - * POST support - */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif /* CONFIG_POST */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_BSP - -#ifdef CONFIG_VIDEO - #define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_BC3450_IDE - #define CONFIG_CMD_IDE -#endif - -#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB) - #ifdef CONFIG_FAT - #define CONFIG_CMD_FAT - #endif - - #ifdef CONFIG_EXT2 - #define CONFIG_CMD_EXT2 - #endif -#endif - -#ifdef CONFIG_BC3450_USB - #define CONFIG_CMD_USB -#endif - -#ifdef CONFIG_PCI - #define CONFIG_CMD_PCI -#endif - -#ifdef CONFIG_POST - #define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo;" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ipaddr=192.168.1.10\0" \ - "serverip=192.168.1.3\0" \ - "netmask=255.255.255.0\0" \ - "hostname=bc3450\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "kernel_addr=fc0a0000\0" \ - "ramdisk_addr=fc1c0000\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ideargs=setenv bootargs root=/dev/hda2 ro\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addcons=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) console=tty0\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile); " \ - "run nfsargs addip addcons; bootm\0" \ - "ide_nfs=run nfsargs addip addcons; " \ - "disk 200000 0:1; bootm\0" \ - "ide_ide=run ideargs addip addcons; " \ - "disk 200000 0:1; bootm\0" \ - "usb_self=run usbload; run ramargs addip addcons; " \ - "bootm 200000 400000\0" \ - "usbload=usb reset; usb scan; usbboot 200000 0:1; " \ - "usbboot 400000 0:2\0" \ - "bootfile=uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 $(filesize);" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for I²C EEPROM M24C32 - * M24C64 should work also. For other EEPROMs config should be verified. - * - * The TQM5200 module may hold an EEPROM at address 0x50. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231) -# define CONFIG_RTC_M41T11 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#else -# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */ -# define CONFIG_BOARD_EARLY_INIT_R -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif /*CONFIG_POST*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - * - * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#undef CONFIG_MPC5xxx_MII10 -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration on BC3450 - * - * PSC1: UART1 (Service-UART) [0x xxxxxxx4] - * PSC2: UART2 [0x xxxxxx4x] - * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x] - * PSC3: USB2 [0x xxxxx1xx] - * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx] - * (this has to match - * CONFIG_USB_CONFIG which is - * used by usb_ohci.c to set - * the USB ports) - * Eth: 10/100Mbit Ethernet [0x xxx0xxxx] - * (this is reset to '5' - * in FEC driver: fec.c) - * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx] - * ATA/CS: ??? [0x x1xxxxxx] - * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx] - * CS1: Use Pin gpio_wkup_6 as second - * SDRAM chip select (mem_cs1) - * Timer: CAN2 / SPI - * I2C: CAN1 / I²C2 [0x bxxxxxxx] - */ -#ifdef CONFIG_BC3450_AC97 -# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124 -#else /* PSC2=UART2 */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max no of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */ - -#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */ - /* more extensive mem test */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* automatic configuration of chip selects */ -#ifdef CONFIG_TQM5200 -# define CONFIG_LAST_STAGE_INIT -#endif /* CONFIG_TQM5200 */ - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#ifdef CONFIG_TQM5200 -# define CONFIG_SYS_CS2_START 0xE5000000 -# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -# define CONFIG_SYS_CS2_CFG 0x0004D930 -#endif /* CONFIG_TQM5200 */ - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#ifdef CONFIG_TQM5200 -# define SM501_FB_BASE 0xE0000000 -# define CONFIG_SYS_CS1_START (SM501_FB_BASE) -# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -# define CONFIG_SYS_CS1_CFG 0x8F48FF70 -# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 -#endif /* CONFIG_TQM5200 */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */ - /* flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * USB stuff - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */ - -/* - * IDE/ATA stuff Supports IDE harddisk - */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h deleted file mode 100644 index 5cc25576ae..0000000000 --- a/include/configs/JSE.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * (C) Copyright 2003 Picture Elements, Inc. - * Stephen Williams <steve@icarus.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options for the JSE board - * (Theoretically easy to change, but the board is fixed.) - */ - -#define CONFIG_JSE 1 - /* JSE has a PPC405GPr */ -#define CONFIG_405GP 1 - /* ... with a 33MHz OSC. connected to the SysCLK input */ -#define CONFIG_SYS_CLK_FREQ 33333333 - /* ... with on-chip memory here (4KBytes) */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 - /* Do not set up locked dcache as init ram. */ -#undef CONFIG_SYS_INIT_DCACHE_CS - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - - /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ -#define CONFIG_SYSTEMACE 1 -#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 -#define CONFIG_SYS_SYSTEMACE_WIDTH 8 -#define CONFIG_DOS_PARTITION 1 - - /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - /* ... place INIT RAM in the OCM address */ -# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR - /* ... give it the whole init ram */ -# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE - /* ... Shave a bit off the end for global data */ -# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - /* ... and place the stack pointer at the top of what's left. */ -# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - /* Enable board_pre_init function */ -#define CONFIG_BOARD_PRE_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - /* Disable post-clk setup init function */ -#undef CONFIG_BOARD_POSTCLK_INIT - /* Disable call to post_init_f: late init function. */ -#undef CONFIG_POST - /* Enable DRAM test. */ -#define CONFIG_SYS_DRAM_TEST 1 - /* Enable misc_init_r function. */ -#define CONFIG_MISC_INIT_R 1 - - /* JSE has EEPROM chips that are good for environment. */ -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_EEPROM 1 -#undef CONFIG_ENV_IS_NOWHERE - - /* This is the 7bit address of the device, not including P. */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - /* After the device address, need one more address byte. */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - /* The EEPROM is 512 bytes. */ -#define CONFIG_SYS_EEPROM_SIZE 512 - /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - /* Put the environment in the second half. */ -#define CONFIG_ENV_OFFSET 0x00 -#define CONFIG_ENV_SIZE 512 - - /* The JSE connects UART1 to the console tap connector. */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - - /* Set console baudrate to 9600 */ -#define CONFIG_BAUDRATE 9600 - -/* - * Configuration related to auto-boot. - * - * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait - * before resorting to autoboot. This value can be overridden by the - * bootdelay environment variable. - * - * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the - * user that an autoboot will happen. - * - * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will - * execute to boot the JSE. This loads the uimage and initrd.img files - * from CompactFlash into memory, then boots them from memory. - * - * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get - * it going on the JSE. - */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" -#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" - - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - - - /* watchdog disabled */ -#undef CONFIG_WATCHDOG - /* SPD EEPROM (sdram speed config) disabled */ -#undef CONFIG_SPD_EEPROM -#undef SPD_EEPROM_ADDRESS - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 -#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 0f4b726f3a..734a77fb4f 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -22,6 +22,8 @@ #define CONFIG_M54451 /* define processor type */ #define CONFIG_M54451EVB /* M54451EVB board */ +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7a55d3c619..2faf58156d 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -22,6 +22,8 @@ #define CONFIG_M54455 /* define processor type */ #define CONFIG_M54455EVB /* M54455EVB board */ +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index e88a6bd8d3..2f4549f270 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -22,11 +22,13 @@ #define CONFIG_M547x /* define processor type */ #define CONFIG_M5475 /* define processor type */ +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 -#define CONFIG_HW_WATCHDOG +#undef CONFIG_HW_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ /* Command line configuration */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index e4128062a9..9aa02f7c6c 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -22,11 +22,13 @@ #define CONFIG_M548x /* define processor type */ #define CONFIG_M5485 /* define processor type */ +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 -#define CONFIG_HW_WATCHDOG +#undef CONFIG_HW_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ /* Command line configuration */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index bf974fd461..1ab23796cf 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index dd8122965a..d9a19c3694 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 98e907245a..1384f360bd 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 65a63e2b7f..2dd71b7ed9 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1735b3c521..14abd3512c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -7,6 +7,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 6b7d648944..17f230f4a1 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 398918a940..245712504c 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -40,6 +40,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) #define CONFIG_SYS_LOWBOOT #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 832c10f5c0..85f5c40ede 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index d47f1be685..52633181ad 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -220,7 +220,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h deleted file mode 100644 index b4daedceea..0000000000 --- a/include/configs/TB5200.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#define CONFIG_TB5200 1 /* ... on a TB5200 base board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration with room for - * max 64 MByte Flash ROM) - * 0xFFF00000 boot high (for a backup copy of U-Boot) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */ -#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_USB - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined(CONFIG_TQM5200_B) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" \ - "" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" -#endif /* CONFIG_TQM5200_B */ - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* List of I2C addresses to be verified by POST */ -#undef CONFIG_SYS_POST_I2C_ADDRS -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR, \ - CONFIG_SYS_I2C_SLAVE} - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_TQM5200_B) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_TQM5200_B */ -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#if defined(CONFIG_TQM5200_B) -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ - "1280k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" -#else -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" -#endif /* CONFIG_TQM5200_B */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#if defined(CONFIG_TQM5200_B) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_TQM5200_B */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#if defined(CONFIG_TQM5200_B) -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#endif /* CONFIG_TQM5200_B */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC3: Bits 20:23 (mask: 0x00000300): - * 0001 -> USB2 - * 0000 -> GPIO - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114 - -/* - * RTC configuration - */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base - year */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 6762e3a57e..7b496c853f 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -12,6 +12,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h deleted file mode 100644 index 895ad4611b..0000000000 --- a/include/configs/W7OLMC.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ -#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADADDR F0080000 - -#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.2 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_REGINFO - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ - -#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ -#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ -#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ -#ifdef CONFIG_SYS_HUSH_PARSER -#endif -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 384000 - - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE {9600} - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -/* resource configuration */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Set up values for external bus controller - * used by cpu_init.c - *----------------------------------------------------------------------- - */ - /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ -#undef CONFIG_USE_PERWE - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* bank 0 is boot flash */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 -/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 - -/* bank 1 is main flash */ -/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_EBC_PB1AP 0x05850240 -/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ -#define CONFIG_SYS_EBC_PB1CR 0xF00FC000 - -/* bank 2 is RTC/NVRAM */ -/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_EBC_PB2AP 0x03000440 -/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_EBC_PB2CR 0xFC018000 - -/* bank 3 is FPGA 0 */ -/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ -#define CONFIG_SYS_EBC_PB3AP 0x02000400 -/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ -#define CONFIG_SYS_EBC_PB3CR 0xFD01A000 - -/* bank 4 is FPGA 1 */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CONFIG_SYS_EBC_PB4AP 0x02000400 -/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_EBC_PB4CR 0xFD11A000 - -/* bank 5 is FPGA 2 */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CONFIG_SYS_EBC_PB5AP 0x02000400 -/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ -#define CONFIG_SYS_EBC_PB5CR 0xFD21A000 - -/* bank 6 is unused */ -/* PB6AP = 0 */ -#define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* PB6CR = 0 */ -#define CONFIG_SYS_EBC_PB6CR 0x00000000 - -/* bank 7 is LED register */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 -/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ -#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -/*define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ -#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR - -#else /* Use Boot Flash for environment variables */ -/*----------------------------------------------------------------------- - * Flash EEPROM for environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ - -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ - -/* - * Init Memory Controller: - */ -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * FPGA(s) configuration - */ -#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ -#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ -#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ -#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ -#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h deleted file mode 100644 index 2a38116dd1..0000000000 --- a/include/configs/W7OLMG.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ -#define CONFIG_W7OLMG 1 /* ...specifically an LMG */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADADDR F0080000 - -#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.2 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DTT - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ - -#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ -#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ -#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ -#ifdef CONFIG_SYS_HUSH_PARSER -#endif -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 384000 - - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE {9600} - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -/* resource configuration */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Set up values for external bus controller - * used by cpu_init.c - *----------------------------------------------------------------------- - */ - /* use PerWE instead of PCI_INT ( these functions share a pin ) */ -#define CONFIG_USE_PERWE 1 - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* bank 0 is boot flash */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 -/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 - -/* bank 1 is main flash */ -/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_EBC_PB1AP 0x04850240 -/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ -#define CONFIG_SYS_EBC_PB1CR 0xF00FC000 - -/* bank 2 is RTC/NVRAM */ -/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_EBC_PB2AP 0x03000440 -/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_EBC_PB2CR 0xFC018000 - -/* bank 3 is FPGA 0 */ -/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ -#define CONFIG_SYS_EBC_PB3AP 0x02000400 -/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ -#define CONFIG_SYS_EBC_PB3CR 0xFD01A000 - -/* bank 4 is SAM 8 bit range */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CONFIG_SYS_EBC_PB4AP 0x02840380 -/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ -#define CONFIG_SYS_EBC_PB4CR 0xFE878000 - -/* bank 5 is SAM 16 bit range */ -/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ -#define CONFIG_SYS_EBC_PB5AP 0x05040d80 -/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ -#define CONFIG_SYS_EBC_PB5CR 0xFD87A000 - -/* bank 6 is unused */ -/* PB6AP = 0 */ -#define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* PB6CR = 0 */ -#define CONFIG_SYS_EBC_PB6CR 0x00000000 - -/* bank 7 is LED register */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 -/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ -#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -/*define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ -#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR - -#else /* Use Boot Flash for environment variables */ -/*----------------------------------------------------------------------- - * Flash EEPROM for environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ - -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (ATMEL 24C04N) - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ - -/* - * Init Memory Controller: - */ -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * FPGA(s) configuration - */ -#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ -#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ -#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ -#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ -#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h deleted file mode 100644 index 2dffcfbed3..0000000000 --- a/include/configs/aev.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ -#define CONFIG_AEVFIFO 1 -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration with room for - * max 64 MByte Flash ROM) - * 0xFFF00000 boot high (for a backup copy of U-Boot) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_AEVFIFO -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_AEVFIFO */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "console=ttyS0,${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index f1c270c939..a87059c543 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -340,6 +340,12 @@ #endif /* CONFIG_MUSB_GADGET */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* Remove other SPL modes. */ +#undef CONFIG_SPL_YMODEM_SUPPORT +#undef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_NAND /* disable host part of MUSB in SPL */ #undef CONFIG_MUSB_HOST /* disable EFI partitions and partition UUID support */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 290a6a3e06..c3c9169d05 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,11 +19,15 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 3de5079962..31e758d81b 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,11 +19,15 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/amcore.h b/include/configs/amcore.h new file mode 100644 index 0000000000..2a785b3fc3 --- /dev/null +++ b/include/configs/amcore.h @@ -0,0 +1,140 @@ +/* + * Sysam AMCORE board configuration + * + * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AMCORE_CONFIG_H +#define __AMCORE_CONFIG_H + +#define CONFIG_AMCORE +#define CONFIG_HOSTNAME AMCORE + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_MCF530x +#define CONFIG_M5307 + +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "bootm ffc20000" + +#include <config_cmd_default.h> +#undef CONFIG_CMD_AES +#undef CONFIG_CMD_BOOTD +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_XIMG +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIMER +#define CONFIG_CMD_DIAG + +#define CONFIG_SYS_PROMPT "amcore $ " +/* undef to save memory */ +#undef CONFIG_SYS_LONGHELP + +#if defined(CONFIG_CMD_KGDB) +/* Console I/O buff. size */ +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START 0x0 +#define CONFIG_SYS_MEMTEST_END 0x1000000 + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_CLK 45000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +/* Register Base Addrs */ +#define CONFIG_SYS_MBAR 0x10000000 +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +/* size of internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +/* amcore design has flash data bytes wired swapped */ +#define CONFIG_SYS_WRITE_SWAPPED_DATA +/* reserve 128-4KB */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 + +/* memory map space for linux boot data */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Cache Configuration + * + * Special 8K version 3 core cache. + * This is a single unified instruction/data cache. + * sdram - single region - no masks + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ + CF_ACR_EN) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ + CF_CACR_EC) + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +/* 4MB, AA=0,V=1 C/I BIT for errata */ +#define CONFIG_SYS_CS0_MASK 0x003f0001 +/* WS=10, AA=1, PS=16bit (10) */ +#define CONFIG_SYS_CS0_CTRL 0x1980 +/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ +#define CONFIG_SYS_CS1_BASE 0x3000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x0100 + +#endif /* __AMCORE_CONFIG_H */ + diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 61809fcdbe..6d38853ed0 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 Marcel Ziswiler + * Copyright (c) 2014-2015 Marcel Ziswiler * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C @@ -47,12 +45,8 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB -/* USB networking support */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX - /* PCI host support */ -#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */ +#define CONFIG_PCI #define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI @@ -60,12 +54,31 @@ /* PCI networking support */ #define CONFIG_E1000 -#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */ +#define CONFIG_E1000_NO_NVM /* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +/* Miscellaneous commands */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_FAT_WRITE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h index 727b14a6c2..47760ef7ba 100644 --- a/include/configs/aspenite.h +++ b/include/configs/aspenite.h @@ -11,6 +11,11 @@ #define __CONFIG_ASPENITE_H /* + * Generic board support + */ +#define CONFIG_SYS_GENERIC_BOARD + +/* * Version number information */ #define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB" diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h new file mode 100644 index 0000000000..490c53e92f --- /dev/null +++ b/include/configs/bav335x.h @@ -0,0 +1,633 @@ +/* + * bav335x.h + * + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_BAV335X_H +#define __CONFIG_BAV335X_H + +#include <configs/ti_am335x_common.h> +#define CONFIG_ENV_IS_NOWHERE + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_FIT +# define CONFIG_TIMESTAMP +# define CONFIG_LZO +# ifdef CONFIG_ENABLE_VBOOT +# define CONFIG_FIT_SIGNATURE +# define CONFIG_RSA +# endif +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds" + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#else +#define NANDARGS "" +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ +DEFAULT_LINUX_BOOT_ENV \ +"boot_fdt=try\0" \ +"bootpart=0:2\0" \ +"bootdir=\0" \ +"fdtdir=/dtbs\0" \ +"bootfile=zImage\0" \ +"fdtfile=undefined\0" \ +"console=ttyO0,115200n8\0" \ +"loadaddr=0x82000000\0" \ +"fdtaddr=0x88000000\0" \ +"rdaddr=0x88080000\0" \ +"initrd_high=0xffffffff\0" \ +"fdt_high=0xffffffff\0" \ +"partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ +"optargs=\0" \ +"cmdline=\0" \ +"mmcdev=0\0" \ +"mmcpart=1\0" \ +"mmcroot=/dev/mmcblk0p2 ro\0" \ +"mmcrootfstype=ext4 rootwait fixrtc\0" \ +"rootpath=/export/rootfs\0" \ +"nfsopts=nolock\0" \ +"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ +"ramroot=/dev/ram0 rw\0" \ +"ramrootfstype=ext2\0" \ +"mmcargs=setenv bootargs console=${console} ${optargs} " \ + "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \ +"server_ip=192.168.1.100\0" \ +"gw_ip=192.168.1.1\0" \ +"netmask=255.255.255.0\0" \ +"hostname=\0" \ +"device=eth0\0" \ +"autoconf=off\0" \ +"root_dir=/home/userid/targetNFS\0" \ +"nfs_options=,vers=3\0" \ +"nfsrootfstype=ext4 rootwait fixrtc\0" \ +"nfsargs=setenv bootargs console=${console} ${optargs} " \ + "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \ + "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \ +"netargs=setenv bootargs console=${console} " \ + "${optargs} root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \ +"bootenv=uEnv.txt\0" \ +"script=boot.scr\0" \ +"scriptfile=${script}\0" \ +"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ +"bootscript=echo Running bootscript from mmc${bootpart} ...; " \ + "source ${loadaddr}\0" \ + "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ +"importbootenv=echo Importing environment from mmc ...; " \ + "env import -t -r $loadaddr $filesize\0" \ +"ramargs=setenv bootargs console=${console} " \ + "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \ +"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ +"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadrd=load mmc ${bootpart} ${rdaddr} " \ + "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \ +"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \ + "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \ +"mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "gpio set 54;" \ + "setenv bootpart ${mmcdev}:1; " \ + "if test -e mmc ${bootpart} /etc/fstab; then " \ + "setenv mmcpart 1;" \ + "fi; " \ + "echo Checking for: /uEnv.txt ...;" \ + "if test -e mmc ${bootpart} /uEnv.txt; then " \ + "if run loadbootenv; then " \ + "gpio set 55;" \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "echo Checking if uenvcmd is set ...;" \ + "if test -n ${uenvcmd}; then " \ + "gpio set 56; " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "echo Checking if client_ip is set ...;" \ + "if test -n ${client_ip}; then " \ + "if test -n ${dtb}; then " \ + "setenv fdtfile ${dtb};" \ + "echo using ${fdtfile} ...;" \ + "fi;" \ + "gpio set 56; " \ + "if test -n ${uname_r}; then " \ + "echo Running nfsboot_uname_r ...;" \ + "run nfsboot_uname_r;" \ + "fi;" \ + "echo Running nfsboot ...;" \ + "run nfsboot;" \ + "fi;" \ + "fi; " \ + "echo Checking for: /${script} ...;" \ + "if test -e mmc ${bootpart} /${script}; then " \ + "gpio set 55;" \ + "setenv scriptfile ${script};" \ + "run loadbootscript;" \ + "echo Loaded script from ${scriptfile};" \ + "gpio set 56; " \ + "run bootscript;" \ + "fi; " \ + "echo Checking for: /boot/${script} ...;" \ + "if test -e mmc ${bootpart} /boot/${script}; then " \ + "gpio set 55;" \ + "setenv scriptfile /boot/${script};" \ + "run loadbootscript;" \ + "echo Loaded script from ${scriptfile};" \ + "gpio set 56; " \ + "run bootscript;" \ + "fi; " \ + "echo Checking for: /boot/uEnv.txt ...;" \ + "for i in 1 2 3 4 5 6 7 ; do " \ + "setenv mmcpart ${i};" \ + "setenv bootpart ${mmcdev}:${mmcpart};" \ + "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \ + "gpio set 55;" \ + "load mmc ${bootpart} ${loadaddr} " \ + "/boot/uEnv.txt;" \ + "env import -t ${loadaddr} ${filesize};" \ + "echo Loaded environment from /boot/uEnv.txt;" \ + "if test -n ${dtb}; then " \ + "setenv fdtfile ${dtb};" \ + "echo Using: dtb=${fdtfile} ...;" \ + "fi;" \ + "echo Checking if uname_r is set in " \ + "/boot/uEnv.txt...;" \ + "if test -n ${uname_r}; then " \ + "gpio set 56; " \ + "echo Running uname_boot ...;" \ + "setenv mmcroot /dev/mmcblk${mmcdev}" \ + "p${mmcpart} ro;" \ + "run uname_boot;" \ + "fi;" \ + "fi;" \ + "done;" \ + "fi;\0" \ +"netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ +"nfsboot=echo Booting from ${server_ip} ...; " \ + "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \ + "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \ + ":${device}:${autoconf}; " \ + "setenv autoload no; " \ + "setenv serverip ${server_ip}; " \ + "setenv ipaddr ${client_ip}; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} dtbs/${fdtfile}; " \ + "run nfsargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ +"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \ + "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \ + "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \ + ":${device}:${autoconf}; " \ + "setenv autoload no; " \ + "setenv serverip ${server_ip}; " \ + "setenv ipaddr ${client_ip}; " \ + "tftp ${loadaddr} vmlinuz-${uname_r}; " \ + "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \ + "run nfsargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ +"ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ +"findfdt="\ + "if test $board_rev = B; then " \ + "setenv fdtfile birdland_bav335b.dtb; " \ + "setenv fdtbase am335x-boneblack; fi; " \ + "if test $board_rev = A; then " \ + "setenv fdtfile birdland_bav335a.dtb; " \ + "setenv fdtbase am335x-boneblack; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ +"uname_boot="\ + "setenv bootdir /boot; " \ + "setenv bootfile vmlinuz-${uname_r}; " \ + "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ + "echo loading ${bootdir}/${bootfile} ...; "\ + "run loadimage;" \ + "setenv fdtdir /boot/dtbs/${uname_r}; " \ + "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \ + "run loadfdt;" \ + "else " \ + "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \ + "if test -e mmc ${bootpart} ${fdtdir}/" \ + "${fdtfile}; then " \ + "run loadfdt;" \ + "else " \ + "setenv fdtdir /boot/dtb-${uname_r}; " \ + "if test -e mmc ${bootpart} ${fdtdir}" \ + "/${fdtfile}; then " \ + "run loadfdt;" \ + "else " \ + "setenv fdtdir /boot/dtbs; " \ + "if test -e mmc ${bootpart} ${fdtdir}" \ + "/${fdtfile}; then " \ + "run loadfdt;" \ + "else " \ + "echo; echo unable to find " \ + "[${fdtfile}] " \ + "did you name it correctly?" \ + "echo booting fallback " \ + "[/boot/dtbs/" \ + "${uname_r}" \ + "/${fdtbase}.dtb]...;" \ + "setenv fdtdir /boot/dtbs/" \ + "${uname_r}; " \ + "setenv fdtfile " \ + "${fdtbase}.dtb; " \ + "run loadfdt;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "fi; " \ + "setenv rdfile initrd.img-${uname_r}; " \ + "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \ + "echo loading ${bootdir}/${rdfile} ...; "\ + "run loadrd;" \ + "if test -n ${uuid}; then " \ + "setenv mmcroot UUID=${uuid} ro;" \ + "fi;" \ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \ + "${fdtaddr}] ... ;" \ + "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \ + "else " \ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ +"fi;\0" \ + NANDARGS \ + DFUARGS +#endif + +#define CONFIG_BOOTCOMMAND \ + "gpio set 53; " \ + "i2c mw 0x24 1 0x3e; " \ + "run findfdt; " \ + "setenv mmcdev 0; " \ + "setenv bootpart 0:1; " \ + "run mmcboot;" \ + "gpio clear 56; " \ + "gpio clear 55; " \ + "gpio clear 54; " \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:1; " \ + "run mmcboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE + +/* USB gadget RNDIS */ +#define CONFIG_SPL_MUSB_NEW_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +#endif + +#ifdef CONFIG_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { \ + 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=nand.0:" \ + "128k(NAND.SPL)," \ + "128k(NAND.SPL.backup1)," \ + "128k(NAND.SPL.backup2)," \ + "128k(NAND.SPL.backup3)," \ + "256k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "128k(NAND.u-boot-env)," \ + "128k(NAND.u-boot-env.backup1)," \ + "8m(NAND.kernel)," \ + "-(NAND.rootfs)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_AM33XX_BCH +#endif +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#endif /* !CONFIG_NAND */ + +/* + * For NOR boot, we must set this to the start of where NOR is mapped + * in memory. + */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 +#endif + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* Fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xD022 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#endif /* CONFIG_MUSB_GADGET */ + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL" +#endif + +/* USB Device Firmware Update support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + "dfu_alt_info_nand=" \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9\0" +#else +#define DFU_ALT_INFO_NAND "" +#endif +#define CONFIG_DFU_RAM +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram 0x80200000 0xD80000;" \ + "fdt ram 0x80F80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000\0" +#define DFUARGS \ + "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_NAND +#endif + +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ +#define MTDIDS_DEFAULT "nor0=m25p80-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ + "512k(u-boot),128k(u-boot-env1)," \ + "128k(u-boot-env2),3464k(kernel)," \ + "-(rootfs)" +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + +/* SPI flash. */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* + * NOR Size = 16 MiB + * Number of Sectors/Blocks = 128 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x000000 - 0x07FFFF : U-Boot (512 KiB) + * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) + * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) + * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) + */ +#if defined(CONFIG_NOR) +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "512k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel),-(rootfs)" +#endif +#endif /* NOR support */ + +#endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h index c7719f389a..4aa8550921 100644 --- a/include/configs/beagle_x15.h +++ b/include/configs/beagle_x15.h @@ -59,6 +59,7 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 5df460c96b..58013c6c9b 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -36,8 +36,6 @@ #define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */ #define CONFIG_MACH_TYPE MACH_TYPE_BEAVER -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 49afe46e2a..240fc464bc 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -12,6 +12,31 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ +#define BUR_COMMON_ENV \ +"defaultip=192.168.60.253\0" \ +"defaultsip=192.168.60.254\0" \ +"netconsole=echo switching to network console ...; " \ +"if dhcp; then " \ +"setenv ncip ${serverip}; else " \ +"setenv ncip 192.168.60.254; " \ +"setenv serverip 192.168.60.254; " \ +"setenv gatewayip 192.168.60.254; " \ +"setenv ipaddr 192.168.60.1; " \ +"fi;" \ +"setenv netdisplay0 '" \ +"setcurs 1 9; puts myip; setcurs 10 9; puts ${ipaddr};" \ +"setcurs 1 10;puts serverip; setcurs 10 10; puts ${serverip};" \ +"run netdisplay0; " \ +"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" + +#define CONFIG_CMD_TIME +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_BMP +#define CONFIG_BMP_24BMP +#define CONFIG_BMP_32BPP + #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_AM33XX @@ -47,7 +72,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 4 +#define CONFIG_NET_RETRY_COUNT 2 #define CONFIG_CMD_PING #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ @@ -57,7 +82,9 @@ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" - +/* Network console */ +#define CONFIG_NETCONSOLE 1 +#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and @@ -110,11 +137,13 @@ * we are on so we do not need to rely on the command prompt. We set a * console baudrate of 115200 and use the default baud rate table. */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_MALLOC_LEN (5120 << 10) #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE /* As stated above, the following choices are optional. */ #define CONFIG_SYS_LONGHELP diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 5e13b655c2..55de464acb 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -39,8 +39,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_CARDHU -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9feca1b47b..3eb7886eb6 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -26,11 +26,15 @@ #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 918032bd75..8c63138322 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -17,6 +17,10 @@ #define CONFIG_CM_T3517 /* working with CM-T3517 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -30,7 +34,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h index 2b876fede1..4888c945fe 100644 --- a/include/configs/colibri_t20_iris.h +++ b/include/configs/colibri_t20_iris.h @@ -18,8 +18,6 @@ #define CONFIG_TEGRA_UARTA_SDIO1 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_BOARD_EARLY_INIT_F - /* SD/MMC support */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index ce6f23b8c4..ee6fa1c830 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 Stefan Agner + * Copyright (c) 2013-2015 Stefan Agner * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,18 +11,17 @@ #include "tegra30-common.h" +/* High-level configuration options */ #define V_PROMPT "Colibri T30 # " #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30" -/* Board-specific config */ +/* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C @@ -54,6 +53,25 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +/* Miscellaneous commands */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_FAT_WRITE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 0b04ee67b3..5f5eb3b313 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -32,8 +32,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_DALMORE -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c8739ed294..932640112b 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -23,6 +23,10 @@ #define MACH_TYPE_OMAP3_CPS 2751 #endif #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 /* * High Level Configuration Options @@ -36,7 +40,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 981233a070..ea6e5c0329 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -37,6 +37,10 @@ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD + +/* Add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" /* * Commands configuration diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 70a698ab32..5ce01fb2ae 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -12,6 +12,31 @@ #ifndef _CONFIG_EDMINIV2_H #define _CONFIG_EDMINIV2_H +/* general settings */ +#define CONFIG_SYS_GENERIC_BOARD + +/* + * SPL + */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NOR_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0xffff0000 +#define CONFIG_SPL_MAX_SIZE 0x0000fff0 +#define CONFIG_SPL_STACK 0x00020000 +#define CONFIG_SPL_BSS_START_ADDR 0x00020000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff +#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_UBOOT_BASE 0xfff90000 +#define CONFIG_SYS_UBOOT_START 0x00800000 +#define CONFIG_SYS_TEXT_BASE 0x00800000 + /* * Version number information */ @@ -89,13 +114,9 @@ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_LEGACY #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_BASE 0xfff80000 -#define CONFIG_SYS_FLASH_SECTSZ \ - {16384, 8192, 8192, 32768, \ - 65536, 65536, 65536, 65536, 65536, 65536, 65536} /* auto boot */ #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 59676ae61b..87f8db0fba 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -24,6 +24,9 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + /* Keep L2 Cache Disabled */ #define CONFIG_CMD_CACHE diff --git a/include/configs/flea3.h b/include/configs/flea3.h index edff0f54cf..854ae90bd4 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -22,6 +22,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h deleted file mode 100644 index b555d82ddc..0000000000 --- a/include/configs/galaxy5200.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messatechnik GmbH - * - * (C) Copyright 2009 - * Jon Smirl <jonsmirl@gmail.com> - * - * (C) Copyright 2009 - * Eric Millbrandt, DEKA Research and Development Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_BOARDINFO "galaxy5200" - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFE000000 boot low - * 0x00100000 boot from RAM (for testing only) does not work - */ -#ifdef CONFIG_galaxy5200_LOWBOOT -#define CONFIG_SYS_TEXT_BASE 0xFE000000 -#endif - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */ - /* define gps port conf. */ - /* register later on to */ - /* enable UART function! */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_PING -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_USB -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_FAT - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ -#define CONFIG_SYS_LOWBOOT 1 -#endif -/* RAMBOOT will be defined automatically in memory section */ - -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ - "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ - /* even with bootdelay=0 */ -#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */ -#define CONFIG_RESET_TO_RETRY - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to U-Boot;"\ - "echo" - -#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \ - "bootm ff040000 ff900000 fffc0000" -#define CONFIG_BOOTARGS "console=ttyPSC0,115200" -#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */ - -/* - * EEPROM CAT24WC32 configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ -#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_SIZE 4096 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Flash configuration - */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 -/* - * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this - * variable defined - */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - /* (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Use hardware protection. This seems required, as the BDI uses hardware - * protection. Without this, U-Boot can't work with this sectors as its - * protection is software only by default. - */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/* - * Environment settings - */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ - /* beginning of the EEPROM */ -#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -/* - * SDRAM configuration - */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x71500F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x47770000 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ - /* bootloader or debugger config */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM - -/* End of used area in SPRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Chip Select configuration for NAND flash */ -#define CONFIG_SYS_CS1_START 0x20000000 -#define CONFIG_SYS_CS1_SIZE 0x90000 -#define CONFIG_SYS_CS1_CFG 0x00025b00 - -/* Chip Select configuration for Epson S1D13513 */ -#define CONFIG_SYS_CS3_START 0x10000000 -#define CONFIG_SYS_CS3_SIZE 0x400000 -#define CONFIG_SYS_CS3_CFG 0xffff3d10 - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 -#define CONFIG_NO_AUTOLOAD 1 - -/* - * GPIO configuration - * - * GPS port configuration - * - * [29:31] = 01x - * AC97 on PSC1 - * PSC1_0 -> AC97 SDATA out - * PSC1_1 -> AC97 SDTA in - * PSC1_2 -> AC97 SYNC out - * PSC1_3 -> AC97 bitclock out - * PSC1_4 -> AC97 reset out - * - * [28] = Reserved - * - * [25:27] = 110 - * SPI on PSC2 - * PSC2_0 -> MOSI - * PSC2_1 -> MISO - * PSC2_2 -> n/a - * PSC2_3 -> CLK - * PSC2_4 -> SS - * - * [24] = Reserved - * - * [20:23] = 0001 - * USB on PSC3 - * PSC3_0 -> USB_OE OE out - * PSC3_1 -> USB_TXN Tx- out - * PSC3_2 -> USB_TXP Tx+ out - * PSC3_3 -> USB_TXD - * PSC3_4 -> USB_RXP Rx+ in - * PSC3_5 -> USB_RXN Rx- in - * PSC3_6 -> USB_PWR PortPower out - * PSC3_7 -> USB_SPEED speed out - * PSC3_8 -> USB_SUSPEND suspend - * PSC3_9 -> USB_OVRCURNT overcurrent in - * - * [18:19] = 10 - * Two UARTs - * - * [17] = 0 - * USB differential mode - * - * [16] = 1 - * PCI disabled - * - * [12:15] = 0101 - * Ethernet 100Mbit with MD - * ETH_0 -> ETH Txen - * ETH_1 -> ETH TxD0 - * ETH_2 -> ETH TxD1 - * ETH_3 -> ETH TxD2 - * ETH_4 -> ETH TxD3 - * ETH_5 -> ETH Txerr - * ETH_6 -> ETH MDC - * ETH_7 -> ETH MDIO - * ETH_8 -> ETH RxDv - * ETH_9 -> ETH RxCLK - * ETH_10 -> ETH Collision - * ETH_11 -> ETH TxD - * ETH_12 -> ETH RxD0 - * ETH_13 -> ETH RxD1 - * ETH_14 -> ETH RxD2 - * ETH_15 -> ETH RxD3 - * ETH_16 -> ETH Rxerr - * ETH_17 -> ETH CRS - * - * [9:11] = 111 - * SPI on PSC6 - * PSC6_0 -> MISO - * PSC6_1 -> SS# - * PSC6_2 -> MOSI - * PSC6_3 -> CLK - * - * [8] = 0 - * IrDA/USB 48MHz clock generated internally - * - * [6:7] = 01 - * ATA chip selects on csb_4/5 - * CSB_4 -> ATA_CS0 out - * CSB_5 -> ATA_CS1 out - * - * [5] = 1 - * PSC3_4 is used as CS6 - * - * [4] = 1 - * PSC3_5 is used as CS7 - * - * [2:3] = 00 - * No Alternatives - * - * [1] = 0 - * gpio_wkup_7 is GPIO - * - * [0] = 0 - * gpio_wkup_6 is GPIO - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_CRC32_VERIFY 1 - -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - -#define CONFIG_VERSION_VARIABLE 1 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -/* no burst access on the LPB */ -#define CONFIG_SYS_CS_BURST 0x00000000 -/* one deadcycle for the 33MHz statemachine */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 - -#define CONFIG_SYS_BOOTCS_CFG 0x0002d900 -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * USB settings - */ -#define CONFIG_USB_CLOCK 0x0001bbbb -/* USB is on PSC3 */ -#define CONFIG_PSC3_USB -#define CONFIG_USB_CONFIG 0x00000100 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* - * IDE/ATA stuff Supports IDE harddisk - */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CONFIG_IDE_PREINIT -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 -#define CONFIG_ATAPI 1 - -/* we enable IDE and FAT support, so we also need partition support */ -#define CONFIG_DOS_PARTITION 1 - -/* - * Open Firmware flat tree - */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600" - -#endif /* __CONFIG_H */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 404c56af10..0ac198df8d 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -26,6 +26,11 @@ #endif /* + * Generic board support + */ +#define CONFIG_SYS_GENERIC_BOARD + +/* * Version number information */ #define CONFIG_IDENT_STRING "\nMarvell-gplugD" diff --git a/include/configs/harmony.h b/include/configs/harmony.h index ff9fbc9965..ad3dcdb7ba 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -27,9 +27,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */ - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 310d5e2106..664a2b25f3 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -18,6 +18,7 @@ /* * Board */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DRIVER_TI_EMAC #define CONFIG_BARIX_IPAM390 diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 0a79c7cfc3..8c016b7955 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index c8df23b534..ec133f9e92 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_KM8309_COMMON_H #define __CONFIG_KM8309_COMMON_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 149895cb7e..058b0ab42b 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -23,6 +23,9 @@ #ifndef __CONFIG_KM8321_COMMON_H #define __CONFIG_KM8321_COMMON_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/km8360.h b/include/configs/km8360.h index f5ac32a332..04cde46cc5 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* KMBEC FPGA (PRIO) */ #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 diff --git a/include/configs/korat.h b/include/configs/korat.h deleted file mode 100644 index 5494a6007d..0000000000 --- a/include/configs/korat.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Larry Johnson, lrj@acm.org - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * korat.h - configuration for Korat board - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_SYS_CLK_FREQ 33333333 - -#ifdef CONFIG_KORAT_PERMANENT -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 -#else -#define CONFIG_SYS_TEXT_BASE 0xF7F60000 -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Manufacturer's information serial EEPROM parameters - */ -#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */ -#define MAN_INFO_FIELD 2 -#define MAN_INFO_LENGTH 9 -#define MAN_MAC_ADDR_FIELD 3 -#define MAN_MAC_ADDR_LENGTH 12 - -/* - * Base addresses -- Note these are effective addresses where the actual - * resources get mapped (not physical addresses). - */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH0_SIZE 0x01000000 -#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE) -#define CONFIG_SYS_FLASH1_TOP 0xF8000000 -#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000 -#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE) -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000) - -#define CONFIG_SYS_USB2D0_BASE 0xe0000100 -#define CONFIG_SYS_USB_DEVICE 0xe0000000 -#define CONFIG_SYS_USB_HOST 0xe0000400 -#define CONFIG_SYS_CPLD_BASE 0xc0000000 - -/* - * Initial RAM & stack pointer - */ -/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */ -#undef CONFIG_SYS_INIT_RAM_DCACHE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR } - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * DDR SDRAM - */ -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ -#define CONFIG_DDR_ECC /* Use ECC when available */ -#define SPD_EEPROM_ADDRESS {0x50} -#define CONFIG_PROG_SDRAM_TLB -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */ - /* per 440EPx Errata CHIP_11 */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C RTC */ -#define CONFIG_RTC_M41T60 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* I2C SYSMON (LM73) */ -#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */ -#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_MIN_TEMP -30 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#define CONFIG_HOSTNAME korat - -/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u_boot=korat/u-boot.bin\0" \ - "load=tftp 200000 ${u_boot}\0" \ - "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \ - "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \ - "F7F60000 F7FBFFFF\0" \ - "upd=run load update\0" \ - "bootfile=korat/uImage\0" \ - "dtb=korat/korat.dtb\0" \ - "kernel_addr=F4000000\0" \ - "ramdisk_addr=F4400000\0" \ - "dtb_addr=F41E0000\0" \ - "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \ - "cp.b ${fileaddr} F4000000 ${filesize}\0" \ - "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \ - "cp.b ${fileaddr} F41E0000 ${filesize}\0" \ - "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \ - "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \ - "${dtb}\0" \ - "rd_size=73728\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "ramdisk_size=${rd_size}\0" \ - "usbdev=sda1\0" \ - "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \ - "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "pciclk=33\0" \ - "addide=setenv bootargs ${bootargs} ide=reverse " \ - "idebus=${pciclk}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_cf=run usbargs addide addip addtty; " \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "flash_nfs=run nfsargs addide addip addtty; " \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "flash_self=run ramargs addip addtty; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_cf" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ -#define CONFIG_PHY_DYNAMIC_ANEG 1 - -#undef CONFIG_PHY_RESET /* Don't do software PHY reset */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */ - /* buffers & descriptors */ -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 3 - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* Comment this out to enable USB 1.1 device */ -#define USB_2_0_DEVICE - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ - CONFIG_SYS_POST_UART) - -#define CONFIG_LOGBUFFER -#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ - -#define CONFIG_SUPPORT_VFAT - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * Korat-specific options - */ -#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */ - -/* - * PCI stuff - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ - /* CONFIG_SYS_PCI_MEMBASE */ -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT -#define CONFIG_SYS_PCI_MASTER_INIT -#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data have to be in the - * first 8 MB of memory, since this is the maximum mapped by the Linux kernel - * during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (NOR-FLASH) initialization */ -#if CONFIG_SYS_FLASH0_SIZE == 0x01000000 -#define CONFIG_SYS_EBC_PB0AP 0x04017300 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000) -#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 -#define CONFIG_SYS_EBC_PB0AP 0x04017300 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000) -#else -#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE -#endif - -/* Memory Bank 1 (NOR-FLASH) initialization */ -#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000 -#define CONFIG_SYS_EBC_PB1AP 0x04017300 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000) -#else -#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE -#endif - -/* Memory Bank 2 (CPLD) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x04017300 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000) - -/* - * GPIO Setup - * - * Korat GPIO usage: - * - * Init. - * Pin Source I/O value Function - * ------ ------ --- ----- --------------------------------- - * GPIO00 Alt1 I/O x PerAddr07 - * GPIO01 Alt1 I/O x PerAddr06 - * GPIO02 Alt1 I/O x PerAddr05 - * GPIO03 GPIO x x GPIO03 to expansion bus connector - * GPIO04 GPIO x x GPIO04 to expansion bus connector - * GPIO05 GPIO x x GPIO05 to expansion bus connector - * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) - * GPIO07 Alt1 O x PerCS2 (CPLD) - * GPIO08 Alt1 O x PerCS3 to expansion bus connector - * GPIO09 Alt1 O x PerCS4 to expansion bus connector - * GPIO10 Alt1 O x PerCS5 to expansion bus connector - * GPIO11 Alt1 I x PerErr - * GPIO12 GPIO O 0 ATMega !Reset - * GPIO13 GPIO x x Test Point 2 (TP2) - * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) - * GPIO15 GPIO O 0 CPU Run LED !On - * GPIO16 Alt1 O x GMC1TxD0 - * GPIO17 Alt1 O x GMC1TxD1 - * GPIO18 Alt1 O x GMC1TxD2 - * GPIO19 Alt1 O x GMC1TxD3 - * GPIO20 Alt1 I x RejectPkt0 - * GPIO21 Alt1 I x RejectPkt1 - * GPIO22 GPIO I x PGOOD_DDR - * GPIO23 Alt1 O x SCPD0 - * GPIO24 Alt1 O x GMC0TxD2 - * GPIO25 Alt1 O x GMC0TxD3 - * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) - * GPIO27 GPIO O 0 PHY #0 1000BASE-X select - * GPIO28 GPIO O 0 PHY #1 1000BASE-X select - * GPIO29 GPIO I x Test jumper !Present - * GPIO30 GPIO I x SFP module #0 !Present - * GPIO31 GPIO I x SFP module #1 !Present - * - * GPIO32 GPIO O 1 SFP module #0 Tx !Enable - * GPIO33 GPIO O 1 SFP module #1 Tx !Enable - * GPIO34 Alt2 I x !UART1_CTS - * GPIO35 Alt2 O x !UART1_RTS - * GPIO36 Alt1 I x !UART0_CTS - * GPIO37 Alt1 O x !UART0_RTS - * GPIO38 Alt2 O x UART1_Tx - * GPIO39 Alt2 I x UART1_Rx - * GPIO40 Alt1 I x IRQ0 (Ethernet 0) - * GPIO41 Alt1 I x IRQ1 (Ethernet 1) - * GPIO42 Alt1 I x IRQ2 (PCI interrupt) - * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) - * GPIO44 xxxx x x (grounded through pulldown) - * GPIO45 GPIO O 0 PHY #0 Enable - * GPIO46 GPIO O 0 PHY #1 Enable - * GPIO47 GPIO I x Reset switch !Pressed - * GPIO48 GPIO I x Shutdown switch !Pressed - * GPIO49 xxxx x x (reserved for trace port) - * . . . . . - * . . . . . - * . . . . . - * GPIO63 xxxx x x (reserved for trace port) - */ - -#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12 -#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13 -#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27 -#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28 -#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30 -#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31 -#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32 -#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33 -#define CONFIG_SYS_GPIO_PHY0_EN 45 -#define CONFIG_SYS_GPIO_PHY1_EN 46 -#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47 - -/* - * PPC440 GPIO Configuration - */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ -{ \ -/* GPIO Core 0 */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ -}, \ -{ \ -/* GPIO Core 1 */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ -} \ -} - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h index 29b263f301..dd30df27b0 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -14,6 +14,11 @@ #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ +#define CONFIG_AM335X_LCD +#define CONFIG_LCD +#define CONFIG_LCD_NOSTDOUT +#define CONFIG_SYS_WHITE_ON_BLACK +#define LCD_BPP LCD_COLOR32 /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -38,57 +43,71 @@ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SPL_MMC_SUPPORT -#undef CONFIG_SPL_OS_BOOT -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - -/* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ - -#endif /* CONFIG_SPL_OS_BOOT */ - -/* Always 128 KiB env size */ -#define CONFIG_ENV_SIZE (128 << 10) +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=0\0" \ - "loadaddr=0x80100000\0" \ - "bootfile=arimg\0" \ - "usbboot=echo Booting from USB-Stick ...; " \ - "usb start; " \ - "fatload usb 0 ${loadaddr} ${bootfile}; " \ - "usb stop; " \ - "go ${loadaddr};\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload 0; " \ - "dhcp; " \ - "tftp ${loadaddr} arimg; " \ - "go ${loadaddr}\0" \ - "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ - "usb start; " \ - "fatload usb 0 0x80000000 updateubootusb.img; " \ - "source;\0" \ - "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ - "setenv autoload 0; " \ - "dhcp;" \ - "tftp 0x80000000 updateUBOOT.img;" \ - "source;\0" +BUR_COMMON_ENV \ +"vx_romfsbase=0x800E0000\0" \ +"vx_romfssize=0x20000\0" \ +"vx_memtop=0x8FBEF000\0" \ +"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \ +"autoload=0\0" \ +"loadaddr=0x80100000\0" \ +"logoaddr=0x82000000\0" \ +"defaultARlen=0x8000\0" \ +"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \ +"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \ +"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \ + "bmp display ${logoaddr} 0 0\0" \ +"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \ + "bmp display ${logoaddr} 0 0\0" \ +"mmcboot=echo booting AR from eMMC-flash ...; "\ + "run logo0 || run logo1; " \ + "run loadromfs; " \ + "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \ + "run defaultAR;\0" \ +"netboot=echo booting AR from network ...; " \ + "run loadromfs; " \ + "tftp ${loadaddr} arimg && go ${loadaddr}; " \ + "puts 'networkboot failed!';\0" \ +"usbupdate=echo updating u-boot from usb ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img && source; " \ + "puts 'usbupdate failed!'\0" \ +"netscript=echo running script from network (tftp) ...; " \ + "tftp 0x80000000 netscript.img && source; " \ + "puts 'netscript load failed!'\0" \ +"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \ + "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \ +"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \ + "if tftp 0x80100000 arimg.bin; " \ + "then mmc write 0x80100000 800 ${defaultARlen}; " \ + "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \ +"netupdateROMFS=echo updating romfs from network (tftp) ...; " \ + "if tftp 0x80100000 romfs.bin; " \ + "then mmc write 0x80100000 700 100; " \ + "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0" + #endif /* !CONFIG_SPL_BUILD*/ #define CONFIG_BOOTCOMMAND \ "run usbupdate;" -#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ +#define CONFIG_BOOTDELAY 0 /* undefine command which we not need here */ -#undef CONFIG_BOOTM_LINUX #undef CONFIG_BOOTM_NETBSD #undef CONFIG_BOOTM_PLAN9 #undef CONFIG_BOOTM_RTEMS -#undef CONFIG_GZIP -#undef CONFIG_ZLIB +#undef CONFIG_CMD_CRC32 + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMD_BOOTZ /* USB configuration */ #define CONFIG_USB_MUSB_DSPS @@ -100,6 +119,8 @@ #define CONFIG_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST #ifdef CONFIG_MUSB_HOST #define CONFIG_CMD_USB diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 17a1cde039..f80efedeb2 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -15,6 +15,10 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 +/* Errata fixes */ +#define CONFIG_ARM_ERRATA_828024 +#define CONFIG_ARM_ERRATA_826974 + /* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 26eb220354..3fd3184245 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -16,6 +16,10 @@ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX @@ -26,7 +30,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #define CONFIG_OF_LIBFDT #define CONFIG_FIT diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index ac5208fa0d..f721a4d6a2 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -20,9 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 4ae9afd4e5..d2ef1af62c 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 09d55ce9b8..f8cd39d74d 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -19,6 +19,7 @@ #define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e1..152a6e564b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -29,6 +29,10 @@ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 @@ -42,7 +46,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <asm/arch/mem.h> #include <linux/stringify.h> diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index cf331ab207..5397599911 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -21,8 +21,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h new file mode 100644 index 0000000000..3030054949 --- /dev/null +++ b/include/configs/omap3_cairo.h @@ -0,0 +1,286 @@ +/* + * Configuration settings for the QUIPOS Cairo board. + * + * Copyright (C) DENX GmbH + * + * Author : + * Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Derived from EVM code by + * Manikandan Pillai <mani.pillai@ti.com> + * Itself derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * Also derived from include/configs/omap3_beagle.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP3_CAIRO_CONFIG_H +#define __OMAP3_CAIRO_CONFIG_H + +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#define CONFIG_NAND + +#include <configs/ti_omap3_common.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_REVISION_TAG 1 +#define CONFIG_ENV_OVERWRITE + +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS 1 + +/* Probe all devices */ +#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } + +#define CONFIG_NAND + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_SETEXPR /* Evaluate expressions */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK + +/* Disable some commands */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_LED 1 + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +/* override default CONFIG_BOOTDELAY */ +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "machid=ffffffff\0" \ + "fdt_high=0x87000000\0" \ + "baudrate=115200\0" \ + "ethaddr=00:50:C2:7E:90:F0\0" \ + "fec_addr=00:50:C2:7E:90:F0\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.2.9\0" \ + "gateway=192.168.2.1\0" \ + "serverip=192.168.2.10\0" \ + "nfshost=192.168.2.10\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootargs_mmc_ramdisk=mem=128M " \ + "console=ttyO1,115200n8 " \ + "root=/dev/ram0 rw " \ + "initrd=0x81600000,16M " \ + "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ + "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ + "mmcboot=mmc init; " \ + "fatload mmc 0 0x80000000 uImage; " \ + "fatload mmc 0 0x81600000 ramdisk.gz; " \ + "setenv bootargs ${bootargs_mmc_ramdisk}; " \ + "bootm 0x80000000\0" \ + "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ + "root=/dev/nfs " \ + "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ + "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ + "omap_vout.vid1_static_vrfb_alloc=y\0" \ + "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ + "bootm 0x80000000\0" \ + "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ + "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ + "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ + "omapfb.rotate_type=1\0" \ + "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ + "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ + "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ + "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ + "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ + "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ + "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ + "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ + "nand erase 0 20000; " \ + "fatload mmc 0 0x81600000 MLO; " \ + "nandecc hw; " \ + "nand write.i 0x81600000 0 20000;\0" \ + "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ + "nand erase 80000 40000; " \ + "fatload mmc 0 0x81600000 u-boot.bin; " \ + "nandecc sw; " \ + "nand write.i 0x81600000 80000 40000;\0" \ + "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ + "nand erase 280000 300000; " \ + "fatload mmc 0 0x81600000 uImage; " \ + "nandecc sw; " \ + "nand write.i 0x81600000 280000 300000;\0" \ + "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ + "nandecc sw; " \ + "nand write.jffs2 0x680000 0xFF ${filesize}; " \ + "nand erase 680000 ${filesize}; " \ + "nand write.jffs2 81600000 680000 ${filesize};\0" \ + "flash_scrub=nand scrub; " \ + "run flash_xloader; " \ + "run flash_uboot; " \ + "run flash_kernel; " \ + "run flash_rootfs;\0" \ + "flash_all=run ledred; " \ + "nand erase.chip; " \ + "run ledorange; " \ + "run flash_xloader; " \ + "run flash_uboot; " \ + "run flash_kernel; " \ + "run flash_rootfs; " \ + "run ledgreen; " \ + "run boot_nand; \0" \ + +#define CONFIG_BOOTCOMMAND \ + "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ + "else run boot_nand; fi" + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#endif + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#define CONFIG_OMAP3_SPI + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Defines for SPL */ +#define CONFIG_SPL_OMAP3_ID_NAND + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + +/* env defaults */ +#define CONFIG_BOOTFILE "uImage" + +/* Override OMAP3 common serial console configuration from UART3 + * to UART2. + * + * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) + * are needed and peripheral clocks for UART2 must be enabled in + * function per_clocks_enable(). + */ +#undef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 2 +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SYS_NS16550_COM3 +#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 +#undef CONFIG_SERIAL3 +#define CONFIG_SERIAL2 +#endif + +/* Keep old prompt in case some existing script depends on it */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "Cairo # " + +/* Provide MACH_TYPE for compatibility with non-DT kernels */ +#define MACH_TYPE_OMAP3_CAIRO 3063 +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#endif /* __OMAP3_CAIRO_CONFIG_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bdc08f586..4e587e10ff 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -18,7 +18,7 @@ #define __OMAP3EVM_CONFIG_H #include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index e7df15400d..370f21e3ee 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,10 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 1185f42550..a7acc1becb 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_MMC_H #include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 4427e88b7e..c6cad93889 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_NAND_H #include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index aeb385f5ff..13cd35b16a 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -18,13 +18,17 @@ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SYS_TEXT_BASE 0x80400000 #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index bf1d34dedb..b61297f9ee 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -23,11 +23,15 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 45feeb5773..11d7b86eb1 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -17,11 +17,15 @@ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index ac307eb456..1ca79d4ee4 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -23,11 +23,15 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * NOTE: these #defines presume standard SDP jumper settings. diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c5d742c2bd..611cd5e1a3 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -22,7 +22,7 @@ #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <configs/ti_omap3_common.h> /* Remove SPL boot option - we do not support that on LDP yet */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 45bb47088b..284419ffc8 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -30,9 +30,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/plutux.h b/include/configs/plutux.h index b663b89d2c..6878ed7995 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -20,9 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 2516a3e97e..2d264d2ef7 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -15,6 +15,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 5f77051d13..4442064db9 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -32,9 +32,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */ - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h new file mode 100644 index 0000000000..668a91e116 --- /dev/null +++ b/include/configs/socfpga_arria5.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__ + +#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" +#include "../../board/altera/socfpga/pll_config.h" + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +#define CONFIG_REGEX /* Enable regular expression support */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_arria5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ee227fef0f..6d9347204b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -19,8 +19,7 @@ * High level configuration */ #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c3d958cb30..676144a668 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -21,6 +21,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU #define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE @@ -33,6 +34,8 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_REGEX /* Enable regular expression support */ @@ -66,6 +69,12 @@ #endif +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_cyclone5 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index a11f4ed2e1..16281f5ba8 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -11,6 +11,8 @@ * Common configurations used for both spear3xx as well as spear6xx */ +#define CONFIG_SYS_GENERIC_BOARD + /* U-boot Load Address */ #define CONFIG_SYS_TEXT_BASE 0x00700000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index bd7d049277..1f7a1cb1f4 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -204,8 +204,6 @@ #define CONFIG_SYS_I2C_SOFT #define CONFIG_SYS_I2C_SOFT_SPEED 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 -#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ /* We use pin names in Kconfig and sunxi_name_to_gpio() */ #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl @@ -213,6 +211,11 @@ extern int soft_i2c_gpio_sda; extern int soft_i2c_gpio_scl; #endif +#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ +#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ +#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ #endif #define CONFIG_CMD_I2C diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 38288f69aa..2d12e86566 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -17,6 +17,10 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -25,7 +29,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index dd69d4ebab..49ed79ffbc 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -21,13 +21,17 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define MACH_TYPE_OMAP3_TAO3530 2836 #define CONFIG_SDRC /* Has an SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> /* * Display CPU and Board information diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index e37b23359b..cfa7fb12d7 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -19,8 +19,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/tec.h b/include/configs/tec.h index 9ea4ff4971..13c24c960c 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -20,9 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index fa6ccc16ee..2cf1f68404 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -36,7 +36,12 @@ /* * Size of malloc() pool */ +#ifdef CONFIG_DFU_MMC +#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ + CONFIG_SYS_DFU_DATA_BUF_SIZE) +#else #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#endif #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ @@ -145,6 +150,8 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index c0c1060216..110a4f8795 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -127,7 +127,11 @@ * we are on so we do not need to rely on the command prompt. We set a * console baudrate of 115200 and use the default baud rate table. */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) +#ifdef CONFIG_DFU_MMC +#define CONFIG_SYS_MALLOC_LEN ((16 << 20) + CONFIG_SYS_DFU_DATA_BUF_SIZE) +#else +#define CONFIG_SYS_MALLOC_LEN (16 << 20) +#endif #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "U-Boot# " #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 840e108e05..429b109afa 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -16,12 +16,17 @@ #include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #ifndef CONFIG_SPL_BUILD # define CONFIG_OMAP_SERIAL #endif +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + /* The chip has SDRC controller */ #define CONFIG_SDRC diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd3..09f05f18a7 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,9 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64 /* Use General purpose timer 1 */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 10ac4a46bc..7426bde8a0 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,6 +19,10 @@ /* High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /* @@ -32,7 +36,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 59f4f6767b..81be8a2204 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE -#define CONFIG_BOARD_EARLY_INIT_F - /* SPI */ #define CONFIG_TEGRA20_SFLASH #define CONFIG_SPI_FLASH diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 9a6207048c..a6c7d5f136 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -14,6 +14,19 @@ #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ +#define CONFIG_AM335X_LCD +#define CONFIG_LCD +#define CONFIG_LCD_NOSTDOUT +#define CONFIG_SYS_WHITE_ON_BLACK +#define LCD_BPP LCD_COLOR32 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_OMAP_WATCHDOG +#define CONFIG_SPL_WATCHDOG_SUPPORT +/* Bootcount using the RTC block */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -22,6 +35,8 @@ /* Support both device trees and ATAGs. */ #define CONFIG_OF_LIBFDT +#define CONFIG_USE_FDT /* use fdt within board code */ +#define CONFIG_OF_BOARD_SETUP #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -79,8 +94,8 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif /* CONFIG_NAND */ -/* Always 128 KiB env size */ -#define CONFIG_ENV_SIZE (128 << 10) +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) #ifdef CONFIG_NAND #define NANDARGS \ @@ -103,47 +118,83 @@ #ifdef CONFIG_MMC #define MMCARGS \ - "silent=1\0" +"dtbdev=mmc\0" \ +"dtbpart=0:1\0" \ +"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \ + "bmp display ${loadaddr} 0 0\0" \ +"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \ + "bmp display ${loadaddr} 0 0\0" \ +"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \ +"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \ + "rootfstype=ext4\0" \ +"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \ + "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \ + "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \ + "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \ +"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \ + "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \ + "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \ +"defboot=run logo0 || run logo1; " \ + "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \ + "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \ + "run ramboot; run usbupdate;\0" \ +"bootlimit=1\0" \ +"altbootcmd=run logo0 || run logo1; " \ + "run mmcboot0;\0" \ +"upduboot=dhcp; " \ + "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \ + "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0" #else #define MMCARGS "" #endif /* CONFIG_MMC */ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=0\0" \ - "loadaddr=0x80200000\0" \ - "bootfile=zImage\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "rootpath=/tftpboot/tseries/rootfs-small\0" \ - "nfsopts=nolock\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "run netargs; " \ - "bootm ${loadaddr}\0" \ - "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ - "usb start; " \ - "fatload usb 0 0x80000000 updateubootusb.img; " \ - "source;\0" \ - "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ - "setenv autoload 0; " \ - "dhcp;" \ - "tftp 0x80000000 updateUBOOT.img;" \ - "source;\0" \ - NANDARGS \ - MMCARGS +BUR_COMMON_ENV \ +"verify=no\0" \ +"autoload=0\0" \ +"dtb=bur-ppt-ts30.dtb\0" \ +"dtbaddr=0x80100000\0" \ +"loadaddr=0x80200000\0" \ +"ramaddr=0x80A00000\0" \ +"kernel=zImage\0" \ +"ramdisk=rootfs.cpio.uboot\0" \ +"console=ttyO0,115200n8\0" \ +"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \ +"nfsroot=/tftpboot/tseries/rootfs-small\0" \ +"nfsopts=nolock\0" \ +"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \ +"netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \ + "ip=dhcp\0" \ +"netboot=echo Booting from network ...; " \ + "dhcp; " \ + "tftp ${loadaddr} ${kernel}; " \ + "tftp ${dtbaddr} ${dtb}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ +"ramboot=echo Booting from network into RAM ...; "\ + "if dhcp; then; " \ + "tftp ${loadaddr} ${kernel}; " \ + "tftp ${ramaddr} ${ramdisk}; " \ + "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \ + "then; else tftp ${dtbaddr} ${dtb}; fi;" \ + "run mmcroot0; " \ + "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \ +"usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \ +"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \ +NANDARGS \ +MMCARGS #endif /* !CONFIG_SPL_BUILD*/ #define CONFIG_BOOTCOMMAND \ - "run mmcboot1;" -#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */ + "run defboot;" +#define CONFIG_BOOTDELAY 0 #ifdef CONFIG_NAND /* @@ -260,6 +311,10 @@ #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FS_GENERIC #endif /* CONFIG_MMC, ... */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 00787bbb28..bce94b3fdc 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * High Level Configuration Options */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 8880de86c4..4594002424 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -21,8 +21,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/ventana.h b/include/configs/ventana.h index f195f8a6ea..62bec9955e 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -21,9 +21,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */ - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 7fb28a54ba..810eef12de 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -29,8 +29,6 @@ /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ -#define CONFIG_SYS_NO_FLASH - #define CONFIG_SUPPORT_RAW_INITRD /* Cache Definitions */ @@ -56,14 +54,6 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT - -/* SMP Spin Table Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) -#else -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#endif - /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x00000000 #define V2M_PA_CS1 0x14000000 @@ -79,13 +69,6 @@ #define V2M_BASE 0x80000000 -/* - * Physical addresses, offset from V2M_PA_CS0-3 - */ -#define V2M_NOR0 (V2M_PA_CS0) -#define V2M_NOR1 (V2M_PA_CS4) -#define V2M_SRAM (V2M_PA_CS1) - /* Common peripherals relative to CS7. */ #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) @@ -146,9 +129,17 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) -/* SMSC91C111 Ethernet Configuration */ +/* Ethernet Configuration */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +/* The real hardware Versatile express uses SMSC9118 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT 1 +#define CONFIG_SMC911X_BASE (0x018000000) +#else +/* The Vexpress64 simulators use SMSC91C111 */ #define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE (0x01A000000) +#endif /* PL011 Serial Configuration */ #define CONFIG_PL011_SERIAL @@ -175,7 +166,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PXE #define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY @@ -237,7 +227,7 @@ "fdt_addr_r=0x83000000\0" \ "fdt_high=0xa0000000\0" -#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0" #define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ "$initrd_addr_r:$initrd_size $fdt_addr_r" #define CONFIG_BOOTDELAY -1 @@ -258,4 +248,27 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 /* max command args */ +/* Flash memory is available on the Juno board only */ +#ifndef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_NO_FLASH +#else +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ + +/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ + +#endif + #endif /* __VEXPRESS_AEMV8A_H */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 175311cad9..c7730fc862 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -18,6 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * Top level Makefile configuration choices */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h index e083cbd07f..94f151e9be 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER -#define CONFIG_BOARD_EARLY_INIT_F - /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 8e1c7a44cc..48b869268b 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 diff --git a/include/configs/x600.h b/include/configs/x600.h index 04187c0a31..241bf65f30 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -16,6 +16,7 @@ */ #define CONFIG_SPEAR600 /* SPEAr600 SoC */ #define CONFIG_X600 /* on X600 board */ +#define CONFIG_SYS_GENERIC_BOARD #include <asm/arch/hardware.h> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 864528a5ea..485babd824 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -255,7 +255,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) -#define CONFIG_SYS_MALLOC_LEN 0xC00000 +#define CONFIG_SYS_MALLOC_LEN 0x1400000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/include/e500.h b/include/e500.h index 5884a224d2..255f46bf1e 100644 --- a/include/e500.h +++ b/include/e500.h @@ -11,6 +11,9 @@ typedef struct { unsigned long freq_processor[CONFIG_MAX_CPUS]; +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS]; +#endif unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; @@ -24,6 +27,14 @@ typedef struct #ifdef CONFIG_SYS_DPAA_PME unsigned long freq_pme; #endif +#ifdef CONFIG_SYS_CPRI + unsigned long freq_cpri; +#endif +#ifdef CONFIG_SYS_MAPLE + unsigned long freq_maple; + unsigned long freq_maple_ulb; + unsigned long freq_maple_etvpe; +#endif #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK unsigned char diff_sysclk; #endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 1233dfb280..5ac515d87d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -168,7 +168,7 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ - COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */ + COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_COUNT, }; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index dbfae68ef4..ebb1ac6d40 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -180,7 +180,7 @@ struct jr_regs { * related information */ struct sg_entry { -#ifdef defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) +#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) uint32_t addr_lo; /* Memory Address - lo */ uint16_t addr_hi; /* Memory Address of start of buffer - hi */ uint16_t reserved_zero; diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h new file mode 100644 index 0000000000..b6794cefcc --- /dev/null +++ b/include/fsl_sec_mon.h @@ -0,0 +1,58 @@ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2015 Freescale Semiconductor, Inc. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SEC_MON_H +#define __FSL_SEC_MON_H + +#include <common.h> +#include <asm/io.h> + +#ifdef CONFIG_SYS_FSL_SEC_MON_LE +#define sec_mon_in32(a) in_le32(a) +#define sec_mon_out32(a, v) out_le32(a, v) +#define sec_mon_in16(a) in_le16(a) +#define sec_mon_clrbits32 clrbits_le32 +#define sec_mon_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_MON_BE) +#define sec_mon_in32(a) in_be32(a) +#define sec_mon_out32(a, v) out_be32(a, v) +#define sec_mon_in16(a) in_be16(a) +#define sec_mon_clrbits32 clrbits_be32 +#define sec_mon_setbits32 setbits_be32 +#else +#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined +#endif + +struct ccsr_sec_mon_regs { + u8 reserved0[0x04]; + u32 hp_com; /* 0x04 SEC_MON_HP Command Register */ + u8 reserved2[0x0c]; + u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ +}; + +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ +#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ +#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ +#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ +#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ + +/* + * SEC_MON read. This specifies the possible reads + * from the SEC_MON + */ +enum { + SEC_MON_SSM_ST, + SEC_MON_SW_FSV, + SEC_MON_SW_SV, +}; + +int change_sec_mon_state(uint32_t initial_state, uint32_t final_state); + +#endif /* __FSL_SEC_MON_H */ diff --git a/include/fsl_secboot_err.h b/include/fsl_secboot_err.h new file mode 100644 index 0000000000..afc50a80ca --- /dev/null +++ b/include/fsl_secboot_err.h @@ -0,0 +1,128 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_SECBOOT_ERR_H +#define _FSL_SECBOOT_ERR_H + +#define ERROR_ESBC_PAMU_INIT 0x100000 +#define ERROR_ESBC_SEC_RESET 0x200000 +#define ERROR_ESBC_SEC_INIT 0x400000 +#define ERROR_ESBC_SEC_DEQ 0x800000 +#define ERROR_ESBC_SEC_DEQ_TO 0x1000000 +#define ERROR_ESBC_SEC_ENQ 0x2000000 +#define ERROR_ESBC_SEC_JOBQ_STATUS 0x4000000 +#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH 0x1 +#define ERROR_ESBC_CLIENT_HDR_LOC 0x2 +#define ERROR_ESBC_CLIENT_HEADER_BARKER 0x4 +#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN 0x8 +#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN 0x10 +#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED 0x11 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY 0x12 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM 0x13 +#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN 0x14 +#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED 0x15 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY 0x16 +#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM 0x17 +#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18 +#define ERROR_IE_TABLE_NOT_FOUND 0x19 +#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20 +#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40 +#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80 +#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100 +#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP 0x200 +#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY 0x400 +#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM 0x800 +#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS 0x1000 +#define ERROR_ESBC_CLIENT_BAD_ADDRESS 0x2000 +#define ERROR_ESBC_CLIENT_MISC 0x4000 +#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD 0x8000 +#define ERROR_ESBC_CLIENT_HEADER_SG 0x10000 +#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE 0x20000 +#define ERROR_ESBC_WRONG_CMD 0x40000 +#define ERROR_ESBC_MISSING_BOOTM 0x80000 +#define ERROR_ESBC_CLIENT_MAX 0x0 + +struct fsl_secboot_errcode { + int errcode; + const char *name; +}; + +static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = { + { ERROR_ESBC_PAMU_INIT, + "Error in initializing PAMU"}, + { ERROR_ESBC_SEC_RESET, + "Error in resetting Job ring of SEC"}, + { ERROR_ESBC_SEC_INIT, + "Error in initializing SEC"}, + { ERROR_ESBC_SEC_ENQ, + "Error in enqueue operation by SEC"}, + { ERROR_ESBC_SEC_DEQ_TO, + "Dequeue operation by SEC is timed out"}, + { ERROR_ESBC_SEC_DEQ, + "Error in dequeue operation by SEC"}, + { ERROR_ESBC_SEC_JOBQ_STATUS, + "Error in status of the job submitted to SEC"}, + { ERROR_ESBC_CLIENT_CPUID_NO_MATCH, + "Current core is not boot core i.e core0" }, + { ERROR_ESBC_CLIENT_HDR_LOC, + "Header address not in allowed memory range" }, + { ERROR_ESBC_CLIENT_HEADER_BARKER, + "Wrong barker code in header" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_LEN, + "Wrong public key length in header" }, + { ERROR_ESBC_CLIENT_HEADER_SIG_LEN, + "Wrong signature length in header" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN, + "Public key length not twice of signature length" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1, + "Public key Modulus most significant bit not set" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2, + "Public key Modulus in header not odd" }, + { ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD, + "Signature not less than modulus" }, + { ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP, + "Entry point not in allowed space or one of the SG entries" }, + { ERROR_ESBC_CLIENT_HASH_COMPARE_KEY, + "Public key hash comparison failed" }, + { ERROR_ESBC_CLIENT_HASH_COMPARE_EM, + "RSA verification failed" }, + { ERROR_ESBC_CLIENT_SSM_TRUSTSTS, + "SNVS not in TRUSTED state" }, + { ERROR_ESBC_CLIENT_BAD_ADDRESS, + "Bad address error" }, + { ERROR_ESBC_CLIENT_MISC, + "Miscallaneous error" }, + { ERROR_ESBC_CLIENT_HEADER_SG, + "No SG support" }, + { ERROR_ESBC_CLIENT_HEADER_IMG_SIZE, + "Invalid Image size" }, + { ERROR_ESBC_WRONG_CMD, + "Unknown cmd/Wrong arguments. Core in infinite loop"}, + { ERROR_ESBC_MISSING_BOOTM, + "Bootm command missing from bootscript" }, + { ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED, + "Selected key is revoked" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY, + "Wrong key entry" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM, + "Wrong key is selected" }, + { ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN, + "Wrong srk public key len in header" }, + { ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED, + "Selected IE key is revoked" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY, + "Wrong key entry in IE Table" }, + { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM, + "Wrong IE key is selected" }, + { ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN, + "Wrong IE public key len in header" }, + { ERROR_IE_TABLE_NOT_FOUND, + "Information about IE Table missing" }, + { ERROR_ESBC_CLIENT_MAX, "NULL" } +}; + +void fsl_secboot_handle_error(int error); +#endif diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h new file mode 100644 index 0000000000..353a123ee5 --- /dev/null +++ b/include/fsl_sfp.h @@ -0,0 +1,85 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_SFP_SNVS_ +#define _FSL_SFP_SNVS_ + +#include <common.h> +#include <config.h> +#include <asm/io.h> + +#ifdef CONFIG_SYS_FSL_SRK_LE +#define srk_in32(a) in_le32(a) +#else +#define srk_in32(a) in_be32(a) +#endif + +#ifdef CONFIG_SYS_FSL_SFP_LE +#define sfp_in32(a) in_le32(a) +#define sfp_out32(a, v) out_le32(a, v) +#define sfp_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_SFP_BE) +#define sfp_in32(a) in_be32(a) +#define sfp_out32(a, v) out_be32(a, v) +#define sfp_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined +#endif + +/* Number of SRKH registers */ +#define NUM_SRKH_REGS 8 + +#ifdef CONFIG_SYS_FSL_SFP_VER_3_2 +struct ccsr_sfp_regs { + u32 ospr; /* 0x200 */ + u32 ospr1; /* 0x204 */ + u32 reserved1[4]; + u32 fswpr; /* 0x218 FSL Section Write Protect */ + u32 fsl_uid; /* 0x21c FSL UID 0 */ + u32 fsl_uid_1; /* 0x220 FSL UID 0 */ + u32 reserved2[12]; + u32 srk_hash[8]; /* 0x254 Super Root Key Hash */ + u32 oem_uid; /* 0x274 OEM UID 0*/ + u32 oem_uid_1; /* 0x278 OEM UID 1*/ + u32 oem_uid_2; /* 0x27c OEM UID 2*/ + u32 oem_uid_3; /* 0x280 OEM UID 3*/ + u32 oem_uid_4; /* 0x284 OEM UID 4*/ + u32 reserved3[8]; +}; +#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0) +struct ccsr_sfp_regs { + u32 ospr; /* 0x200 */ + u32 reserved0[14]; + u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */ + u32 oem_uid; /* 0x9c OEM Unique ID */ + u8 reserved2[0x04]; + u32 ovpr; /* 0xA4 Intent To Secure */ + u8 reserved4[0x08]; + u32 fsl_uid; /* 0xB0 FSL Unique ID */ + u8 reserved5[0x04]; + u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */ + u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */ + +}; +#else +struct ccsr_sfp_regs { + u8 reserved0[0x40]; + u32 ospr; /* 0x40 OEM Security Policy Register */ + u8 reserved2[0x38]; + u32 srk_hash[8]; /* 0x7c Super Root Key Hash */ + u32 oem_uid; /* 0x9c OEM Unique ID */ + u8 reserved4[0x4]; + u32 ovpr; /* 0xA4 OEM Validation Policy Register */ + u8 reserved8[0x8]; + u32 fsl_uid; /* 0xB0 FSL Unique ID */ +}; +#endif +#define ITS_MASK 0x00000004 +#define ITS_BIT 2 +#define OSPR_KEY_REVOC_SHIFT 13 +#define OSPR_KEY_REVOC_MASK 0x0000e000 + +#endif diff --git a/include/fsl_validate.h b/include/fsl_validate.h new file mode 100644 index 0000000000..c4605349a6 --- /dev/null +++ b/include/fsl_validate.h @@ -0,0 +1,199 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_VALIDATE_H_ +#define _FSL_VALIDATE_H_ + +#include <fsl_sec.h> +#include <fsl_sec_mon.h> +#include <command.h> +#include <linux/types.h> + +#define WORD_SIZE 4 + +/* Minimum and maximum size of RSA signature length in bits */ +#define KEY_SIZE 4096 +#define KEY_SIZE_BYTES (KEY_SIZE/8) +#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE)) + +extern struct jobring jr; + +#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define SRK_FLAG 0x01 +#define UNREVOCABLE_KEY 4 +#define ALIGN_REVOC_KEY 3 +#define MAX_KEY_ENTRIES 4 +#endif + +/* Barker code size in bytes */ +#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */ + /* header */ + +/* No-error return values */ +#define ESBC_VALID_HDR 0 /* header is valid */ + +/* Maximum number of SG entries allowed */ +#define MAX_SG_ENTRIES 8 + +/* + * ESBC uboot client header structure. + * The struct contain the following fields + * barker code + * public key offset + * pub key length + * signature offset + * length of the signature + * ptr to SG table + * no of entries in SG table + * esbc ptr + * size of esbc + * esbc entry point + * Scatter gather flag + * UID flag + * FSL UID + * OEM UID + * Here, pub key is modulus concatenated with exponent + * of equal length + */ +struct fsl_secboot_img_hdr { + u8 barker[ESBC_BARKER_LEN]; /* barker code */ + union { + u32 pkey; /* public key offset */ +#ifdef CONFIG_KEY_REVOCATION + u32 srk_tbl_off; +#endif + }; + + union { + u32 key_len; /* pub key length in bytes */ +#ifdef CONFIG_KEY_REVOCATION + struct { + u32 srk_table_flag:8; + u32 srk_sel:8; + u32 num_srk:16; + } len_kr; +#endif + }; + + u32 psign; /* signature offset */ + u32 sign_len; /* length of the signature in bytes */ + union { + struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ + u8 *pimg; /* ptr to ESBC client image */ + }; + union { + u32 sg_entries; /* no of entries in SG table */ + u32 img_size; /* ESBC client image size in bytes */ + }; + ulong img_start; /* ESBC client entry point */ + u32 sg_flag; /* Scatter gather flag */ + u32 uid_flag; + u32 fsl_uid_0; + u32 oem_uid_0; + u32 reserved1[2]; + u32 fsl_uid_1; + u32 oem_uid_1; + u32 reserved2[2]; + u32 ie_flag; + u32 ie_key_sel; +}; + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +struct ie_key_table { + u32 key_len; + u8 pkey[2 * KEY_SIZE_BYTES]; +}; + +struct ie_key_info { + uint32_t key_revok; + uint32_t num_keys; + struct ie_key_table ie_key_tbl[32]; +}; +#endif + +#ifdef CONFIG_KEY_REVOCATION +struct srk_table { + u32 key_len; + u8 pkey[2 * KEY_SIZE_BYTES]; +}; +#endif + +/* + * SG table. + */ +#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) +/* + * This struct contains the following fields + * length of the segment + * source address + */ +struct fsl_secboot_sg_table { + u32 len; /* length of the segment in bytes */ + ulong src_addr; /* ptr to the data segment */ +}; +#else +/* + * This struct contains the following fields + * length of the segment + * Destination Target ID + * source address + * destination address + */ +struct fsl_secboot_sg_table { + u32 len; + u32 trgt_id; + ulong src_addr; + ulong dst_addr; +}; +#endif + +/* + * ESBC private structure. + * Private structure used by ESBC to store following fields + * ESBC client key + * ESBC client key hash + * ESBC client Signature + * Encoded hash recovered from signature + * Encoded hash of ESBC client header plus ESBC client image + */ +struct fsl_secboot_img_priv { + uint32_t hdr_location; + ulong ie_addr; + u32 key_len; + struct fsl_secboot_img_hdr hdr; + + u8 img_key[2 * KEY_SIZE_BYTES]; /* ESBC client key */ + u8 img_key_hash[32]; /* ESBC client key hash */ + +#ifdef CONFIG_KEY_REVOCATION + struct srk_table srk_tbl[MAX_KEY_ENTRIES]; +#endif + u8 img_sign[KEY_SIZE_BYTES]; /* ESBC client signature */ + + u8 img_encoded_hash[KEY_SIZE_BYTES]; /* EM wrt RSA PKCSv1.5 */ + /* Includes hash recovered after + * signature verification + */ + + u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */ + /* Includes hash of + * ESBC client header plus + * ESBC client image + */ + + struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ + u32 ehdrloc; /* ESBC client location */ +}; + +int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]); +int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]); +int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]); + +#endif diff --git a/include/linux/linkage.h b/include/linux/linkage.h index 5797498adc..efb04eeed4 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -11,6 +11,11 @@ #include <asm/linkage.h> +/* Some toolchains use other characters (e.g. '`') to mark new line in macro */ +#ifndef ASM_NL +#define ASM_NL ; +#endif + #ifdef __cplusplus #define CPP_ASMLINKAGE extern "C" #else @@ -43,15 +48,15 @@ #define ALIGN_STR __ALIGN_STR #define LENTRY(name) \ - ALIGN; \ + ALIGN ASM_NL \ SYMBOL_NAME_LABEL(name) #define ENTRY(name) \ - .globl SYMBOL_NAME(name); \ + .globl SYMBOL_NAME(name) ASM_NL \ LENTRY(name) #define WEAK(name) \ - .weak SYMBOL_NAME(name); \ + .weak SYMBOL_NAME(name) ASM_NL \ LENTRY(name) #ifndef END @@ -61,7 +66,7 @@ #ifndef ENDPROC #define ENDPROC(name) \ - .type name STT_FUNC; \ + .type name STT_FUNC ASM_NL \ END(name) #endif diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 297c4cbd99..93cbe36c47 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -73,6 +73,7 @@ enum { #define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 #define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F +#define TPS65217_PWR_OFF 0x80 #define TPS65217_PWR_SRC_USB_BITMASK 0x4 #define TPS65217_PWR_SRC_AC_BITMASK 0x8 diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 24da23fe50..95d6246f59 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -23,7 +23,7 @@ struct stdio_dev { int flags; /* Device flags: input/output/system */ int ext; /* Supported extensions */ - char name[16]; /* Device name */ + char name[32]; /* Device name */ /* GENERAL functions */ |
