diff options
Diffstat (limited to 'include')
46 files changed, 354 insertions, 108 deletions
diff --git a/include/_exports.h b/include/_exports.h index 594470328e..279017e87f 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -23,7 +23,9 @@ EXPORT_FUNC(dummy, void, free_hdlr, void) #endif EXPORT_FUNC(malloc, void *, malloc, size_t) +#ifndef CONFIG_SYS_MALLOC_SIMPLE EXPORT_FUNC(free, void, free, void *) +#endif EXPORT_FUNC(udelay, void, udelay, unsigned long) EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) diff --git a/include/configs/alt.h b/include/configs/alt.h index 58eac31358..e9ffa4866b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -38,8 +38,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF2 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -70,7 +68,6 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -114,4 +111,7 @@ /* SCIF2 */ #define CONFIG_SMSTP7_ENA 0x00080000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __ALT_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09ee10c059..290a6a3e06 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -297,7 +297,6 @@ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 190ef0e71b..3de5079962 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -306,7 +306,6 @@ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 35eae76930..eaed7eaa20 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -16,6 +16,10 @@ #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100MKII +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 2f5a6609b8..848a15832f 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -13,7 +13,7 @@ * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_BALLOON3 1 /* Balloon3 board */ +#define CONFIG_BALLOON3 1 /* Balloon3 board */ /* * Environment settings @@ -84,18 +84,17 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ #define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */ #define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ @@ -135,7 +134,7 @@ #define CONFIG_ENV_IS_IN_FLASH #else #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_SYS_MONITOR_BASE 0x000000 @@ -191,7 +190,6 @@ #define CONFIG_SYS_MDMRS_VAL 0x00220022 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 #define CONFIG_SYS_SXCNFG_VAL 0x00000000 -#define CONFIG_SYS_MEM_BUF_IMP 0x0f /* * PCMCIA and CF Interfaces diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index e9d5d01620..49afe46e2a 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -175,7 +175,6 @@ * * ---------------------------------------------------------------------------- */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index b2a9f35797..9feca1b47b 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -365,7 +365,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 08bd276b44..7fc364e838 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -2,18 +2,22 @@ * Toradex Colibri PXA270 configuration file * * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_H +#define __CONFIG_H /* * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x0 +/* Avoid overwriting factory configuration block */ +#define CONFIG_BOARD_SIZE_LIMIT 0x40000 /* * Environment settings @@ -22,13 +26,13 @@ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ + "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ "fi; " \ "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ "fi; " \ - "bootm 0x80000;" + "bootm 0xc0000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ @@ -50,6 +54,8 @@ */ #include <config_cmd_default.h> +#undef CONFIG_CMD_LOADB /* Both together */ +#undef CONFIG_CMD_LOADS /* saves 10 KB */ #define CONFIG_CMD_NET #define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS @@ -59,7 +65,6 @@ /* * Networking Configuration - * chip on the Voipac PXA270 board */ #ifdef CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -82,7 +87,7 @@ */ #define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_LONGHELP +#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else @@ -96,7 +101,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE 1 - /* * Clock Configuration */ @@ -142,25 +146,24 @@ #else /* No flash */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +/* Skip factory configuration block */ #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) #define CONFIG_ENV_SIZE 0x40000 #define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * GPIO settings */ #define CONFIG_SYS_GPSR0_VAL 0x00000000 #define CONFIG_SYS_GPSR1_VAL 0x00020000 -#define CONFIG_SYS_GPSR2_VAL 0x0002C000 +#define CONFIG_SYS_GPSR2_VAL 0x0002c000 #define CONFIG_SYS_GPSR3_VAL 0x00000000 #define CONFIG_SYS_GPCR0_VAL 0x00000000 @@ -168,19 +171,19 @@ #define CONFIG_SYS_GPCR2_VAL 0x00000000 #define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x08000000 -#define CONFIG_SYS_GPDR1_VAL 0x0002A981 -#define CONFIG_SYS_GPDR2_VAL 0x0202FC00 -#define CONFIG_SYS_GPDR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xc8008000 +#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 +#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff +#define CONFIG_SYS_GPDR3_VAL 0x0061e804 -#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 -#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000300 -#define CONFIG_SYS_GAFR3_U_VAL 0x00024001 +#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 +#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 +#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 #define CONFIG_SYS_PSSR_VAL 0x30 @@ -193,26 +196,26 @@ /* * Memory settings */ -#define CONFIG_SYS_MSC0_VAL 0x000095f2 -#define CONFIG_SYS_MSC1_VAL 0x00007ff4 -#define CONFIG_SYS_MSC2_VAL 0x00000000 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 -#define CONFIG_SYS_MDREFR_VAL 0x2013e01e -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 +#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 +#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 +#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 +#define CONFIG_SYS_MDREFR_VAL 0x2003a031 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 /* * PCMCIA and CF Interfaces */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00028307 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT0_VAL 0x00038787 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO0_VAL 0x0002830f #define CONFIG_SYS_MCIO1_VAL 0x0001430f #include "pxa-common.h" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 1c69551d16..84b047e53f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -213,8 +213,6 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#undef CONFIG_SPL_STACK -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index fe72bd0d3b..b42dab7a7f 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -38,4 +38,20 @@ #define CONFIG_BOARD_REV_GPIO_COUNT 2 +#define CONFIG_PHY_IRAM_BASE 0x02020000 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + +/* + * Low Power settings + */ +#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C + +/* + * Number of CPUs available + */ +#define CONFIG_CORE_COUNT 0x8 + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/flea3.h b/include/configs/flea3.h index bf02829cde..edff0f54cf 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -124,8 +124,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/gose.h b/include/configs/gose.h index 44c8a3053a..0dc28c7ece 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -68,7 +66,6 @@ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 /* I2C */ @@ -101,4 +98,10 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SDHI */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __GOSE_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c14889ce30..1dffab1374 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -68,7 +66,6 @@ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 /* i2c */ @@ -92,7 +89,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE - /* Module stop status bits */ /* INTC-RT */ #define CONFIG_SMSTP0_ENA 0x00400000 @@ -103,4 +99,10 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SD */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __KOELSCH_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 291267f0f0..e830c6df0a 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* SPI */ #define CONFIG_SPI @@ -83,7 +81,6 @@ #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -112,4 +109,7 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __LAGER_H */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index a145f0812f..603d17cef6 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -146,8 +146,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 8b47537614..5ee0abe02a 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -29,6 +29,9 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +/* Reserve the last 1 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -56,8 +59,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */ - #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 9fa86603f6..c395020919 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -25,13 +25,11 @@ #define CONFIG_CMD_MMC -/* - * FIXME: The number of bank is actually 8. But there is no way to reserve the - * last 16 Mib in the last bank now. So I just excluded the last bank - * temporally. - */ -#define CONFIG_NR_DRAM_BANKS 7 +#define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +/* Reserve the last 22 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 8885e17581..e7df15400d 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -259,7 +259,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 9480d8daf2..7dbc9aee3a 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -114,7 +114,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 8abce1b425..75506b22f3 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -116,7 +116,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h index 6490be5504..bd0f44b0d8 100644 --- a/include/configs/palmtreo680.h +++ b/include/configs/palmtreo680.h @@ -117,7 +117,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/porter.h b/include/configs/porter.h new file mode 100644 index 0000000000..9703c840b7 --- /dev/null +++ b/include/configs/porter.h @@ -0,0 +1,112 @@ +/* + * include/configs/porter.h + * This file is Porter board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __PORTER_H +#define __PORTER_H + +#undef DEBUG +#define CONFIG_R8A7791 +#define CONFIG_RMOBILE_BOARD_STRING "Porter" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE + +/* SD */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __PORTER_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index c33f1cb880..e9ef7cc980 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -35,6 +35,8 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* Support File sytems */ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 21e13e5473..c7affd6f3a 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -142,7 +142,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (101 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/silk.h b/include/configs/silk.h index a4235e94d0..161e0a5e26 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF2 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -71,7 +69,6 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -104,6 +101,9 @@ #define CONFIG_SH_MMCIF_ADDR 0xee200000 #define CONFIG_SH_MMCIF_CLK 48000000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + /* Module stop status bits */ /* INTC-RT */ #define CONFIG_SMSTP0_ENA 0x00400000 diff --git a/include/configs/snowball.h b/include/configs/snowball.h index dacb5604cd..126201cf96 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -175,7 +175,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 9fbe68a8a2..38288f69aa 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -237,7 +237,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7d2c0d2fa7..dd69d4ebab 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -346,7 +346,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 005fc6aeb3..fa6ccc16ee 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -43,13 +43,7 @@ /* * NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#else #define CONFIG_TEGRA_SERIAL -#endif #define CONFIG_SYS_NS16550 /* diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index deb6bb2b8f..dcc2bdc7f6 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -171,7 +171,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 87a4efcd5a..27a3dd1366 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -58,7 +58,6 @@ + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ #define CONFIG_CMD_ASKEN @@ -137,7 +136,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40400000 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2bd116477c..c0c1060216 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -213,10 +213,9 @@ * SPLs). We have our BSS be placed 2MiB after this, to allow for the * default Linux kernel address of 0x80008000 to work with most sized * kernels, in the Falcon Mode case. We have the SPL malloc pool at the - * end of the BSS area. We place our stack at 32MiB after the start of - * DRAM to allow room for all of the above. + * end of the BSS area. We suggest that the stack be placed at 32MiB after + * the start of DRAM to allow room for all of the above (handled in Kconfig). */ -#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #endif diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 36621a553c..10ac4a46bc 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -354,7 +354,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 8d7970a376..5302b1fb81 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -131,7 +131,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ #define CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 3f738fb642..df89d14cc3 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -88,6 +88,8 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* Comment out the following to enable L2 cache */ #define CONFIG_UNIPHIER_L2CACHE_ON @@ -186,6 +188,7 @@ /* USB */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 2dea921045..989e755279 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -188,7 +188,6 @@ #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) #define CONFIG_BOOTDELAY 2 diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 2fb91a8f8c..887433b16f 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -221,7 +221,7 @@ #else /* No flash */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif /* @@ -297,7 +297,6 @@ #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 -#define CONFIG_SYS_MEM_BUF_IMP 0x0f /* * PCMCIA and CF Interfaces diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index c7a17f7a49..8e1c7a44cc 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -146,8 +146,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h new file mode 100644 index 0000000000..511ecca0b8 --- /dev/null +++ b/include/configs/xilinx_zynqmp.h @@ -0,0 +1,131 @@ +/* + * Configuration for Xilinx ZynqMP + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * Based on Configuration for Versatile Express + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __XILINX_ZYNQMP_H +#define __XILINX_ZYNQMP_H + +#define CONFIG_REMAKE_ELF + +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_GENERIC_BOARD + +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF9010000 +#define GICC_BASE 0xF9020000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE + +/* Have release address at the end of 256MB for now */ +#define CPU_RELEASE_ADDR 0xFFFFFF0 + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP" + +#define CONFIG_SYS_TEXT_BASE 0x8000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ +#define COUNTER_FREQUENCY 4000000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000) + +/* Serial setup */ +#define CONFIG_ZYNQ_SERIAL_UART0 +#define CONFIG_ZYNQ_SERIAL + +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MEMORY +#define CONFIG_DOS_PARTITION + +#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_MMC +# define CONFIG_GENERIC_MMC +# define CONFIG_SDHCI +# define CONFIG_ZYNQ_SDHCI +# define CONFIG_CMD_MMC +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) +# define CONFIG_FAT_WRITE +# define CONFIG_CMD_EXT4_WRITE +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x8000000 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x80000\0" \ + "fdt_addr=0x7000000\0" \ + "fdt_high=0x10000000\0" \ + "sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \ + "fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" + +#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ + "earlycon=cdns,mmio,0xff000000,${baudrate}n8" +#define CONFIG_PREBOOT "run bootargs" +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOARD_LATE_INIT + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PROMPT "ZynqMP> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 + +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_CLOCKS + +#endif /* __XILINX_ZYNQMP_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index fe331bc082..1dbbc15256 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -136,7 +136,6 @@ unsigned char zipitz2_spi_read(void); /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* diff --git a/include/dfu.h b/include/dfu.h index c27856cb72..7d31abdf33 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -140,6 +140,9 @@ struct dfu_entity { unsigned int inited:1; }; +#ifdef CONFIG_SET_DFU_ALT_INFO +void set_dfu_alt_info(char *interface, char *devstr); +#endif int dfu_config_entities(char *s, char *interface, char *devstr); void dfu_free_entities(void); void dfu_show_entities(void); diff --git a/include/exports.h b/include/exports.h index 205affe72d..1a01e430bb 100644 --- a/include/exports.h +++ b/include/exports.h @@ -15,7 +15,9 @@ int printf(const char* fmt, ...); void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); +#ifndef CONFIG_SYS_MALLOC_SIMPLE void free(void*); +#endif void __udelay(unsigned long); unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); diff --git a/include/fb_mmc.h b/include/fb_mmc.h index 1ad1d1327d..402ba9b1b4 100644 --- a/include/fb_mmc.h +++ b/include/fb_mmc.h @@ -6,3 +6,4 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, unsigned int download_bytes, char *response); +void fb_mmc_erase(const char *cmd, char *response); diff --git a/include/fdtdec.h b/include/fdtdec.h index 1bc70dba21..1233dfb280 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -168,6 +168,7 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */ COMPAT_COUNT, }; diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 607e8d4922..0f957dc367 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -29,9 +29,8 @@ void draw_logo(void); #endif #ifdef CONFIG_SET_DFU_ALT_INFO -char *get_dfu_alt_system(void); -char *get_dfu_alt_boot(void); -void set_dfu_alt_info(void); +char *get_dfu_alt_system(char *interface, char *devstr); +char *get_dfu_alt_boot(char *interface, char *devstr); #endif #ifdef CONFIG_BOARD_TYPES void set_board_type(void); |
