diff options
Diffstat (limited to 'include')
38 files changed, 215 insertions, 178 deletions
diff --git a/include/.gitignore b/include/.gitignore index 03a533ced4..ef7dd5fc8a 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,7 +1,7 @@ /autoconf.mk* /asm -/asm-blackfin/arch -/asm-ppc/arch +/asm-*/arch +/asm-*/proc /bmp_logo.h /config.h /config.mk diff --git a/include/asm-arm/arch-at91sam9/at91_pio.h b/include/asm-arm/arch-at91sam9/at91_pio.h index 84c3866d30..f6ce1f924e 100644 --- a/include/asm-arm/arch-at91sam9/at91_pio.h +++ b/include/asm-arm/arch-at91sam9/at91_pio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91_pio.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People diff --git a/include/asm-arm/arch-at91sam9/at91_pit.h b/include/asm-arm/arch-at91sam9/at91_pit.h index 5026325a5a..94dd242a5f 100644 --- a/include/asm-arm/arch-at91sam9/at91_pit.h +++ b/include/asm-arm/arch-at91sam9/at91_pit.h @@ -1,5 +1,8 @@ /* - * include/asm-arm/arch-at91/at91_pit.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. * * Periodic Interval Timer (PIT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. diff --git a/include/asm-arm/arch-at91sam9/at91_pmc.h b/include/asm-arm/arch-at91sam9/at91_pmc.h index 52cd8e5dab..103be86999 100644 --- a/include/asm-arm/arch-at91sam9/at91_pmc.h +++ b/include/asm-arm/arch-at91sam9/at91_pmc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91_pmc.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h] * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People diff --git a/include/asm-arm/arch-at91sam9/at91_rstc.h b/include/asm-arm/arch-at91sam9/at91_rstc.h index fb8d1618a2..e49caef921 100644 --- a/include/asm-arm/arch-at91sam9/at91_rstc.h +++ b/include/asm-arm/arch-at91sam9/at91_rstc.h @@ -1,5 +1,8 @@ /* - * include/asm-arm/arch-at91/at91_rstc.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. * * Reset Controller (RSTC) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. diff --git a/include/asm-arm/arch-at91sam9/at91_spi.h b/include/asm-arm/arch-at91sam9/at91_spi.h index aaad92621c..30643c6092 100644 --- a/include/asm-arm/arch-at91sam9/at91_spi.h +++ b/include/asm-arm/arch-at91sam9/at91_spi.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91_spi.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h] * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h index e16909c641..d1b33a069a 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91sam9/at91cap9.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91cap9.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] * * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> diff --git a/include/asm-arm/arch-at91sam9/at91cap9_matrix.h b/include/asm-arm/arch-at91sam9/at91cap9_matrix.h index a641686b6c..22b7e9b8f4 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9_matrix.h +++ b/include/asm-arm/arch-at91sam9/at91cap9_matrix.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91cap9_matrix.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h] * * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> diff --git a/include/asm-arm/arch-at91sam9/at91sam9260.h b/include/asm-arm/arch-at91sam9/at91sam9260.h index 1bf45989b5..920a7f3c9f 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9260.h +++ b/include/asm-arm/arch-at91sam9/at91sam9260.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/at91sam9260.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] * * (C) 2006 Andrew Victor * diff --git a/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h index a8e9fec6c7..f8b023d932 100644 --- a/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h +++ b/include/asm-arm/arch-at91sam9/at91sam9260_matrix.h @@ -1,5 +1,7 @@ /* - * include/asm-arm/arch-at91/at91sam9260_matrix.h + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h] + * + * Copyright (C) 2007 Atmel Corporation. * * Memory Controllers (MATRIX, EBI) - System peripherals registers. * Based on AT91SAM9260 datasheet revision B. diff --git a/include/asm-arm/arch-at91sam9/at91sam926x_mc.h b/include/asm-arm/arch-at91sam9/at91sam926x_mc.h deleted file mode 100644 index 041138f809..0000000000 --- a/include/asm-arm/arch-at91sam9/at91sam926x_mc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * include/asm-arm/arch-at91/at91sam926x_mc.h - * - * Memory Controllers (SMC, SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM926x_MC_H -#define AT91SAM926x_MC_H - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - -/* Static Memory Controller (SMC) registers */ -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - -#endif diff --git a/include/asm-arm/arch-at91sam9/at91sam9_smc.h b/include/asm-arm/arch-at91sam9/at91sam9_smc.h new file mode 100644 index 0000000000..d64511b36d --- /dev/null +++ b/include/asm-arm/arch-at91sam9/at91sam9_smc.h @@ -0,0 +1,76 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9_SMC_H +#define AT91SAM9_SMC_H + +#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ +#define AT91_SMC_NWESETUP_(x) ((x) << 0) +#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ +#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) +#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ +#define AT91_SMC_NRDSETUP_(x) ((x) << 16) +#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ +#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) + +#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ +#define AT91_SMC_NWEPULSE_(x) ((x) << 0) +#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ +#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) +#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ +#define AT91_SMC_NRDPULSE_(x) ((x) << 16) +#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ +#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) + +#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ +#define AT91_SMC_NWECYCLE_(x) ((x) << 0) +#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ +#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) + +#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) +#define AT91_SMC_EXNWMODE_READY (3 << 4) +#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ +#define AT91_SMC_BAT_SELECT (0 << 8) +#define AT91_SMC_BAT_WRITE (1 << 8) +#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ +#define AT91_SMC_DBW_8 (0 << 12) +#define AT91_SMC_DBW_16 (1 << 12) +#define AT91_SMC_DBW_32 (2 << 12) +#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ +#define AT91_SMC_TDF_(x) ((x) << 16) +#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ +#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ +#define AT91_SMC_PS (3 << 28) /* Page Size */ +#define AT91_SMC_PS_4 (0 << 28) +#define AT91_SMC_PS_8 (1 << 28) +#define AT91_SMC_PS_16 (2 << 28) +#define AT91_SMC_PS_32 (3 << 28) + +#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ +#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#endif + +#endif diff --git a/include/asm-arm/arch-at91sam9/clk.h b/include/asm-arm/arch-at91sam9/clk.h index 86da9a6e09..f67b4356d9 100644 --- a/include/asm-arm/arch-at91sam9/clk.h +++ b/include/asm-arm/arch-at91sam9/clk.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h index 2500eae2a4..c157e107e1 100644 --- a/include/asm-arm/arch-at91sam9/gpio.h +++ b/include/asm-arm/arch-at91sam9/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/gpio.h + * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] * * Copyright (C) 2005 HP Labs * diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h index 80b334f36e..d2fe45388b 100644 --- a/include/asm-arm/arch-at91sam9/hardware.h +++ b/include/asm-arm/arch-at91sam9/hardware.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/hardware.h + * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] * * Copyright (C) 2003 SAN People * Copyright (C) 2003 ATMEL diff --git a/include/asm-arm/arch-at91sam9/io.h b/include/asm-arm/arch-at91sam9/io.h index be9e9abe56..f09b2df0e3 100644 --- a/include/asm-arm/arch-at91sam9/io.h +++ b/include/asm-arm/arch-at91sam9/io.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-at91/io.h + * [origin: Linux kernel include/asm-arm/arch-at91/io.h] * * Copyright (C) 2003 SAN People * diff --git a/include/asm-arm/arch-at91sam9/memory-map.h b/include/asm-arm/arch-at91sam9/memory-map.h index da98822461..8015dad6a9 100644 --- a/include/asm-arm/arch-at91sam9/memory-map.h +++ b/include/asm-arm/arch-at91sam9/memory-map.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h index f89a401bbc..0552c27ce6 100644 --- a/include/asm-arm/arch-mx31/mx31.h +++ b/include/asm-arm/arch-mx31/mx31.h @@ -24,9 +24,7 @@ #ifndef __ASM_ARCH_MX31_H #define __ASM_ARCH_MX31_H -u32 mx31_get_mpl_dpdgck_clk(void); -u32 mx31_get_mcu_main_clk(void); -u32 mx31_get_ipg_clk(void); -void mx31_gpio_mux(unsigned long mode); +extern u32 mx31_get_ipg_clk(void); +extern void mx31_gpio_mux(unsigned long mode); #endif /* __ASM_ARCH_MX31_H */ diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index 8054f62b06..501ce0e680 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007 - * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 3cd5ad62c0..bbf726dc62 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -59,16 +59,16 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ - #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfe000000 -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_CPLD_BASE 0x80000000 #define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) +#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ @@ -237,6 +237,7 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_NET_MULTI 1 #define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ +#define CONFIG_HAS_ETH0 1 #define CONFIG_NETCONSOLE /* include NetConsole support */ @@ -246,6 +247,9 @@ #undef CONFIG_BOOTARGS +#define xstr(s) str(s) +#define str(s) #s + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=acadia\0" \ @@ -268,8 +272,9 @@ "ramdisk_addr=fff20000\0" \ "initrd_high=30000000\0" \ "load=tftp 200000 acadia/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ @@ -501,4 +506,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index dab21d0c0a..c891fa80ed 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * Configuation settings for the AT91CAP9ADK board. diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 96d1b8dff3..41c418f9ab 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * * Configuation settings for the AT91SAM9260EK board. diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 4ea040bc22..2f0df8ad2d 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -291,6 +291,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_HAS_ETH0 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 @@ -426,4 +427,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 784e7c0f8b..cbd74a0d8d 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -128,6 +128,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -435,4 +436,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 88fd7caa7a..ba68fd4b96 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -201,6 +201,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -306,4 +307,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index d2f6b1021a..cce883fd85 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -79,7 +79,7 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ #define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1) +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ /*----------------------------------------------------------------------- diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index f4cf42c311..57cc90a6de 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -490,7 +490,7 @@ * Some Kilauea stuff..., mainly fpga registers */ #define CFG_FPGA_REG_BASE CFG_FPGA_BASE -#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11)) +#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 10)) /* interrupt */ #define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000 diff --git a/include/configs/luan.h b/include/configs/luan.h index af237d9be0..37151d31fd 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -195,6 +195,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_HAS_ETH0 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ @@ -306,4 +307,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 360e2e11d2..7e0df87019 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -56,9 +56,11 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR #define CONFIG_XILINX_EMAC 1 +#define CFG_ENET #else #ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 +#define CFG_ENET #endif #endif #undef ET_DEBUG @@ -70,18 +72,28 @@ #endif /* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR #define CFG_INTC_0 1 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif /* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) #define CFG_TIMER_0 1 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - +#else +#error BAD CLOCK FREQ +#endif +#endif /* FSL */ /* #define CFG_FSL_2 */ /* #define FSL_INTR_2 1 */ @@ -195,7 +207,12 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL -#define CONFIG_CMD_PING + +#ifndef CFG_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif #if defined(CONFIG_SYSTEMACE) #define CONFIG_CMD_EXT2 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 7614b95019..2ea48a6da9 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -28,7 +28,7 @@ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ #define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ -#define CONFIG_MX31_CLK32 32000 +#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -139,7 +139,7 @@ #define CFG_LOAD_ADDR CONFIG_LOADADDR -#define CFG_HZ 32000 +#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */ #define CONFIG_CMDLINE_EDITING 1 diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 5a6eb4a37d..be2b3ec7ef 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -330,4 +330,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 7db973676b..8a1ff1acba 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -114,6 +114,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0x14 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -433,4 +434,8 @@ unsigned char spi_read(void); #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 851a7ad40a..1879d38522 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -331,4 +331,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index f6e99aca77..adc420b9ad 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -92,6 +92,7 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CONFIG_HAS_ETH0 1 #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* needed for NetConsole */ @@ -346,4 +347,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 30fb303c96..c738567a5f 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -63,9 +63,11 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR #define CONFIG_XILINX_EMAC 1 +#define CFG_ENET #else #ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 +#define CFG_ENET #endif #endif #undef ET_DEBUG @@ -77,18 +79,28 @@ #endif /* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR #define CFG_INTC_0 1 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif /* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) #define CFG_TIMER_0 1 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ #define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - +#else +#error BAD CLOCK FREQ +#endif +#endif /* * memory layout - Example * TEXT_BASE = 0x3600_0000; @@ -162,7 +174,12 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING + +#ifndef CFG_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif #ifdef XILINX_SYSACE_BASEADDR #define CONFIG_CMD_EXT2 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c9323f6074..f22e79824c 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -139,7 +139,6 @@ #define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ #define CFG_SDRAM_BANKS (2) - /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ @@ -227,6 +226,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ @@ -383,4 +383,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 1e3571eb4d..6f9d3e3c6f 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -541,4 +541,8 @@ /*---------------------------------------------------------------------------*/ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/logbuff.h b/include/logbuff.h index d415729053..f117c66e37 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -60,6 +60,7 @@ int drv_logbuff_init (void); void logbuff_init_ptrs (void); void logbuff_log(char *msg); void logbuff_reset (void); +unsigned long logbuffer_base (void); #endif /* CONFIG_LOGBUFFER */ |
