diff options
Diffstat (limited to 'include/configs/pcu_e.h')
| -rw-r--r-- | include/configs/pcu_e.h | 226 |
1 files changed, 113 insertions, 113 deletions
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 664a885fff..921451927b 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -61,7 +61,7 @@ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -75,8 +75,8 @@ #define CONFIG_SPI_X /* 16 bit EEPROM addressing */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* ---------------------------------------------------------------- @@ -87,7 +87,7 @@ * far enough from the start of the data area (as well as from the * stack pointer). * ---------------------------------------------------------------- */ -#define CFG_SPI_INIT_OFFSET 0xB00 +#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 /* @@ -114,60 +114,60 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ +#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ /* Ethernet hardware configuration done using port pins */ -#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */ +#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ +#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ +#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ +#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ +#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ +#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ #else /* XXX */ -#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */ -#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ -#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ -#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ -#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ +#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */ +#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ +#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */ +#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */ +#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */ #endif /* XXX */ /* Ethernet settings: * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex */ -#define CFG_ETH_MDDIS_VALUE 0 -#define CFG_ETH_CFG1_VALUE 1 -#define CFG_ETH_CFG2_VALUE 1 -#define CFG_ETH_CFG3_VALUE 1 +#define CONFIG_SYS_ETH_MDDIS_VALUE 0 +#define CONFIG_SYS_ETH_CFG1_VALUE 1 +#define CONFIG_SYS_ETH_CFG2_VALUE 1 +#define CONFIG_SYS_ETH_CFG3_VALUE 1 /* PUMA configuration */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */ +#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */ #else /* XXX */ -#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */ +#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */ #endif /* XXX */ -#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ +#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ +#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings @@ -177,53 +177,53 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFE000000 +#define CONFIG_SYS_IMMR 0xFE000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Address accessed to reset the board - must not be mapped/assigned */ -#define CFG_RESET_ADDRESS 0xFEFFFFFF +#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* this is an ugly hack needed because of the silly non-constant address map */ -#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) +#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) #if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ #if 0 /* Start port with environment in flash; switch to SPI EEPROM later */ @@ -235,8 +235,8 @@ #else /* Final version: environment in EEPROM */ #define CONFIG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0 -#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_ENV_OFFSET 1024 #define CONFIG_ENV_SIZE 1024 #endif @@ -244,8 +244,8 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 @@ -254,10 +254,10 @@ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -268,21 +268,21 @@ * Asynchronous external master enable. */ /* => 0x70600200 */ -#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) +#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 @@ -291,15 +291,15 @@ * interrupt status bit, set PLL multiplication factor ! */ /* 0x00004080 */ -#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ -#define CFG_PLPRCR \ - ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ +#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ +#define CONFIG_SYS_PLPRCR \ + ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ ) -#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000) +#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -311,7 +311,7 @@ */ #define SCCR_MASK SCCR_EBDF11 /* 0x01800000 */ -#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ +#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ @@ -328,34 +328,34 @@ * Don't expect the "date" command to work without a 32kHz clock input! */ /* 0x00C3 => 0x0003 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) +#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration Register 19-4 *----------------------------------------------------------------------- */ -#define CFG_RCCR 0x0000 +#define CONFIG_SYS_RCCR 0x0000 /*----------------------------------------------------------------------- * RMDS - RISC Microcode Development Support Control Register *----------------------------------------------------------------------- */ -#define CFG_RMDS 0 +#define CONFIG_SYS_RMDS 0 /*----------------------------------------------------------------------- * * Interrupt Levels *----------------------------------------------------------------------- */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ +#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ -#define CFG_DER 0 +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -374,27 +374,27 @@ * used to re-map FLASH: restrict access enough but not too much to * meddle with FLASH accesses */ -#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ +#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ /* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) -#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CONFIG_SYS_OR_TIMING_FLASH) /* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_OR6_REMAP CFG_OR0_REMAP -#define CFG_OR6_PRELIM CFG_OR0_PRELIM -#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM +#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) #else /* XXX */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM +#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) #endif /* XXX */ /* @@ -413,11 +413,11 @@ #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) #else /* XXX */ -#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) #endif /* XXX */ /* @@ -429,11 +429,11 @@ #define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) +#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) #else /* XXX */ -#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) +#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) #endif /* XXX */ /* @@ -461,11 +461,11 @@ #define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR3_PRELIM PUMA_CONF_BR_READ -#define CFG_OR3_PRELIM PUMA_CONF_OR_READ +#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ +#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ #else /* XXX */ -#define CFG_BR4_PRELIM PUMA_CONF_BR_READ -#define CFG_OR4_PRELIM PUMA_CONF_OR_READ +#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ +#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ #endif /* XXX */ /* @@ -477,11 +477,11 @@ #define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) +#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) #else /* XXX */ -#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) +#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) #endif /* XXX */ /* @@ -493,11 +493,11 @@ #define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) +#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) #else /* XXX */ -#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) +#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) #endif /* XXX */ /* @@ -508,15 +508,15 @@ #define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ #define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) -#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) +#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) /* * Memory Periodic Timer Prescaler */ /* periodic timer for refresh */ -#define CFG_MPTPR 0x0200 +#define CONFIG_SYS_MPTPR 0x0200 /* * MAMR settings for SDRAM @@ -525,9 +525,9 @@ * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X */ /* periodic timer for refresh */ -#define CFG_MAMR_PTA 0x30 /* = 48 */ +#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */ -#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ +#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ MAMR_AMA_TYPE_1 | \ MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | \ |
