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-rw-r--r--drivers/block/dwc_ahsata.c17
-rw-r--r--drivers/net/fec_mxc.c42
-rw-r--r--drivers/pci/pci.c4
-rw-r--r--drivers/pci/pcie_imx.c40
-rw-r--r--drivers/serial/serial_lpuart.c19
5 files changed, 107 insertions, 15 deletions
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 15d65d77f3..29f478bfbe 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
return blkcnt;
}
+int sata_port_status(int dev, int port)
+{
+ struct sata_port_regs *port_mmio;
+ struct ahci_probe_ent *probe_ent = NULL;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
+ return -EINVAL;
+
+ if (sata_dev_desc[dev].priv == NULL)
+ return -ENODEV;
+
+ probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+ port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
+
+ return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
+}
+
/*
* SATA interface between low level driver and command layer
*/
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cefda48e4..549d648613 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define FEC_XFER_TIMEOUT 5000
+/*
+ * The standard 32-byte DMA alignment does not work on mx6solox, which requires
+ * 64-byte alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32-bytes)
+ */
+#define FEC_DMA_RX_MINALIGN 64
+
#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif
@@ -711,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
break;
}
- if (!timeout)
+ if (!timeout) {
ret = -EINVAL;
+ goto out;
+ }
- invalidate_dcache_range(addr, addr + size);
- if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+ /*
+ * The TDAR bit is cleared when the descriptors are all out from TX
+ * but on mx6solox we noticed that the READY bit is still not cleared
+ * right after TDAR.
+ * These are two distinct signals, and in IC simulation, we found that
+ * TDAR always gets cleared prior than the READY bit of last BD becomes
+ * cleared.
+ * In mx6solox, we use a later version of FEC IP. It looks like that
+ * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+ * version.
+ *
+ * Fix this by polling the READY bit of BD after the TDAR polling,
+ * which covers the mx6solox case and does not harm the other SoCs.
+ */
+ timeout = FEC_XFER_TIMEOUT;
+ while (--timeout) {
+ invalidate_dcache_range(addr, addr + size);
+ if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+ FEC_TBD_READY))
+ break;
+ }
+
+ if (!timeout)
ret = -EINVAL;
+out:
debug("fec_send: status 0x%x index %d ret %i\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index, ret);
@@ -881,9 +913,9 @@ static int fec_alloc_descs(struct fec_priv *fec)
/* Allocate RX buffers. */
/* Maximum RX buffer size. */
- size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+ size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
for (i = 0; i < FEC_RBD_NUM; i++) {
- data = memalign(ARCH_DMA_MINALIGN, size);
+ data = memalign(FEC_DMA_RX_MINALIGN, size);
if (!data) {
printf("%s: error allocating rxbuf %d\n", __func__, i);
goto err_ring;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4fd9c532b3..28859f3161 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -648,6 +648,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+#ifdef CONFIG_PCI_FIXUP_DEV
+ board_pci_fixup_dev(hose, dev, vendor, device, class);
+#endif
+
#ifdef CONFIG_PCI_SCAN_SHOW
indent++;
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index a3982c4553..fd7e4d499f 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -23,13 +23,20 @@
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR 0x08ffc000
+#define MX6_IO_ADDR 0x08000000
+#define MX6_MEM_ADDR 0x08100000
+#define MX6_ROOT_ADDR 0x08f00000
+#else
#define MX6_DBI_ADDR 0x01ffc000
-#define MX6_DBI_SIZE 0x4000
#define MX6_IO_ADDR 0x01000000
-#define MX6_IO_SIZE 0x100000
#define MX6_MEM_ADDR 0x01100000
-#define MX6_MEM_SIZE 0xe00000
#define MX6_ROOT_ADDR 0x01f00000
+#endif
+#define MX6_DBI_SIZE 0x4000
+#define MX6_IO_SIZE 0x100000
+#define MX6_MEM_SIZE 0xe00000
#define MX6_ROOT_SIZE 0xfc000
/* PCIe Port Logic registers (memory-mapped) */
@@ -57,6 +64,8 @@
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+#define PCIE_PHY_PUP_REQ (1 << 7)
+
/* iATU registers */
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
static int imx6_pcie_assert_core_reset(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
+#if defined(CONFIG_MX6SX)
+ struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+ /* SSP_EN is not used on MX6SX anymore */
+ setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+ /* Force PCIe PHY reset */
+ setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+ /* Power up PCIe PHY */
+ setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
return 0;
}
@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
IOMUXC_GPR12_LOS_LEVEL_MASK,
IOMUXC_GPR12_LOS_LEVEL_9);
+#ifdef CONFIG_MX6SX
+ clrsetbits_le32(&iomuxc_regs->gpr[12],
+ IOMUXC_GPR12_RX_EQ_MASK,
+ IOMUXC_GPR12_RX_EQ_2);
+#endif
+
writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
(0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
(20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
*/
mdelay(50);
+#if defined(CONFIG_MX6SX)
+ /* SSP_EN is not used on MX6SX anymore */
+ clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+ /* Clear PCIe PHY reset bit */
+ clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
/* Enable PCIe */
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
imx6_pcie_toggle_reset();
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index b0c6f6f4ab..63fc388b26 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -14,8 +14,13 @@
#define US1_TDRE (1 << 7)
#define US1_RDRF (1 << 5)
+#define US1_OR (1 << 3)
#define UC2_TE (1 << 3)
#define UC2_RE (1 << 2)
+#define CFIFO_TXFLUSH (1 << 7)
+#define CFIFO_RXFLUSH (1 << 6)
+#define SFIFO_RXOF (1 << 2)
+#define SFIFO_RXUF (1 << 0)
#define STAT_LBKDIF (1 << 31)
#define STAT_RXEDGIF (1 << 30)
@@ -62,14 +67,10 @@ static void lpuart_serial_setbrg(void)
static int lpuart_serial_getc(void)
{
- u8 status;
-
- while (!(__raw_readb(&base->us1) & US1_RDRF))
+ while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
WATCHDOG_RESET();
- status = __raw_readb(&base->us1);
- status |= US1_RDRF;
- __raw_writeb(status, &base->us1);
+ barrier();
return __raw_readb(&base->ud);
}
@@ -112,6 +113,12 @@ static int lpuart_serial_init(void)
__raw_writeb(0, &base->umodem);
__raw_writeb(0, &base->uc1);
+ /* Disable FIFO and flush buffer */
+ __raw_writeb(0x0, &base->upfifo);
+ __raw_writeb(0x0, &base->utwfifo);
+ __raw_writeb(0x1, &base->urwfifo);
+ __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
+
/* provide data bits, parity, stop bit, etc */
serial_setbrg();
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