diff options
Diffstat (limited to 'drivers')
52 files changed, 2470 insertions, 549 deletions
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 51b10263b8..a93810934a 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -131,6 +131,10 @@ int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; + ret = dfu_write_buffer_drain(dfu); + if (ret) + return ret; + if (dfu->flush_medium) ret = dfu->flush_medium(dfu); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5e10ea7e66..63cc876612 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -18,11 +18,29 @@ static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; static long dfu_file_buf_len; +static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) +{ + int ret; + + if (part == mmc->part_num) + return 0; + + ret = mmc_switch_part(dfu->dev_num, part); + if (ret) { + error("Cannot switch to partition %d\n", part); + return ret; + } + mmc->part_num = part; + + return 0; +} + static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { struct mmc *mmc = find_mmc_device(dfu->dev_num); u32 blk_start, blk_count, n = 0; + int ret, part_num_bkp = 0; /* * We must ensure that we work in lba_blk_size chunks, so ALIGN @@ -39,6 +57,13 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EINVAL; } + if (dfu->data.mmc.hw_partition >= 0) { + part_num_bkp = mmc->part_num; + ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition); + if (ret) + return ret; + } + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num, blk_start, blk_count, buf); @@ -57,9 +82,17 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, if (n != blk_count) { error("MMC operation failed"); + if (dfu->data.mmc.hw_partition >= 0) + mmc_access_part(dfu, mmc, part_num_bkp); return -EIO; } + if (dfu->data.mmc.hw_partition >= 0) { + ret = mmc_access_part(dfu, mmc, part_num_bkp); + if (ret) + return ret; + } + return 0; } @@ -194,6 +227,8 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, * 2nd and 3rd: * lba_start and lba_size, for raw write * mmc_dev and mmc_part, for filesystems and part + * 4th (optional): + * mmcpart <num> (access to HW eMMC partitions) */ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) { @@ -233,11 +268,22 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) return -ENODEV; } + dfu->data.mmc.hw_partition = -EINVAL; if (!strcmp(entity_type, "raw")) { dfu->layout = DFU_RAW_ADDR; dfu->data.mmc.lba_start = second_arg; dfu->data.mmc.lba_size = third_arg; dfu->data.mmc.lba_blk_size = mmc->read_bl_len; + + /* + * Check for an extra entry at dfu_alt_info env variable + * specifying the mmc HW defined partition number + */ + if (s) + if (!strcmp(strsep(&s, " "), "mmcpart")) + dfu->data.mmc.hw_partition = + simple_strtoul(s, NULL, 0); + } else if (!strcmp(entity_type, "part")) { disk_partition_t partinfo; block_dev_desc_t *blk_dev = &mmc->block_dev; diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 2d07097e85..ccdbef6b75 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -163,6 +163,18 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) return ret; } +unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu) +{ + /* + * Currently, Poll Timeout != 0 is only needed on nand + * ubi partition, as the not used sectors need an erase + */ + if (dfu->data.nand.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +} + int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) { char *st; @@ -211,6 +223,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) dfu->read_medium = dfu_read_medium_nand; dfu->write_medium = dfu_write_medium_nand; dfu->flush_medium = dfu_flush_medium_nand; + dfu->poll_timeout = dfu_polltimeout_nand; /* initial state */ dfu->inited = 0; diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index b940d9b316..37946d5e18 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc) /* * Convert bitstream data and load into the fpga */ -int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { printf("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loadfs(desc->devdesc, buf, size, + fpga_fsinfo); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ -int fpga_load(int devnum, const void *buf, size_t bsize) +int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume failure */ const fpga_desc *desc = fpga_validate(devnum, buf, bsize, @@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize) switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load(desc->devdesc, buf, bsize); + ret_val = xilinx_load(desc->devdesc, buf, bsize, + bstype); #else fpga_no_sup((char *)__func__, "Xilinx devices"); #endif diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eab1b51e5..859fb3c778 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,29 +31,30 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(xilinx_desc *desc ); */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan2_ss_load (desc, buf, bsize); + ret_val = spartan2_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan2_sp_load (desc, buf, bsize); + ret_val = spartan2_sp_load(desc, buf, bsize); break; default: @@ -64,19 +65,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan2_ss_dump (desc, buf, bsize); + ret_val = spartan2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan2_sp_dump (desc, buf, bsize); + ret_val = spartan2_sp_dump(desc, buf, bsize); break; default: @@ -87,7 +88,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_info( Xilinx_desc *desc ) +static int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,10 +97,10 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -248,10 +249,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -296,10 +297,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -439,7 +440,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ @@ -447,3 +448,9 @@ static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan2_op = { + .load = spartan2_load, + .dump = spartan2_dump, + .info = spartan2_info, +}; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 3edc5c2c66..b0213e6999 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,29 +35,30 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(xilinx_desc *desc ); */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan3_ss_load (desc, buf, bsize); + ret_val = spartan3_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan3_sp_load (desc, buf, bsize); + ret_val = spartan3_sp_load(desc, buf, bsize); break; default: @@ -68,19 +69,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan3_ss_dump (desc, buf, bsize); + ret_val = spartan3_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan3_sp_dump (desc, buf, bsize); + ret_val = spartan3_sp_dump(desc, buf, bsize); break; default: @@ -91,7 +92,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_info( Xilinx_desc *desc ) +static int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,10 +101,10 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -254,10 +255,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -302,10 +303,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -457,7 +458,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ @@ -465,3 +466,9 @@ static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan3_op = { + .load = spartan3_load, + .dump = spartan3_dump, + .info = spartan3_info, +}; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b5a895d41a..0d2d9a4693 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,25 +84,26 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Virtex2_ss_load (desc, buf, bsize); + ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Virtex2_ssm_load (desc, buf, bsize); + ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: @@ -112,19 +113,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Virtex2_ss_dump (desc, buf, bsize); + ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Virtex2_ssm_dump (desc, buf, bsize); + ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: @@ -134,7 +135,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_info (Xilinx_desc * desc) +static int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,10 +154,10 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", __FUNCTION__, __LINE__, fn); @@ -352,10 +353,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -404,16 +405,22 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; } /* vim: set ts=4 tw=78: */ + +struct xilinx_fpga_op virtex2_op = { + .load = virtex2_load, + .dump = virtex2_dump, + .info = virtex2_info, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 2e0db535d4..3795c1aff6 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -19,23 +19,13 @@ #include <spartan3.h> #include <zynqpl.h> -#if 0 -#define FPGA_DEBUG -#endif - -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local Static Functions */ -static int xilinx_validate (Xilinx_desc * desc, char *fn); +static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ -int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { unsigned int length; unsigned int swapsize; @@ -43,7 +33,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; const fpga_desc *desc; - Xilinx_desc *xdesc; + xilinx_desc *xdesc; dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ @@ -94,7 +84,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return FPGA_FAIL; } } else { - printf("%s: Please fill correct device ID to Xilinx_desc\n", + printf("%s: Please fill correct device ID to xilinx_desc\n", __func__); } printf(" part number = \"%s\"\n", buffer); @@ -138,137 +128,60 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - return fpga_load(devnum, dataptr, swapsize); + return fpga_load(devnum, dataptr, swapsize, bstype); } -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Loader...\n", - __FUNCTION__); - ret_val = Spartan2_load (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Loader...\n", - __FUNCTION__); - ret_val = Spartan3_load (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Loader...\n", - __FUNCTION__); - ret_val = Virtex2_load (desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Loader...\n", - __func__); - ret_val = zynq_load(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->load(desc, buf, bsize, bstype); } -int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +#if defined(CONFIG_CMD_FPGA_LOADFS) +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo) { - int ret_val = FPGA_FAIL; /* assume a failure */ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Reader...\n", - __FUNCTION__); - ret_val = Spartan2_dump (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Reader...\n", - __FUNCTION__); - ret_val = Spartan3_dump (desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Reader...\n", - __FUNCTION__); - ret_val = Virtex2_dump (desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Reader...\n", - __func__); - ret_val = zynq_dump(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); + if (!desc->operations->loadfs) + return FPGA_FAIL; + + return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); +} #endif - break; - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) +{ + if (!xilinx_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + return FPGA_FAIL; + } - return ret_val; + return desc->operations->dump(desc, buf, bsize); } -int xilinx_info (Xilinx_desc * desc) +int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; if (xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: printf ("Spartan-II\n"); break; - case Xilinx_Spartan3: + case xilinx_spartan3: printf ("Spartan-III\n"); break; - case Xilinx_Virtex2: + case xilinx_virtex2: printf ("Virtex-II\n"); break; case xilinx_zynq: @@ -315,47 +228,7 @@ int xilinx_info (Xilinx_desc * desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - Spartan2_info (desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - Spartan3_info (desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - Virtex2_info (desc); -#else - /* just in case */ - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - zynq_info(desc); -#else - /* just in case */ - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - ; - } + desc->operations->info(desc); } else printf ("No Device Function Table.\n"); @@ -369,7 +242,7 @@ int xilinx_info (Xilinx_desc * desc) /* ------------------------------------------------------------------------- */ -static int xilinx_validate (Xilinx_desc * desc, char *fn) +static int xilinx_validate(xilinx_desc *desc, char *fn) { int ret_val = false; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 923a1586d8..68fe0f3b03 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> +#include <fs.h> #include <zynqpl.h> #include <linux/sizes.h> #include <asm/arch/hardware.h> @@ -36,7 +37,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(Xilinx_desc *desc) +static int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -147,81 +148,62 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } - -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 i, control, isr_status, status, swap, diff; - u32 *buf_start; + unsigned long ts; + u32 isr_status; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; - } - - buf_start = check_data((u8 *)buf, bsize, &swap); - if (!buf_start) - return FPGA_FAIL; - - /* Check if data is postpone from start */ - diff = (u32)buf_start - (u32)buf; - if (diff) { - printf("%s: Bitstream is not validated yet (diff %x)\n", - __func__, diff); - return FPGA_FAIL; - } + /* Set up the transfer */ + writel((u32)srcbuf, &devcfg_base->dma_src_addr); + writel(dstbuf, &devcfg_base->dma_dst_addr); + writel(srclen, &devcfg_base->dma_src_len); + writel(dstlen, &devcfg_base->dma_dst_len); - if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); - return FPGA_FAIL; - } + isr_status = readl(&devcfg_base->int_sts); - if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { - u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { + if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { + debug("%s: Error: isr = 0x%08X\n", __func__, + isr_status); + debug("%s: Write count = 0x%08X\n", __func__, + readl(&devcfg_base->write_count)); + debug("%s: Read count = 0x%08X\n", __func__, + readl(&devcfg_base->read_count)); - /* - * This might be dangerous but permits to flash if - * ARCH_DMA_MINALIGN is greater than header size - */ - if (new_buf > buf_start) { - debug("%s: Aligned buffer is after buffer start\n", - __func__); - new_buf -= ARCH_DMA_MINALIGN; + return FPGA_FAIL; } + if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { + printf("%s: Timeout wait for DMA to complete\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } - printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, - (u32)buf_start, (u32)new_buf, swap); - - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); - - swap = SWAP_DONE; - buf = new_buf; - } else if (swap != SWAP_DONE) { - /* For bitstream which are aligned */ - u32 *new_buf = (u32 *)buf; + debug("%s: DMA transfer is done\n", __func__); - printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, - swap); + /* Clear out the DMA status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); + return FPGA_SUCCESS; +} - swap = SWAP_DONE; - } +static int zynq_dma_xfer_init(bitstream_type bstype) +{ + u32 status, control, isr_status; + unsigned long ts; /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -298,6 +280,95 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); } + return FPGA_SUCCESS; +} + +static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) +{ + u32 *new_buf; + u32 i; + + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, + (u32)buf, (u32)new_buf, swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + + buf = new_buf; + } else if (swap != SWAP_DONE) { + /* For bitstream which are aligned */ + u32 *new_buf = (u32 *)buf; + + printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, + swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + } + + return buf; +} + +static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, + size_t bsize, u32 blocksize, u32 *swap, + bitstream_type *bstype) +{ + u32 *buf_start; + u32 diff; + + buf_start = check_data((u8 *)buf, blocksize, swap); + + if (!buf_start) + return FPGA_FAIL; + + /* Check if data is postpone from start */ + diff = (u32)buf_start - (u32)buf; + if (diff) { + printf("%s: Bitstream is not validated yet (diff %x)\n", + __func__, diff); + return FPGA_FAIL; + } + + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + + if (zynq_dma_xfer_init(*bstype)) + return FPGA_FAIL; + + return 0; +} + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + + /* + * send bsize inplace of blocksize as it was not a bitstream + * in chunks + */ + if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, + &bstype)) + return FPGA_FAIL; + + buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); + debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); @@ -305,36 +376,89 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) flush_dcache_range((u32)buf, (u32)buf + roundup(bsize, ARCH_DMA_MINALIGN)); - /* Set up the transfer */ - writel((u32)buf | 1, &devcfg_base->dma_src_addr); - writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); - writel(bsize >> 2, &devcfg_base->dma_src_len); - writel(0, &devcfg_base->dma_dst_len); + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; isr_status = readl(&devcfg_base->int_sts); - - /* Polling the PCAP_INIT status for Set */ + /* Check FPGA configuration completion */ ts = get_timer(0); - while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { - if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { - debug("%s: Error: isr = 0x%08X\n", __func__, - isr_status); - debug("%s: Write count = 0x%08X\n", __func__, - readl(&devcfg_base->write_count)); - debug("%s: Read count = 0x%08X\n", __func__, - readl(&devcfg_base->read_count)); - - return FPGA_FAIL; - } - if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { - printf("%s: Timeout wait for DMA to complete\n", + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; } isr_status = readl(&devcfg_base->int_sts); } - debug("%s: DMA transfer is done\n", __func__); + debug("%s: FPGA config done\n", __func__); + + if (bstype != BIT_PARTIAL) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} + +#if defined(CONFIG_CMD_FPGA_LOADFS) +static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fsinfo) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + u32 partialbit = 0; + u32 blocksize; + u32 pos = 0; + int fstype; + char *interface, *dev_part, *filename; + + blocksize = fsinfo->blocksize; + interface = fsinfo->interface; + dev_part = fsinfo->dev_part; + filename = fsinfo->filename; + fstype = fsinfo->fstype; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, + &partialbit)) + return FPGA_FAIL; + + dcache_disable(); + + do { + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, + 0xffffffff, 0)) + return FPGA_FAIL; + + bsize -= blocksize; + pos += blocksize; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (bsize > blocksize) { + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + } else { + if (fs_read(filename, (u32) buf, pos, bsize) < 0) + return FPGA_FAIL; + } + } while (bsize > blocksize); + + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; + + dcache_enable(); + + isr_status = readl(&devcfg_base->int_sts); /* Check FPGA configuration completion */ ts = get_timer(0); @@ -349,16 +473,23 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); - /* Clear out the DMA status */ - writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - if (!partialbit) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; } +#endif -int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } + +struct xilinx_fpga_op zynq_op = { + .load = zynq_load, +#if defined(CONFIG_CMD_FPGA_LOADFS) + .loadfs = zynq_loadfs, +#endif + .dump = zynq_dump, + .info = zynq_info, +}; diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 0b70071871..6517af1628 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -34,6 +34,7 @@ static struct at91_port *at91_pio_get_port(unsigned port) #endif #endif default: + printf("Error: at91_gpio: Fail to get PIO base!\n"); return NULL; } } @@ -200,7 +201,7 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &at91_port->idr); writel(mask, &at91_port->pudr); diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 90c8387918..5ba0e03862 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -216,21 +216,7 @@ static int twsi_stop(int status) */ #define TWSI_FREQUENCY(m, n) \ - ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) - -/* - * These are required to be reprogrammed before enabling the controller - * because a reset loses them. - * Default values come from the spec, but a twsi_reset will change them. - * twsi_slave_address left uninitialized lest checkpatch.pl complains. - */ - -/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ -static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default frequency corresponding to default m=4, n=4 */ -static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); -/* Default slave address is 0 (so is an uninitialized static) */ -static u8 twsi_slave_address; + (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) /* * Reset controller. @@ -238,7 +224,7 @@ static u8 twsi_slave_address; * Controller reset also resets the baud rate and slave address, so * re-establish them. */ -static void twsi_reset(void) +static void twsi_reset(u8 baud_rate, u8 slave_address) { /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; @@ -247,9 +233,9 @@ static void twsi_reset(void) /* wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); /* set baud rate */ - writel(twsi_baud_rate, &twsi->baudrate); + writel(baud_rate, &twsi->baudrate); /* set slave address even though we don't use it */ - writel(twsi_slave_address, &twsi->slave_address); + writel(slave_address, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); /* assert STOP but don't care for the result */ (void) twsi_stop(0); @@ -277,12 +263,8 @@ void i2c_init(int requested_speed, int slaveadd) } } } - /* save baud rate and slave for later calls to twsi_reset */ - twsi_baud_rate = baud; - twsi_actual_speed = highest_speed; - twsi_slave_address = slaveadd; /* reset controller */ - twsi_reset(); + twsi_reset(baud, slaveadd); } /* diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index f1f65131a2..b3264af452 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -142,7 +142,7 @@ static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c)); + zynq_i2c_debug_status(zynq_i2c); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -235,7 +235,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif return 0; } diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 931922bc4a..34febf52f0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,8 +28,10 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4c3b93d413..55416136ab 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -174,7 +174,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; -#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO + uint wml_value; wml_value = data->blocksize/4; @@ -184,12 +184,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = WML_RD_WML_MAX_VAL; esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->dest); +#endif } else { +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO flush_dcache_range((ulong)data->src, (ulong)data->src+data->blocks *data->blocksize); - +#endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { @@ -199,19 +202,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->src); +#endif } -#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ - if (!(data->flags & MMC_DATA_READ)) { - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. " - "Can not write to a locked card.\n\n"); - return TIMEOUT; - } - esdhc_write32(®s->dsaddr, (u32)data->src); - } else - esdhc_write32(®s->dsaddr, (u32)data->dest); -#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); @@ -252,6 +246,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) return 0; } +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO static void check_and_invalidate_dcache_range (struct mmc_cmd *cmd, struct mmc_data *data) { @@ -261,6 +256,8 @@ static void check_and_invalidate_dcache_range unsigned end = start+size ; invalidate_dcache_range(start, end); } +#endif + /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@ -388,9 +385,10 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) goto out; } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); -#endif + if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); +#endif } out: diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index acca0269e5..a57a9b1faf 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -243,9 +243,10 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef DEBUG if (data->flags & MMC_DATA_READ) { + u32 cnt = word_count * 4; printf("Read Data:\n"); - print_buffer(0, data->dest, 1, - word_count*4, 0); + print_buffer(0, data->dest + cnt * block_count, + 1, cnt, 0); } #endif #ifdef DEBUG diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 08187d5f3e..55c2c68cdb 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -150,6 +150,8 @@ int mmc_send_status(struct mmc *mmc, int timeout) #endif return TIMEOUT; } + if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) + return SWITCH_ERR; return 0; } @@ -504,7 +506,7 @@ static int mmc_change_freq(struct mmc *mmc) err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); if (err) - return err; + return err == SWITCH_ERR ? 0 : err; /* Now check to see that it worked */ err = mmc_send_ext_csd(mmc, ext_csd); @@ -556,6 +558,32 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } +int mmc_select_hwpart(int dev_num, int hwpart) +{ + struct mmc *mmc = find_mmc_device(dev_num); + int ret; + + if (!mmc) + return -1; + + if (mmc->part_num == hwpart) + return 0; + + if (mmc->part_config == MMCPART_NOAVAILABLE) { + printf("Card doesn't support part_switch\n"); + return -1; + } + + ret = mmc_switch_part(dev_num, hwpart); + if (ret) + return -1; + + mmc->part_num = hwpart; + + return 0; +} + + int mmc_switch_part(int dev_num, unsigned int part_num) { struct mmc *mmc = find_mmc_device(dev_num); @@ -1320,10 +1348,13 @@ static int mmc_complete_init(struct mmc *mmc) int mmc_init(struct mmc *mmc) { int err = IN_PROGRESS; - unsigned start = get_timer(0); + unsigned start; if (mmc->has_init) return 0; + + start = get_timer(0); + if (!mmc->init_in_progress) err = mmc_start_init(mmc); diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c new file mode 100644 index 0000000000..05936f5d1f --- /dev/null +++ b/drivers/mmc/rpmb.c @@ -0,0 +1,323 @@ +/* + * Copyright 2014, Staubli Faverges + * Pierre Aubert + * + * eMMC- Replay Protected Memory Block + * According to JEDEC Standard No. 84-A441 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <mmc.h> +#include <sha256.h> +#include "mmc_private.h" + +/* Request codes */ +#define RPMB_REQ_KEY 1 +#define RPMB_REQ_WCOUNTER 2 +#define RPMB_REQ_WRITE_DATA 3 +#define RPMB_REQ_READ_DATA 4 +#define RPMB_REQ_STATUS 5 + +/* Response code */ +#define RPMB_RESP_KEY 0x0100 +#define RPMB_RESP_WCOUNTER 0x0200 +#define RPMB_RESP_WRITE_DATA 0x0300 +#define RPMB_RESP_READ_DATA 0x0400 + +/* Error codes */ +#define RPMB_OK 0 +#define RPMB_ERR_GENERAL 1 +#define RPMB_ERR_AUTH 2 +#define RPMB_ERR_COUNTER 3 +#define RPMB_ERR_ADDRESS 4 +#define RPMB_ERR_WRITE 5 +#define RPMB_ERR_READ 6 +#define RPMB_ERR_KEY 7 +#define RPMB_ERR_CNT_EXPIRED 0x80 +#define RPMB_ERR_MSK 0x7 + +/* Sizes of RPMB data frame */ +#define RPMB_SZ_STUFF 196 +#define RPMB_SZ_MAC 32 +#define RPMB_SZ_DATA 256 +#define RPMB_SZ_NONCE 16 + +#define SHA256_BLOCK_SIZE 64 + +/* Error messages */ +static const char * const rpmb_err_msg[] = { + "", + "General failure", + "Authentication failure", + "Counter failure", + "Address failure", + "Write failure", + "Read failure", + "Authentication key not yet programmed", +}; + + +/* Structure of RPMB data frame. */ +struct s_rpmb { + unsigned char stuff[RPMB_SZ_STUFF]; + unsigned char mac[RPMB_SZ_MAC]; + unsigned char data[RPMB_SZ_DATA]; + unsigned char nonce[RPMB_SZ_NONCE]; + unsigned long write_counter; + unsigned short address; + unsigned short block_count; + unsigned short result; + unsigned short request; +}; + +static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, + bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + + cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT; + cmd.cmdarg = blockcount & 0x0000FFFF; + if (is_rel_write) + cmd.cmdarg |= 1 << 31; + cmd.resp_type = MMC_RSP_R1; + + return mmc_send_cmd(mmc, &cmd, NULL); +} +static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, + unsigned int count, bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, count, is_rel_write); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return 1; + } + + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + + data.src = (const char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_WRITE; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return 1; + } + return 0; +} +static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned short expected) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, 1, false); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return -1; + } + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1; + + data.dest = (char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_READ; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return -1; + } + /* Check the response and the status */ + if (be16_to_cpu(s->request) != expected) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:response= %x\n", __func__, + be16_to_cpu(s->request)); +#endif + return -1; + } + ret = be16_to_cpu(s->result); + if (ret) { + printf("%s %s\n", rpmb_err_msg[ret & RPMB_ERR_MSK], + (ret & RPMB_ERR_CNT_EXPIRED) ? + "Write counter has expired" : ""); + } + + /* Return the status of the command */ + return ret; +} +static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_STATUS); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + return mmc_rpmb_response(mmc, rpmb_frame, expected); +} +static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len, + unsigned char *output) +{ + sha256_context ctx; + int i; + unsigned char k_ipad[SHA256_BLOCK_SIZE]; + unsigned char k_opad[SHA256_BLOCK_SIZE]; + + sha256_starts(&ctx); + + /* According to RFC 4634, the HMAC transform looks like: + SHA(K XOR opad, SHA(K XOR ipad, text)) + + where K is an n byte key. + ipad is the byte 0x36 repeated blocksize times + opad is the byte 0x5c repeated blocksize times + and text is the data being protected. + */ + + for (i = 0; i < RPMB_SZ_MAC; i++) { + k_ipad[i] = key[i] ^ 0x36; + k_opad[i] = key[i] ^ 0x5c; + } + /* remaining pad bytes are '\0' XOR'd with ipad and opad values */ + for ( ; i < SHA256_BLOCK_SIZE; i++) { + k_ipad[i] = 0x36; + k_opad[i] = 0x5c; + } + sha256_update(&ctx, k_ipad, SHA256_BLOCK_SIZE); + sha256_update(&ctx, buff, len); + sha256_finish(&ctx, output); + + /* Init context for second pass */ + sha256_starts(&ctx); + + /* start with outer pad */ + sha256_update(&ctx, k_opad, SHA256_BLOCK_SIZE); + + /* then results of 1st hash */ + sha256_update(&ctx, output, RPMB_SZ_MAC); + + /* finish up 2nd pass */ + sha256_finish(&ctx, output); +} +int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter) +{ + int ret; + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WCOUNTER); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER); + if (ret) + return ret; + + *pcounter = be32_to_cpu(rpmb_frame->write_counter); + return 0; +} +int mmc_rpmb_set_key(struct mmc *mmc, void *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_KEY); + memcpy(rpmb_frame->mac, key, RPMB_SZ_MAC); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + return -1; + + /* read the operation status */ + return mmc_rpmb_status(mmc, RPMB_RESP_KEY); +} +int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + int i; + + for (i = 0; i < cnt; i++) { + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_READ_DATA); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + break; + + /* Read the result */ + if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA)) + break; + + /* Check the HMAC if key is provided */ + if (key) { + unsigned char ret_hmac[RPMB_SZ_MAC]; + + rpmb_hmac(key, rpmb_frame->data, 284, ret_hmac); + if (memcmp(ret_hmac, rpmb_frame->mac, RPMB_SZ_MAC)) { + printf("MAC error on block #%d\n", i); + break; + } + } + /* Copy data */ + memcpy(addr + i * RPMB_SZ_DATA, rpmb_frame->data, RPMB_SZ_DATA); + } + return i; +} +int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + unsigned long wcount; + int i; + + for (i = 0; i < cnt; i++) { + if (mmc_rpmb_get_counter(mmc, &wcount)) { + printf("Cannot read RPMB write counter\n"); + break; + } + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + memcpy(rpmb_frame->data, addr + i * RPMB_SZ_DATA, RPMB_SZ_DATA); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->block_count = cpu_to_be16(1); + rpmb_frame->write_counter = cpu_to_be32(wcount); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WRITE_DATA); + /* Computes HMAC */ + rpmb_hmac(key, rpmb_frame->data, 284, rpmb_frame->mac); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + break; + + /* Get status */ + if (mmc_rpmb_status(mmc, RPMB_RESP_WRITE_DATA)) + break; + } + return i; +} diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 0000000000..eb7b1158d6 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,503 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron <leafy.myeh@allwinnertech.com> + * + * MMC driver for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mmc.h> + +struct sunxi_mmc_des { + u32 reserved1_1:1; + u32 dic:1; /* disable interrupt on completion */ + u32 last_des:1; /* 1-this data buffer is the last buffer */ + u32 first_des:1; /* 1-data buffer is the first buffer, + 0-data buffer contained in the next + descriptor is 1st buffer */ + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the + next descriptor address */ + u32 end_of_ring:1; /* 1-last descriptor flag when using dual + data buffer in descriptor */ + u32 reserved1_2:24; + u32 card_err_sum:1; /* transfer error flag */ + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ +#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:16; + u32 data_buf2_sz:16; + u32 buf_addr_ptr1; + u32 buf_addr_ptr2; +}; + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned database; + unsigned fatal_err; + unsigned mod_clk; + struct sunxi_mmc *reg; + struct mmc_config cfg; +}; + +/* support 4 mmc hosts */ +struct sunxi_mmc_host mmc_host[4]; + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->database = (unsigned int)mmchost->reg + 0x100; + mmchost->mmc_no = sdc_no; + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + unsigned int pll_clk; + unsigned int divider; + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d clock and io\n", sdc_no); + + /* config ahb clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); + + /* config mod clock */ + pll_clk = clock_get_pll6(); + /* should be close to 100 MHz but no more, so round up */ + divider = ((pll_clk + 99999999) / 100000000) - 1; + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider, + mmchost->mclkreg); + mmchost->mod_clk = pll_clk / (divider + 1); + + return 0; +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmd; + unsigned timeout_msecs = 2000; + + cmd = SUNXI_MMC_CMD_START | + SUNXI_MMC_CMD_UPCLK_ONLY | + SUNXI_MMC_CMD_WAIT_PRE_OVER; + writel(cmd, &mmchost->reg->cmd); + while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + /* clock update sets various irq status bits, clear these */ + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc, unsigned div) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* Disable Clock */ + rval &= ~SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Change Divider Factor */ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + rval |= div; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + /* Re-enable Clock */ + rval |= SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int clkdiv = 0; + + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n", + mmc->bus_width, mmc->clock, mmchost->mod_clk); + + /* Change clock first */ + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2; + if (mmc->clock) { + if (mmc_config_clock(mmc, clkdiv)) { + mmchost->fatal_err = 1; + return; + } + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(0x2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(0x1, &mmchost->reg->width); + else + writel(0x0, &mmchost->reg->width); +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + const int reading = !!(data->flags & MMC_DATA_READ); + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : + SUNXI_MMC_STATUS_FIFO_FULL; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned timeout_msecs = 2000; + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); + + for (i = 0; i < (byte_cnt >> 2); i++) { + while (readl(&mmchost->reg->status) & status_bit) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + if (reading) + buff[i] = readl(mmchost->database); + else + writel(buff[i], mmchost->database); + } + + return 0; +} + +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned char *buff; + unsigned des_idx = 0; + unsigned buff_frag_num = + (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT; + unsigned remain; + unsigned i, rval; + ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num); + + buff = data->flags & MMC_DATA_READ ? + (unsigned char *)data->dest : (unsigned char *)data->src; + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); + + flush_cache((unsigned long)buff, (unsigned long)byte_cnt); + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */ + else + pdes[des_idx].data_buf1_sz = remain; + + pdes[des_idx].buf_addr_ptr1 = + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0) + pdes[des_idx].first_des = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_des = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; + } + } + flush_cache((unsigned long)pdes, + sizeof(struct sunxi_mmc_des) * (des_idx + 1)); + + rval = readl(&mmchost->reg->gctrl); + /* Enable DMA */ + writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + /* Reset iDMA */ + writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac); + /* Enable iDMA */ + writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE, + &mmchost->reg->dmac); + rval = readl(&mmchost->reg->idie) & + ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ); + if (data->flags & MMC_DATA_WRITE) + rval |= SUNXI_MMC_IDIE_TXIRQ; + else + rval |= SUNXI_MMC_IDIE_RXIRQ; + writel(rval, &mmchost->reg->idie); + writel((u32) pdes, &mmchost->reg->dlba); + writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3), + &mmchost->reg->ftrglevel); + + return 0; +} + +static void mmc_enable_dma_accesses(struct mmc *mmc, int dma) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + unsigned int gctrl = readl(&mmchost->reg->gctrl); + if (dma) + gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + else + gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + writel(gctrl, &mmchost->reg->gctrl); +} + +static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, + unsigned int done_bit, const char *what) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int status; + + do { + status = readl(&mmchost->reg->rint); + if (!timeout_msecs-- || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return TIMEOUT; + } + udelay(1000); + } while (!(status & done_bit)); + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmdval = SUNXI_MMC_CMD_START; + unsigned int timeout_msecs; + int error = 0; + unsigned int status = 0; + unsigned int usedma = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + if (!cmd->cmdidx) + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) + cmdval |= SUNXI_MMC_CMD_WRITE; + if (data->blocks > 1) + cmdval |= SUNXI_MMC_CMD_AUTO_STOP; + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) + if (bytecnt > 64) { +#else + if (0) { +#endif + usedma = 1; + mmc_enable_dma_accesses(mmc, 1); + ret = mmc_trans_data_by_dma(mmc, data); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + } else { + mmc_enable_dma_accesses(mmc, 0); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + } + if (ret) { + error = readl(&mmchost->reg->rint) & \ + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; + error = TIMEOUT; + goto out; + } + } + + error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); + if (error) + goto out; + + if (data) { + timeout_msecs = usedma ? 120 * bytecnt : 120; + debug("cacl timeout %x msec\n", timeout_msecs); + error = mmc_rint_wait(mmc, timeout_msecs, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, + "data"); + if (error) + goto out; + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout_msecs = 2000; + do { + status = readl(&mmchost->reg->status); + if (!timeout_msecs--) { + debug("busy timeout\n"); + error = TIMEOUT; + goto out; + } + udelay(1000); + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (data && usedma) { + /* IDMASTAREG + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = readl(&mmchost->reg->idst); + writel(status, &mmchost->reg->idst); + writel(0, &mmchost->reg->idie); + writel(0, &mmchost->reg->dmac); + writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + } + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, + &mmchost->reg->gctrl); + + return error; +} + +static const struct mmc_ops sunxi_mmc_ops = { + .send_cmd = mmc_send_cmd, + .set_ios = mmc_set_ios, + .init = mmc_core_init, +}; + +int sunxi_mmc_init(int sdc_no) +{ + struct mmc_config *cfg = &mmc_host[sdc_no].cfg; + + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + + cfg->name = "SUNXI SD/MMC"; + cfg->ops = &sunxi_mmc_ops; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + mmc_resource_init(sdc_no); + mmc_clk_io_on(sdc_no); + + if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL) + return -1; + + return 0; +} diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 881a63618c..bf99b8e675 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, dat[byte_pos] ^= 1 << bit_pos; printf("nand: bit-flip corrected @data=%d\n", byte_pos); } else if (byte_pos < error_max) { - read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos; + read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; printf("nand: bit-flip corrected @oob=%d\n", byte_pos - SECTOR_BYTES); } else { diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c45593bcc0..7186e3b491 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -249,7 +249,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); @@ -280,10 +280,18 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - /* Invalidate only "status" field for the following check */ - invalidate_dcache_range((unsigned long)&desc_p->txrx_status, - (unsigned long)&desc_p->txrx_status + - sizeof(desc_p->txrx_status)); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so roundup to + * ARCH_DMA_MINALIGN. This is safe because the individual + * descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN. + */ + invalidate_dcache_range( + (unsigned long)desc_p, + (unsigned long)desc_p + + roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN)); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -351,7 +359,7 @@ static int dw_eth_recv(struct eth_device *dev) /* Invalidate received data */ invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, (unsigned long)desc_p->dmamac_addr + - length); + roundup(length, ARCH_DMA_MINALIGN)); NetReceive(desc_p->dmamac_addr, length); @@ -390,6 +398,8 @@ static int dw_phy_init(struct eth_device *dev) if (!phydev) return -1; + phy_connect_dev(phydev, dev); + phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; @@ -412,7 +422,8 @@ int designware_initialize(ulong base_addr, u32 interface) * Since the priv structure contains the descriptors which need a strict * buswidth alignment, memalign is used to allocate memory */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 382b0c7f0a..ce51102052 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -77,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) @@ -215,15 +215,14 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 interface; - u32 tx_currdescnum; - u32 rx_currdescnum; - struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); - char txbuffs[TX_TOTAL_BUFSIZE]; - char rxbuffs[RX_TOTAL_BUFSIZE]; + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index b68d808c74..4de9d41642 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -345,7 +345,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) if (!is_valid_ether_addr(dev->enetaddr)) { #ifdef CONFIG_RANDOM_MACADDR printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); printf("MAC: %pM\n", dev->enetaddr); #else printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index ee5d768937..5ae3b167a9 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 2f4bc11a6c..de9c0e9cd2 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) @@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 8eee272cf1..98c4f09629 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -425,7 +425,7 @@ int ftmac110_initialize(bd_t *bis) dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index abd4e5b463..d509e30d35 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -31,9 +31,7 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); - genphy_config_aneg(phydev); - - phy_reset(phydev); + phydev->supported = phydev->drv->features; return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index c691fbbbc6..230ed97dd1 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,7 @@ #include <phy.h> #include <errno.h> #include <linux/err.h> +#include <linux/compiler.h> /* Generic PHY support and helper functions */ @@ -577,7 +578,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, * Description: Reads the ID registers of the PHY at @addr on the * @bus, stores it in @phy_id and returns zero on success. */ -static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) { int phy_reg; diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 3a55d271a5..c58fe50b72 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -58,6 +58,14 @@ #define MIIM_VSC8514_18G_QSGMII 0x80e0 #define MIIM_VSC8514_18G_CMDSTAT 0x8000 +/* Vitesse VSC8664 Control/Status Register */ +#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13 +#define MIIM_VSC8664_ADDITIONAL_DEV 0x16 +#define MIIM_VSC8664_EPHY_CON 0x17 +#define MIIM_VSC8664_LED_CON 0x1E + +#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001 + /* CIS8201 */ static int vitesse_config(struct phy_device *phydev) { @@ -244,6 +252,33 @@ static int vsc8514_config(struct phy_device *phydev) return 0; } +static int vsc8664_config(struct phy_device *phydev) +{ + u32 val; + + /* Enable MAC interface auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); + val |= (1 << 13); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); + val |= (1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* Enable LED blink */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); + val &= ~(1 << 2); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); + + genphy_config_aneg(phydev); + + return 0; +} + static struct phy_driver VSC8211_driver = { .name = "Vitesse VSC8211", .uid = 0xfc4b0, @@ -334,6 +369,16 @@ static struct phy_driver VSC8662_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8664_driver = { + .name = "Vitesse VSC8664", + .uid = 0x70660, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8664_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + /* Vitesse bought Cicada, so we'll put these here */ static struct phy_driver cis8201_driver = { .name = "CIS8201", @@ -366,6 +411,7 @@ int phy_vitesse_init(void) phy_register(&VSC8574_driver); phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); + phy_register(&VSC8664_driver); phy_register(&cis8201_driver); phy_register(&cis8204_driver); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 6317fb1324..3a41b0ec17 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -49,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi, u64 size) { u32 sz = (__ilog2_u64(size) - 1); - u32 flag = PIWAR_EN | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + u32 flag = 0; +#else + u32 flag = PIWAR_LOCAL; +#endif + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; out_be32(&pi->pitar, r->phys_start >> 12); out_be32(&pi->piwbar, r->bus_start >> 12); diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 3244f690b9..9a8bfe07b8 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c new file mode 100644 index 0000000000..9b874cb07c --- /dev/null +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/ltc3676_pmic.h> + +int power_ltc3676_init(unsigned char bus) +{ + static const char name[] = "LTC3676_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = LTC3676_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index 22c1f15eeb..21f12d2564 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -11,7 +11,7 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -int pmic_init(unsigned char bus) +int power_pfuze100_init(unsigned char bus) { static const char name[] = "PFUZE100_PMIC"; struct pmic *p = pmic_alloc(); diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 704c2439b1..d29d969533 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -32,7 +32,7 @@ enum { }; #define MAX_I2C_RETRY 3 -int tps6586x_read(int reg) +static int tps6586x_read(int reg) { int i; uchar data; @@ -61,7 +61,7 @@ exit: return retval; } -int tps6586x_write(int reg, uchar *data, uint len) +static int tps6586x_write(int reg, uchar *data, uint len) { int i; int retval = -1; diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b1da75ec4d..9c5fbd1d69 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -14,6 +14,8 @@ #include "asm/immap_qe.h" #include "qe.h" +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 + qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8a13454943..f26979dbe1 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -33,6 +33,12 @@ #if defined(CONFIG_K2HK_EVM) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#undef UART_MCRVAL +#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL +#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) +#else +#define UART_MCRVAL (UART_MCR_RTS) +#endif #endif #ifndef CONFIG_SYS_NS16550_IER diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c4fb59cfb3..fd61a5e545 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) - gd->bd->bi_baudrate = baudrate; -#endif serial_setbrg(); @@ -502,12 +499,11 @@ int uart_post_test(int flags) unsigned char c; int ret, saved_baud, b; struct serial_device *saved_dev, *s; - bd_t *bd = gd->bd; /* Save current serial state */ ret = 0; saved_dev = serial_current; - saved_baud = bd->bi_baudrate; + saved_baud = gd->baudrate; for (s = serial_devices; s; s = s->next) { /* If this driver doesn't support loop back, skip it */ @@ -530,7 +526,7 @@ int uart_post_test(int flags) /* Test every available baud rate */ for (b = 0; b < ARRAY_SIZE(bauds); ++b) { - bd->bi_baudrate = bauds[b]; + gd->baudrate = bauds[b]; serial_setbrg(); /* @@ -572,7 +568,7 @@ int uart_post_test(int flags) done: /* Restore previous serial state */ serial_current = saved_dev; - bd->bi_baudrate = saved_baud; + gd->baudrate = saved_baud; serial_reinit_all(); serial_setbrg(); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 896c8d407e..66becdc782 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_THOR_FUNCTION) += f_thor.o obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o +obj-$(CONFIG_CMD_FASTBOOT) += f_fastboot.o endif ifdef CONFIG_USB_ETHER obj-y += ether.o diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 02d3fdade8..9cd003636a 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -205,13 +205,26 @@ static void ci_invalidate_qtd(int ep_num) static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { - struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); - return &ci_ep->req; + struct ci_req *ci_req; + + ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); + if (!ci_req) + return NULL; + + INIT_LIST_HEAD(&ci_req->queue); + ci_req->b_buf = 0; + + return &ci_req->req; } -static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) { - return; + struct ci_req *ci_req; + + ci_req = container_of(req, struct ci_req, req); + if (ci_req->b_buf) + free(ci_req->b_buf); + free(ci_req); } static void ep_enable(int num, int in, int maxpacket) @@ -267,99 +280,102 @@ static int ci_ep_disable(struct usb_ep *ep) return 0; } -static int ci_bounce(struct ci_ep *ep, int in) +static int ci_bounce(struct ci_req *ci_req, int in) { - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba; + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr; + uint32_t aligned_used_len; /* Input buffer address is not aligned. */ if (addr & (ARCH_DMA_MINALIGN - 1)) goto align; /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + if (req->length & (ARCH_DMA_MINALIGN - 1)) goto align; /* The buffer is well aligned, only flush cache. */ - ep->b_len = ep->req.length; - ep->b_buf = ep->req.buf; + ci_req->hw_len = req->length; + ci_req->hw_buf = req->buf; goto flush; align: - /* Use internal buffer for small payloads. */ - if (ep->req.length <= 64) { - ep->b_len = 64; - ep->b_buf = ep->b_fast; - } else { - ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); - ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); - if (!ep->b_buf) + if (ci_req->b_buf && req->length > ci_req->b_len) { + free(ci_req->b_buf); + ci_req->b_buf = 0; + } + if (!ci_req->b_buf) { + ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN); + ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len); + if (!ci_req->b_buf) return -ENOMEM; } + ci_req->hw_len = ci_req->b_len; + ci_req->hw_buf = ci_req->b_buf; + if (in) - memcpy(ep->b_buf, ep->req.buf, ep->req.length); + memcpy(ci_req->hw_buf, req->buf, req->length); flush: - ba = (uint32_t)ep->b_buf; - flush_dcache_range(ba, ba + ep->b_len); + hwaddr = (uint32_t)ci_req->hw_buf; + aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN); + flush_dcache_range(hwaddr, hwaddr + aligned_used_len); return 0; } -static void ci_debounce(struct ci_ep *ep, int in) +static void ci_debounce(struct ci_req *ci_req, int in) { - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba = (uint32_t)ep->b_buf; + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr = (uint32_t)ci_req->hw_buf; + uint32_t aligned_used_len; - if (in) { - if (addr == ba) - return; /* not a bounce */ - goto free; - } - invalidate_dcache_range(ba, ba + ep->b_len); + if (in) + return; + + aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN); + invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len); - if (addr == ba) - return; /* not a bounce */ + if (addr == hwaddr) + return; /* not a bounce */ - memcpy(ep->req.buf, ep->b_buf, ep->req.actual); -free: - /* Large payloads use allocated buffer, free it. */ - if (ep->b_buf != ep->b_fast) - free(ep->b_buf); + memcpy(req->buf, ci_req->hw_buf, req->actual); } -static int ci_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags) +static void ci_ep_submit_next_request(struct ci_ep *ci_ep) { - struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_item *item; struct ept_queue_head *head; - int bit, num, len, in, ret; + int bit, num, len, in; + struct ci_req *ci_req; + + ci_ep->req_primed = true; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); head = ci_get_qh(num, in); - len = req->length; - ret = ci_bounce(ci_ep, in); - if (ret) - return ret; + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + len = ci_req->req.length; item->next = TERMINATE; item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)ci_ep->b_buf; - item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; - item->page2 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x2000; - item->page3 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x3000; - item->page4 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x4000; + item->page0 = (uint32_t)ci_req->hw_buf; + item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; + item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; + item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; + item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; ci_flush_qtd(num); head->next = (unsigned) item; head->info = 0; - DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, ci_ep->b_buf); + DBG("ept%d %s queue len %x, req %p, buffer %p\n", + num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); ci_flush_qh(num); if (in) @@ -368,6 +384,29 @@ static int ci_ep_queue(struct usb_ep *ep, bit = EPT_RX(num); writel(bit, &udc->epprime); +} + +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_req *ci_req = container_of(req, struct ci_req, req); + int in, ret; + int __maybe_unused num; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + + ret = ci_bounce(ci_req, in); + if (ret) + return ret; + + DBG("ept%d %s pre-queue req %p, buffer %p\n", + num, in ? "in" : "out", ci_req, ci_req->hw_buf); + list_add_tail(&ci_req->queue, &ci_ep->queue); + + if (!ci_ep->req_primed) + ci_ep_submit_next_request(ci_ep); return 0; } @@ -376,6 +415,8 @@ static void handle_ep_complete(struct ci_ep *ep) { struct ept_queue_item *item; int num, in, len; + struct ci_req *ci_req; + num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) @@ -383,20 +424,27 @@ static void handle_ep_complete(struct ci_ep *ep) item = ci_get_qtd(num, in); ci_invalidate_qtd(num); + len = (item->info >> 16) & 0x7fff; if (item->info & 0xff) printf("EP%d/%s FAIL info=%x pg0=%x\n", num, in ? "in" : "out", item->info, item->page0); - len = (item->info >> 16) & 0x7fff; - ep->req.actual = ep->req.length - len; - ci_debounce(ep, in); + ci_req = list_first_entry(&ep->queue, struct ci_req, queue); + list_del_init(&ci_req->queue); + ep->req_primed = false; + + if (!list_empty(&ep->queue)) + ci_ep_submit_next_request(ep); + + ci_req->req.actual = ci_req->req.length - len; + ci_debounce(ci_req, in); - DBG("ept%d %s complete %x\n", - num, in ? "in" : "out", len); - ep->req.complete(&ep->ep, &ep->req); + DBG("ept%d %s req %p, complete %x\n", + num, in ? "in" : "out", ci_req, len); + ci_req->req.complete(&ep->ep, &ci_req->req); if (num == 0) { - ep->req.length = 0; - usb_ep_queue(&ep->ep, &ep->req, 0); + ci_req->req.length = 0; + usb_ep_queue(&ep->ep, &ci_req->req, 0); ep->desc = &ep0_in_desc; } } @@ -405,13 +453,18 @@ static void handle_ep_complete(struct ci_ep *ep) static void handle_setup(void) { - struct usb_request *req = &controller.ep[0].req; + struct ci_ep *ci_ep = &controller.ep[0]; + struct ci_req *ci_req; + struct usb_request *req; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_head *head; struct usb_ctrlrequest r; int status = 0; int num, in, _num, _in, i; char *buf; + + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + req = &ci_req->req; head = ci_get_qh(0, 0); /* EP0 OUT */ ci_invalidate_qh(0); @@ -424,6 +477,9 @@ static void handle_setup(void) DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, r.wValue); + list_del_init(&ci_req->queue); + ci_ep->req_primed = false; + switch (SETUP(r.bRequestType, r.bRequest)) { case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): _num = r.wIndex & 15; @@ -701,6 +757,8 @@ static int ci_udc_probe(void) /* Init EP 0 */ memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); controller.ep[0].desc = &ep0_in_desc; + INIT_LIST_HEAD(&controller.ep[0].queue); + controller.ep[0].req_primed = false; controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); @@ -708,6 +766,8 @@ static int ci_udc_probe(void) for (i = 1; i < NUM_ENDPOINTS; i++) { memcpy(&controller.ep[i].ep, &ci_ep_init[1], sizeof(*ci_ep_init)); + INIT_LIST_HEAD(&controller.ep[i].queue); + controller.ep[i].req_primed = false; list_add_tail(&controller.ep[i].ep.ep_list, &controller.gadget.ep_list); } diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 4425fd9345..23cff56d7e 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -77,15 +77,22 @@ struct ci_udc { #define CTRL_TXT_BULK (2 << 18) #define CTRL_RXT_BULK (2 << 2) +struct ci_req { + struct usb_request req; + struct list_head queue; + /* Bounce buffer allocated if needed to align the transfer */ + uint8_t *b_buf; + uint32_t b_len; + /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ + uint8_t *hw_buf; + uint32_t hw_len; +}; + struct ci_ep { struct usb_ep ep; struct list_head queue; + bool req_primed; const struct usb_endpoint_descriptor *desc; - - struct usb_request req; - uint8_t *b_buf; - uint32_t b_len; - uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); }; struct ci_drv { diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 1b1e1793d9..859fe828de 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -175,10 +175,17 @@ static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) req->length, f_dfu->blk_seq_num); } +static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu) +{ + return dfu->poll_timeout ? dfu->poll_timeout(dfu) : + DFU_MANIFEST_POLL_TIMEOUT; +} + static void handle_getstatus(struct usb_request *req) { struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + struct dfu_entity *dfu = dfu_get_entity(f_dfu->altsetting); dfu_set_poll_timeout(dstat, 0); @@ -191,7 +198,8 @@ static void handle_getstatus(struct usb_request *req) f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; break; case DFU_STATE_dfuMANIFEST: - dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT); + dfu_set_poll_timeout(dstat, dfu_get_manifest_timeout(dfu)); + break; default: break; } diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c new file mode 100644 index 0000000000..9dd85b636e --- /dev/null +++ b/drivers/usb/gadget/f_fastboot.c @@ -0,0 +1,513 @@ +/* + * (C) Copyright 2008 - 2009 + * Windriver, <www.windriver.com> + * Tom Rix <Tom.Rix@windriver.com> + * + * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de> + * + * Copyright 2014 Linaro, Ltd. + * Rob Herring <robh@kernel.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/composite.h> +#include <linux/compiler.h> +#include <version.h> +#include <g_dnl.h> + +#define FASTBOOT_VERSION "0.4" + +#define FASTBOOT_INTERFACE_CLASS 0xff +#define FASTBOOT_INTERFACE_SUB_CLASS 0x42 +#define FASTBOOT_INTERFACE_PROTOCOL 0x03 + +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200) +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) + +/* The 64 defined bytes plus \0 */ +#define RESPONSE_LEN (64 + 1) + +#define EP_BUFFER_SIZE 4096 + +struct f_fastboot { + struct usb_function usb_function; + + /* IN/OUT EP's and correspoinding requests */ + struct usb_ep *in_ep, *out_ep; + struct usb_request *in_req, *out_req; +}; + +static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) +{ + return container_of(f, struct f_fastboot, usb_function); +} + +static struct f_fastboot *fastboot_func; +static unsigned int download_size; +static unsigned int download_bytes; + +static struct usb_endpoint_descriptor fs_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor fs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor hs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0, + .bInterval = 0x00, +}; + +static struct usb_interface_descriptor interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = FASTBOOT_INTERFACE_CLASS, + .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS, + .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL, +}; + +static struct usb_descriptor_header *fb_runtime_descs[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&fs_ep_in, + (struct usb_descriptor_header *)&hs_ep_out, + NULL, +}; + +/* + * static strings, in UTF-8 + */ +static const char fastboot_name[] = "Android Fastboot"; + +static struct usb_string fastboot_string_defs[] = { + [0].s = fastboot_name, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_fastboot = { + .language = 0x0409, /* en-us */ + .strings = fastboot_string_defs, +}; + +static struct usb_gadget_strings *fastboot_strings[] = { + &stringtab_fastboot, + NULL, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); + +static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + if (!status) + return; + printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); +} + +static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) +{ + int id; + struct usb_gadget *gadget = c->cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + /* DYNAMIC interface numbers assignments */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + interface_desc.bInterfaceNumber = id; + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + fastboot_string_defs[0].id = id; + interface_desc.iInterface = id; + + f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); + if (!f_fb->in_ep) + return -ENODEV; + f_fb->in_ep->driver_data = c->cdev; + + f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); + if (!f_fb->out_ep) + return -ENODEV; + f_fb->out_ep->driver_data = c->cdev; + + hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + + return 0; +} + +static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) +{ + memset(fastboot_func, 0, sizeof(*fastboot_func)); +} + +static void fastboot_disable(struct usb_function *f) +{ + struct f_fastboot *f_fb = func_to_fastboot(f); + + usb_ep_disable(f_fb->out_ep); + usb_ep_disable(f_fb->in_ep); + + if (f_fb->out_req) { + free(f_fb->out_req->buf); + usb_ep_free_request(f_fb->out_ep, f_fb->out_req); + f_fb->out_req = NULL; + } + if (f_fb->in_req) { + free(f_fb->in_req->buf); + usb_ep_free_request(f_fb->in_ep, f_fb->in_req); + f_fb->in_req = NULL; + } +} + +static struct usb_request *fastboot_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return NULL; + + req->length = EP_BUFFER_SIZE; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + + memset(req->buf, 0, req->length); + return req; +} + +static int fastboot_set_alt(struct usb_function *f, + unsigned interface, unsigned alt) +{ + int ret; + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, interface, alt); + + /* make sure we don't enable the ep twice */ + if (gadget->speed == USB_SPEED_HIGH) + ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); + else + ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); + if (ret) { + puts("failed to enable out ep\n"); + return ret; + } + + f_fb->out_req = fastboot_start_ep(f_fb->out_ep); + if (!f_fb->out_req) { + puts("failed to alloc out req\n"); + ret = -EINVAL; + goto err; + } + f_fb->out_req->complete = rx_handler_command; + + ret = usb_ep_enable(f_fb->in_ep, &fs_ep_in); + if (ret) { + puts("failed to enable in ep\n"); + goto err; + } + + f_fb->in_req = fastboot_start_ep(f_fb->in_ep); + if (!f_fb->in_req) { + puts("failed alloc req in\n"); + ret = -EINVAL; + goto err; + } + f_fb->in_req->complete = fastboot_complete; + + ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0); + if (ret) + goto err; + + return 0; +err: + fastboot_disable(f); + return ret; +} + +static int fastboot_add(struct usb_configuration *c) +{ + struct f_fastboot *f_fb = fastboot_func; + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + if (!f_fb) { + f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); + if (!f_fb) + return -ENOMEM; + + fastboot_func = f_fb; + memset(f_fb, 0, sizeof(*f_fb)); + } + + f_fb->usb_function.name = "f_fastboot"; + f_fb->usb_function.hs_descriptors = fb_runtime_descs; + f_fb->usb_function.bind = fastboot_bind; + f_fb->usb_function.unbind = fastboot_unbind; + f_fb->usb_function.set_alt = fastboot_set_alt; + f_fb->usb_function.disable = fastboot_disable; + f_fb->usb_function.strings = fastboot_strings; + + status = usb_add_function(c, &f_fb->usb_function); + if (status) { + free(f_fb); + fastboot_func = f_fb; + } + + return status; +} +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); + +int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +{ + struct usb_request *in_req = fastboot_func->in_req; + int ret; + + memcpy(in_req->buf, buffer, buffer_size); + in_req->length = buffer_size; + ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0); + if (ret) + printf("Error %d on queue\n", ret); + return 0; +} + +static int fastboot_tx_write_str(const char *buffer) +{ + return fastboot_tx_write(buffer, strlen(buffer)); +} + +static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +{ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = compl_do_reset; + fastboot_tx_write_str("OKAY"); +} + +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +static void cb_getvar(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + const char *s; + + strcpy(response, "OKAY"); + strsep(&cmd, ":"); + if (!cmd) { + fastboot_tx_write_str("FAILmissing var"); + return; + } + + if (!strcmp_l1("version", cmd)) { + strncat(response, FASTBOOT_VERSION, sizeof(response)); + } else if (!strcmp_l1("bootloader-version", cmd)) { + strncat(response, U_BOOT_VERSION, sizeof(response)); + } else if (!strcmp_l1("downloadsize", cmd)) { + char str_num[12]; + + sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); + strncat(response, str_num, sizeof(response)); + } else if (!strcmp_l1("serialno", cmd)) { + s = getenv("serial#"); + if (s) + strncat(response, s, sizeof(response)); + else + strcpy(response, "FAILValue not set"); + } else { + strcpy(response, "FAILVariable not implemented"); + } + fastboot_tx_write_str(response); +} + +static unsigned int rx_bytes_expected(void) +{ + int rx_remain = download_size - download_bytes; + if (rx_remain < 0) + return 0; + if (rx_remain > EP_BUFFER_SIZE) + return EP_BUFFER_SIZE; + return rx_remain; +} + +#define BYTES_PER_DOT 0x20000 +static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) +{ + char response[RESPONSE_LEN]; + unsigned int transfer_size = download_size - download_bytes; + const unsigned char *buffer = req->buf; + unsigned int buffer_size = req->actual; + + if (req->status != 0) { + printf("Bad status: %d\n", req->status); + return; + } + + if (buffer_size < transfer_size) + transfer_size = buffer_size; + + memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes, + buffer, transfer_size); + + download_bytes += transfer_size; + + /* Check if transfer is done */ + if (download_bytes >= download_size) { + /* + * Reset global transfer variable, keep download_bytes because + * it will be used in the next possible flashing command + */ + download_size = 0; + req->complete = rx_handler_command; + req->length = EP_BUFFER_SIZE; + + sprintf(response, "OKAY"); + fastboot_tx_write_str(response); + + printf("\ndownloading of %d bytes finished\n", download_bytes); + } else { + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + + if (download_bytes && !(download_bytes % BYTES_PER_DOT)) { + putc('.'); + if (!(download_bytes % (74 * BYTES_PER_DOT))) + putc('\n'); + } + req->actual = 0; + usb_ep_queue(ep, req, 0); +} + +static void cb_download(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + download_size = simple_strtoul(cmd, NULL, 16); + download_bytes = 0; + + printf("Starting download of %d bytes\n", download_size); + + if (0 == download_size) { + sprintf(response, "FAILdata invalid size"); + } else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) { + download_size = 0; + sprintf(response, "FAILdata too large"); + } else { + sprintf(response, "DATA%08x", download_size); + req->complete = rx_handler_dl_image; + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + fastboot_tx_write_str(response); +} + +static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req) +{ + char boot_addr_start[12]; + char *bootm_args[] = { "bootm", boot_addr_start, NULL }; + + puts("Booting kernel..\n"); + + sprintf(boot_addr_start, "0x%lx", load_addr); + do_bootm(NULL, 0, 2, bootm_args); + + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_boot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = do_bootm_on_complete; + fastboot_tx_write_str("OKAY"); +} + +struct cmd_dispatch_info { + char *cmd; + void (*cb)(struct usb_ep *ep, struct usb_request *req); +}; + +static const struct cmd_dispatch_info cmd_dispatch_info[] = { + { + .cmd = "reboot", + .cb = cb_reboot, + }, { + .cmd = "getvar:", + .cb = cb_getvar, + }, { + .cmd = "download:", + .cb = cb_download, + }, { + .cmd = "boot", + .cb = cb_boot, + }, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) +{ + char *cmdbuf = req->buf; + void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) { + if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) { + func_cb = cmd_dispatch_info[i].cb; + break; + } + } + + if (!func_cb) + fastboot_tx_write_str("FAILunknown command"); + else + func_cb(ep, req); + + if (req->status == 0) { + *cmdbuf = '\0'; + req->actual = 0; + usb_ep_queue(ep, req, 0); + } +} diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index feef9e4619..28f215e07c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -219,21 +219,15 @@ static int download_tail(long long int left, int cnt) } /* - * To store last "packet" DFU storage backend requires dfu_write with - * size parameter equal to 0 + * To store last "packet" or write file from buffer to filesystem + * DFU storage backend requires dfu_flush * * This also frees memory malloc'ed by dfu_get_buf(), so no explicit * need fo call dfu_free_buf() is needed. */ - ret = dfu_write(dfu_entity, transfer_buffer, 0, cnt); - if (ret) - error("DFU write failed [%d] cnt: %d", ret, cnt); - ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt); - if (ret) { + if (ret) error("DFU flush failed!"); - return ret; - } return ret; } diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index 74300746b9..02803df23c 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -311,11 +311,7 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev) #define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */ /* Number of buffers we will use. 2 is enough for double-buffering */ -#ifndef CONFIG_CI_UDC #define FSG_NUM_BUFFERS 2 -#else -#define FSG_NUM_BUFFERS 1 /* ci_udc only allows 1 req per ep at present */ -#endif /* Default size of buffer length. */ #define FSG_BUFLEN ((u32)16384) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b301e28252..7211c6ad96 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6cb4d98668..45062e699b 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) - setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); - setbits_be32(&ehci->control, UTMI_PHY_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_UTMI); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); - setbits_be32(&ehci->control, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + USB_EN); } else { - setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); - clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_ULPI); + clrsetbits_be32(&ehci->control, UTMI_PHY_EN | + CONTROL_REGISTER_W1C_MASK, USB_EN); udelay(1000); /* delay required for PHY Clk to appear */ if (!usb_phy_clk_valid(ehci)) return -EINVAL; diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 38db18e2c9..33e5ea9ebd 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -69,6 +69,7 @@ struct fdt_usb { unsigned enabled:1; /* 1 to enable, 0 to disable */ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ unsigned initialized:1; /* has this port already been initialized? */ + enum usb_init_type init_type; enum dr_mode dr_mode; /* dual role mode */ enum periph_id periph_id;/* peripheral id */ struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ @@ -237,29 +238,31 @@ int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) return PORTSC_PSPD(reg); } -/* Put the port into host mode */ -static void set_host_mode(struct fdt_usb *config) +/* Set up VBUS for host/device mode */ +static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) { /* - * If we are an OTG port, check if remote host is driving VBus and - * bail out in this case. + * If we are an OTG port initializing in host mode, + * check if remote host is driving VBus and bail out in this case. */ - if (config->dr_mode == DR_MODE_OTG && - (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + if (init == USB_INIT_HOST && + config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { + printf("tegrausb: VBUS input active; not enabling as host\n"); return; + } - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ if (fdt_gpio_isvalid(&config->vbus_gpio)) { + int vbus_value; + fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - 0 : 1); - debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - "low" : "high"); + + vbus_value = (init == USB_INIT_HOST) ^ + !!(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW); + gpio_direction_output(config->vbus_gpio.gpio, vbus_value); + + debug("set_up_vbus: GPIO %d %d\n", config->vbus_gpio.gpio, + vbus_value); } } @@ -293,10 +296,44 @@ static const unsigned *get_pll_timing(void) return timing; } +/* select the PHY to use with a USB controller */ +static void init_phy_mux(struct fdt_usb *config, uint pts, + enum usb_init_type init) +{ + struct usb_ctlr *usbctlr = config->reg; + +#if defined(CONFIG_TEGRA20) + if (config->periph_id == PERIPH_ID_USBD) { + clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, + PTS_UTMI << PTS1_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS1); + } else { + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + } +#else + /* Set to Host mode (if applicable) after Controller Reset was done */ + clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, + (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); + /* + * Select PHY interface after setting host mode. + * For device mode, the ordering requirement is not an issue, since + * only the first USB controller supports device mode, and that USB + * controller can only talk to a UTMI PHY, so the PHY selection is + * already made at reset time, so this write is a no-op. + */ + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, + pts << PTS_SHIFT); + clrbits_le32(&usbctlr->hostpc1_devlc, STS); +#endif +} + /* set up the UTMI USB controller with the parameters provided */ -static int init_utmi_usb_controller(struct fdt_usb *config) +static int init_utmi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { - u32 val; + u32 b_sess_valid_mask, val; int loop_count; const unsigned *timing; struct usb_ctlr *usbctlr = config->reg; @@ -314,6 +351,10 @@ static int init_utmi_usb_controller(struct fdt_usb *config) /* Follow the crystal clock disable by >100ns delay */ udelay(1); + b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); + clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, + (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); + /* * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. @@ -485,21 +526,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config) clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); /* Select UTMI parallel interface */ -#if defined(CONFIG_TEGRA20) - if (config->periph_id == PERIPH_ID_USBD) { - clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, - PTS_UTMI << PTS1_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS1); - } else { - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS); - } -#else - clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->hostpc1_devlc, STS); -#endif + init_phy_mux(config, PTS_UTMI, init); /* Deassert power down state */ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | @@ -529,7 +556,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config) #endif /* set up the ULPI USB controller with the parameters provided */ -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { u32 val; int loop_count; @@ -557,13 +585,7 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); /* Select ULPI parallel interface */ -#if defined(CONFIG_TEGRA20) - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_ULPI << PTS_SHIFT); -#else - clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, - PTS_ULPI << PTS_SHIFT); -#endif + init_phy_mux(config, PTS_ULPI, init); /* enable ULPI transceiver */ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); @@ -612,7 +634,8 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) return 0; } #else -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { printf("No code to set up ULPI controller, please enable" "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); @@ -765,42 +788,66 @@ int ehci_hcd_init(int index, enum usb_init_type init, config = &port[index]; + switch (init) { + case USB_INIT_HOST: + switch (config->dr_mode) { + case DR_MODE_HOST: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for host mode\n", + config->dr_mode); + return -1; + } + break; + case USB_INIT_DEVICE: + if (config->periph_id != PERIPH_ID_USBD) { + printf("tegrausb: Device mode only supported on first USB controller\n"); + return -1; + } + if (!config->utmi) { + printf("tegrausb: Device mode only supported with UTMI PHY\n"); + return -1; + } + switch (config->dr_mode) { + case DR_MODE_DEVICE: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for device mode\n", + config->dr_mode); + return -1; + } + break; + default: + printf("tegrausb: Unknown USB_INIT_* %d\n", init); + return -1; + } + /* skip init, if the port is already initialized */ - if (config->initialized) + if (config->initialized && config->init_type == init) goto success; - if (config->utmi && init_utmi_usb_controller(config)) { + if (config->utmi && init_utmi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - if (config->ulpi && init_ulpi_usb_controller(config)) { + if (config->ulpi && init_ulpi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - set_host_mode(config); + set_up_vbus(config, init); config->initialized = 1; + config->init_type = init; success: usbctlr = config->reg; *hccr = (struct ehci_hccr *)&usbctlr->cap_length; *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; - if (controller->has_hostpc) { - /* Set to Host mode after Controller Reset was done */ - clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, - USBMODE_CM_HC); - /* Select UTMI parallel interface after setting host mode */ - if (config->utmi) { - clrsetbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, STS); - } - } return 0; } diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c new file mode 100644 index 0000000000..7770d05646 --- /dev/null +++ b/drivers/usb/host/ehci-zynq.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014, Xilinx, Inc + * + * USB Low level initialization(Specific to zynq) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <usb/ulpi.h> + +#include "ehci.h" + +#define ZYNQ_USB_USBCMD_RST 0x0000002 +#define ZYNQ_USB_USBCMD_STOP 0x0000000 +#define ZYNQ_USB_NUM_MIO 12 + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct usb_ehci *ehci; + struct ulpi_viewport ulpi_vp; + int ret, mio_usb; + /* Used for writing the ULPI data address */ + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + + if (!index) { + mio_usb = zynq_slcr_get_mio_pin_status("usb0"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + } else { + mio_usb = zynq_slcr_get_mio_pin_status("usb1"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + } + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ret = ulpi_init(&ulpi_vp); + if (ret) { + puts("zynq ULPI viewport init failed\n"); + return -1; + } + + /* ULPI set flags */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | + ULPI_OTG_EXTVBUSIND); + ulpi_write(&ulpi_vp, &ulpi->function_ctrl, + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | + ULPI_FC_SUSPENDM); + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); + + /* Set VBus */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + struct usb_ehci *ehci; + + if (!index) + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + else + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + + /* Stop controller */ + writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd); + udelay(1000); + + /* Initiate controller reset */ + writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd); + + return 0; +} diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 6599d386dc..8c3b0a145a 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -576,6 +576,10 @@ static void ep0_txstate(struct musb *musb) } else request = NULL; + /* send it out, triggering a "txpktrdy cleared" irq */ + musb_ep_select(musb->mregs, 0); + musb_writew(regs, MUSB_CSR0, csr); + /* report completions as soon as the fifo's loaded; there's no * win in waiting till this last packet gets acked. (other than * very precise fault reporting, needed by USB TMC; possible with @@ -588,10 +592,6 @@ static void ep0_txstate(struct musb *musb) return; musb->ackpend = 0; } - - /* send it out, triggering a "txpktrdy cleared" irq */ - musb_ep_select(musb->mregs, 0); - musb_writew(regs, MUSB_CSR0, csr); } /* diff --git a/drivers/video/Makefile b/drivers/video/Makefile index c527029241..945f35dc5d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 853303b5e5..bb4d7d8c14 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -128,12 +128,12 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(®s->lcdc_lcdcfg1, value); - value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); - value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); lcdc_writel(®s->lcdc_lcdcfg2, value); - value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); - value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); lcdc_writel(®s->lcdc_lcdcfg3, value); /* Display size */ diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c new file mode 100644 index 0000000000..ef5767baed --- /dev/null +++ b/drivers/video/imx25lcdc.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * imx25lcdc.c - Graphic interface for i.MX25 lcd controller + */ + +#include <common.h> + +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice imx25fb; + +void *video_hw_init(void) +{ + struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + GraphicDevice *pGD = &imx25fb; + char *s; + u32 *videomem; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_16BIT_565RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + videomem = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) { + struct ctfb_res_modes var_mode; + u32 lsr, lpcr, lhcr, lvcr; + unsigned long div; + int bpp; + + /* Disable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1); + + bpp = video_get_params(&var_mode, s); + + if (bpp == 0) { + var_mode.xres = 320; + var_mode.yres = 240; + var_mode.pixclock = 154000; + var_mode.left_margin = 68; + var_mode.right_margin = 20; + var_mode.upper_margin = 4; + var_mode.lower_margin = 18; + var_mode.hsync_len = 40; + var_mode.vsync_len = 6; + var_mode.sync = 0; + var_mode.vmode = 0; + } + + /* Fill memory with white */ + memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); + + imx25fb.winSizeX = var_mode.xres; + imx25fb.winSizeY = var_mode.yres; + + /* LCD base clock is 66.6MHZ. We do calculations in kHz */ + div = 66000 / (1000000000L / var_mode.pixclock); + if (div > 63) + div = 63; + if (0 == div) + div = 1; + + lsr = ((var_mode.xres / 16) << 20) | + var_mode.yres; + lpcr = (1 << 31) | + (1 << 30) | + (5 << 25) | + (1 << 23) | + (1 << 22) | + (1 << 19) | + (1 << 7) | + div; + lhcr = (var_mode.right_margin << 0) | + (var_mode.left_margin << 8) | + (var_mode.hsync_len << 26); + + lvcr = (var_mode.lower_margin << 0) | + (var_mode.upper_margin << 8) | + (var_mode.vsync_len << 26); + + writel((uint32_t)videomem, &lcdc->lssar); + writel(lsr, &lcdc->lsr); + writel(var_mode.xres * 2 / 4, &lcdc->lvpwr); + writel(lpcr, &lcdc->lpcr); + writel(lhcr, &lcdc->lhcr); + writel(lvcr, &lcdc->lvcr); + writel(0x00040060, &lcdc->ldcr); + + writel(0xA90300, &lcdc->lpccr); + + /* Ensable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1); + } + + return pGD; +} diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index 3e21fb2306..f75d77064e 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -13,6 +13,7 @@ #include <common.h> #include <asm/errno.h> +#include <asm/global_data.h> #include <linux/string.h> #include <linux/list.h> #include <linux/fb.h> @@ -24,6 +25,8 @@ #include "mxcfb.h" #include "ipu_regs.h" +DECLARE_GLOBAL_DATA_PTR; + static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -415,6 +418,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; + gd->fb_base = fbi->fix.smem_start; + /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); |
