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-rw-r--r--drivers/gpio/mxc_gpio.c8
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/fsl_debug_server.c10
-rw-r--r--drivers/misc/fsl_devdis.c29
-rw-r--r--drivers/misc/mxc_ocotp.c152
-rw-r--r--drivers/misc/mxs_ocotp.c1
-rw-r--r--drivers/net/fec_mxc.c14
-rw-r--r--drivers/net/fm/init.c27
-rw-r--r--drivers/net/phy/vitesse.c11
-rw-r--r--drivers/net/tsec.c6
-rw-r--r--drivers/pci/pcie_layerscape.c9
-rw-r--r--drivers/power/pmic/Makefile1
-rw-r--r--drivers/power/pmic/pmic_pfuze3000.c32
-rw-r--r--drivers/rtc/ds3231.c10
-rw-r--r--drivers/serial/Kconfig4
-rw-r--r--drivers/video/lg4573.c3
-rw-r--r--drivers/video/mb862xx.c3
17 files changed, 284 insertions, 37 deletions
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 0c48320966..70fe5b6a4e 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,16 +40,18 @@ static unsigned long gpio_ports[] = {
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX7)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+ defined(CONFIG_MX7)
[4] = GPIO5_BASE_ADDR,
#ifndef CONFIG_MX6UL
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
#ifndef CONFIG_MX6UL
[6] = GPIO7_BASE_ADDR,
#endif
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5218b91c0b..8d0fc3c5cb 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
index 44cd9b9fd4..a592891f26 100644
--- a/drivers/misc/fsl_debug_server.c
+++ b/drivers/misc/fsl_debug_server.c
@@ -60,29 +60,29 @@ int debug_server_parse_firmware_fit_image(const void **raw_image_addr,
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
if (format != IMAGE_FORMAT_FIT) {
- printf("Error! Not a FIT image\n");
+ printf("Debug Server FW: Not a FIT image\n");
goto out_error;
}
if (!fit_check_format(fit_hdr)) {
- printf("Error! Bad FIT image format\n");
+ printf("Debug Server FW: Bad FIT image format\n");
goto out_error;
}
node_offset = fit_image_get_node(fit_hdr, uname);
if (node_offset < 0) {
- printf("Error! Can not find %s subimage\n", uname);
+ printf("Debug Server FW:Can not find %s subimage\n", uname);
goto out_error;
}
/* Verify Debug Server firmware image */
if (!fit_image_verify(fit_hdr, node_offset)) {
- printf("Error! Bad Debug Server firmware hash");
+ printf("Debug Server FW: Bad Debug Server firmware hash");
goto out_error;
}
if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) {
- printf("Error! Failed to get Debug Server fw description");
+ printf("Debug Server FW: Failed to get FW description");
goto out_error;
}
diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c
new file mode 100644
index 0000000000..996f45c281
--- /dev/null
+++ b/drivers/misc/fsl_devdis.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Author: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#include <asm/arch-ls102xa/config.h>
+#include <linux/compiler.h>
+#include <hwconfig.h>
+#include <fsl_devdis.h>
+
+void device_disable(const struct devdis_table *tbl, uint32_t num)
+{
+ int i;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ /*
+ * Extract hwconfig from environment and disable unused device.
+ */
+ for (i = 0; i < num; i++) {
+ if (hwconfig_sub("devdis", tbl[i].name))
+ setbits_be32(&gur->devdisr + tbl[i].offset,
+ tbl[i].mask);
+ }
+}
+
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index d92044eeda..65ff8158e5 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -25,8 +25,21 @@
#define BM_CTRL_ERROR 0x00000200
#define BM_CTRL_BUSY 0x00000100
#define BO_CTRL_ADDR 0
+#ifdef CONFIG_MX7
+#define BM_CTRL_ADDR 0x0000000f
+#define BM_CTRL_RELOAD 0x00000400
+#else
#define BM_CTRL_ADDR 0x0000007f
-
+#endif
+
+#ifdef CONFIG_MX7
+#define BO_TIMING_FSOURCE 12
+#define BM_TIMING_FSOURCE 0x0007f000
+#define BV_TIMING_FSOURCE_NS 1001
+#define BO_TIMING_PROG 0
+#define BM_TIMING_PROG 0x00000fff
+#define BV_TIMING_PROG_US 10
+#else
#define BO_TIMING_STROBE_READ 16
#define BM_TIMING_STROBE_READ 0x003f0000
#define BV_TIMING_STROBE_READ_NS 37
@@ -36,6 +49,7 @@
#define BO_TIMING_STROBE_PROG 0
#define BM_TIMING_STROBE_PROG 0x00000fff
#define BV_TIMING_STROBE_PROG_US 10
+#endif
#define BM_READ_CTRL_READ_FUSE 0x00000001
@@ -43,6 +57,68 @@
#define WRITE_POSTAMBLE_US 2
+#if defined(CONFIG_MX6) || defined(CONFIG_VF610)
+#define FUSE_BANK_SIZE 0x80
+#ifdef CONFIG_MX6SL
+#define FUSE_BANKS 8
+#else
+#define FUSE_BANKS 16
+#endif
+#elif defined CONFIG_MX7
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS 16
+#else
+#error "Unsupported architecture\n"
+#endif
+
+#if defined(CONFIG_MX6)
+#include <asm/arch/sys_proto.h>
+
+/*
+ * There is a hole in shadow registers address map of size 0x100
+ * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
+ * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
+ * we should account for this hole in address space.
+ *
+ * Similar hole exists between bank 14 and bank 15 of size
+ * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
+ * Note: iMX6SL has only 0-7 banks and there is no hole.
+ * Note: iMX6UL doesn't have this one.
+ *
+ * This function is to covert user input to physical bank index.
+ * Only needed when read fuse, because we use register offset, so
+ * need to calculate real register offset.
+ * When write, no need to consider hole, always use the bank/word
+ * index from fuse map.
+ */
+u32 fuse_bank_physical(int index)
+{
+ u32 phy_index;
+
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
+ phy_index = index;
+ } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ if (index >= 6)
+ phy_index = fuse_bank_physical(5) + (index - 6) + 3;
+ else
+ phy_index = index;
+ } else {
+ if (index >= 15)
+ phy_index = fuse_bank_physical(14) + (index - 15) + 2;
+ else if (index >= 6)
+ phy_index = fuse_bank_physical(5) + (index - 6) + 3;
+ else
+ phy_index = index;
+ }
+ return phy_index;
+}
+#else
+u32 fuse_bank_physical(int index)
+{
+ return index;
+}
+#endif
+
static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
while (readl(&regs->ctrl) & BM_CTRL_BUSY)
@@ -59,9 +135,9 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
{
*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- if (bank >= ARRAY_SIZE((*regs)->bank) ||
- word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
- !assert) {
+ if (bank >= FUSE_BANKS ||
+ word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+ !assert) {
printf("mxc_ocotp %s(): Invalid argument\n", caller);
return -EINVAL;
}
@@ -99,16 +175,38 @@ int fuse_read(u32 bank, u32 word, u32 *val)
{
struct ocotp_regs *regs;
int ret;
+ u32 phy_bank;
ret = prepare_read(&regs, bank, word, val, __func__);
if (ret)
return ret;
- *val = readl(&regs->bank[bank].fuse_regs[word << 2]);
+ phy_bank = fuse_bank_physical(bank);
+
+ *val = readl(&regs->bank[phy_bank].fuse_regs[word << 2]);
return finish_access(regs, __func__);
}
+#ifdef CONFIG_MX7
+static void set_timing(struct ocotp_regs *regs)
+{
+ u32 ipg_clk;
+ u32 fsource, prog;
+ u32 timing;
+
+ ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+ fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
+ + 1000000) + 1;
+ prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
+
+ timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
+
+ clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
+ timing);
+}
+#else
static void set_timing(struct ocotp_regs *regs)
{
u32 ipg_clk;
@@ -130,12 +228,17 @@ static void set_timing(struct ocotp_regs *regs)
clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
BM_TIMING_STROBE_PROG, timing);
}
+#endif
static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
int write)
{
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+#ifdef CONFIG_MX7
+ u32 addr = bank;
+#else
u32 addr = bank << 3 | word;
+#endif
set_timing(regs);
clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
@@ -155,7 +258,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
setup_direct_access(regs, bank, word, false);
writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
wait_busy(regs, 1);
+#ifdef CONFIG_MX7
+ *val = readl((&regs->read_fuse_data0) + (word << 2));
+#else
*val = readl(&regs->read_fuse_data);
+#endif
return finish_access(regs, __func__);
}
@@ -176,8 +283,38 @@ int fuse_prog(u32 bank, u32 word, u32 val)
return ret;
setup_direct_access(regs, bank, word, true);
+#ifdef CONFIG_MX7
+ switch (word) {
+ case 0:
+ writel(0, &regs->data1);
+ writel(0, &regs->data2);
+ writel(0, &regs->data3);
+ writel(val, &regs->data0);
+ break;
+ case 1:
+ writel(val, &regs->data1);
+ writel(0, &regs->data2);
+ writel(0, &regs->data3);
+ writel(0, &regs->data0);
+ break;
+ case 2:
+ writel(0, &regs->data1);
+ writel(val, &regs->data2);
+ writel(0, &regs->data3);
+ writel(0, &regs->data0);
+ break;
+ case 3:
+ writel(0, &regs->data1);
+ writel(0, &regs->data2);
+ writel(val, &regs->data3);
+ writel(0, &regs->data0);
+ break;
+ }
+ wait_busy(regs, BV_TIMING_PROG_US);
+#else
writel(val, &regs->data);
wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+#endif
udelay(WRITE_POSTAMBLE_US);
return finish_access(regs, __func__);
@@ -187,12 +324,15 @@ int fuse_override(u32 bank, u32 word, u32 val)
{
struct ocotp_regs *regs;
int ret;
+ u32 phy_bank;
ret = prepare_write(&regs, bank, word, __func__);
if (ret)
return ret;
- writel(val, &regs->bank[bank].fuse_regs[word << 2]);
+ phy_bank = fuse_bank_physical(bank);
+
+ writel(val, &regs->bank[phy_bank].fuse_regs[word << 2]);
return finish_access(regs, __func__);
}
diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
index 6f0a1d3e6d..6c0d247ed2 100644
--- a/drivers/misc/mxs_ocotp.c
+++ b/drivers/misc/mxs_ocotp.c
@@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
/* Return the original HCLK clock speed. */
*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
*val &= CLKCTRL_HBUS_DIV_MASK;
+ *val >>= CLKCTRL_HBUS_DIV_OFFSET;
/* Scale the HCLK to 454/19 = 23.9 MHz . */
scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index c5dcbbbced..bff5fd1119 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -17,6 +17,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/sys_proto.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/compiler.h>
@@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
writel(0x00000000, &fec->eth->gaddr2);
- /* clear MIB RAM */
- for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
- writel(0, i);
+ /* Do not access reserved register for i.MX6UL */
+ if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ /* clear MIB RAM */
+ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
+ writel(0, i);
- /* FIFO receive start register */
- writel(0x520, &fec->eth->r_fstart);
+ /* FIFO receive start register */
+ writel(0x520, &fec->eth->r_fstart);
+ }
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 9a8a007861..b3ff4c50db 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <errno.h>
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
@@ -230,7 +231,7 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
__attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
-static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
+int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
int off;
uint32_t ph;
@@ -239,11 +240,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
+ if (off == -FDT_ERR_NOTFOUND)
+ return -EINVAL;
if (info->enabled) {
fdt_fixup_phy_connection(blob, off, info->enet_if);
board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
- return ;
+ return 0;
}
#ifdef CONFIG_SYS_FMAN_V3
@@ -281,7 +284,7 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
#endif
)
- return;
+ return 0;
#endif
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
@@ -294,6 +297,8 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
+
+ return 0;
}
void fdt_fixup_fman_ethernet(void *blob)
@@ -305,10 +310,18 @@ void fdt_fixup_fman_ethernet(void *blob)
ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
#else
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- if (fm_info[i].type == FM_ETH_1G_E)
- ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
- else
- ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
+ /* Try the new compatible first.
+ * If the node is missing, try the old.
+ */
+ if (fm_info[i].type == FM_ETH_1G_E) {
+ if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"))
+ ft_fixup_port(blob, &fm_info[i],
+ "fsl,fman-1g-mac");
+ } else {
+ if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
+ ft_fixup_port(blob, &fm_info[i],
+ "fsl,fman-10g-mac");
+ }
}
#endif
}
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 20a67466a7..941d0760b5 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -347,6 +347,16 @@ static struct phy_driver VSC8514_driver = {
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8584_driver = {
+ .name = "Vitesse VSC8584",
+ .uid = 0x707c0,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8574_config,
+ .startup = &vitesse_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver VSC8601_driver = {
.name = "Vitesse VSC8601",
.uid = 0x70420,
@@ -417,6 +427,7 @@ int phy_vitesse_init(void)
phy_register(&VSC8211_driver);
phy_register(&VSC8221_driver);
phy_register(&VSC8574_driver);
+ phy_register(&VSC8584_driver);
phy_register(&VSC8514_driver);
phy_register(&VSC8662_driver);
phy_register(&VSC8664_driver);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 42d037471f..4bdc188c8f 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -271,9 +271,6 @@ void redundant_init(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
- setbits_be32(&regs->dmactrl, DMACTRL_LE);
-#endif
do {
uint16_t status;
@@ -370,9 +367,6 @@ static void startup_tsec(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
-#ifdef CONFIG_LS102XA
- setbits_be32(&regs->dmactrl, DMACTRL_LE);
-#endif
}
/* This returns the status bits of the device. The return value
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 95cfe8c16f..2f24a6a39b 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -689,6 +689,7 @@ void fdt_fixup_smmu_pcie(void *blob)
{
int count;
u32 stream_ids[MAX_STREAM_IDS];
+ u32 ctlr_streamid = 0x300;
#ifdef CONFIG_PCIE1
/* PEX1 stream ID fixup */
@@ -696,6 +697,8 @@ void fdt_fixup_smmu_pcie(void *blob)
alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE2
@@ -704,6 +707,8 @@ void fdt_fixup_smmu_pcie(void *blob)
alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE3
@@ -712,6 +717,8 @@ void fdt_fixup_smmu_pcie(void *blob)
alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
+ &ctlr_streamid, 1);
#endif
#ifdef CONFIG_PCIE4
@@ -720,6 +727,8 @@ void fdt_fixup_smmu_pcie(void *blob)
alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
MAX_STREAM_IDS);
pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
+ append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
+ &ctlr_streamid, 1);
#endif
}
#endif
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 8f6463e127..00fde71b2c 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c
new file mode 100644
index 0000000000..ac807a801f
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze3000.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+
+int power_pfuze3000_init(unsigned char bus)
+{
+ static const char name[] = "PFUZE3000";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index c84bbc647f..e5e1be134c 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c
@@ -49,6 +49,8 @@
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
+#define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */
+#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */
static uchar rtc_read (uchar reg);
@@ -141,6 +143,14 @@ void rtc_reset (void)
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
}
+/*
+ * Enable 32KHz output
+ */
+void rtc_enable_32khz_output(void)
+{
+ rtc_write(RTC_STAT_REG_ADDR,
+ RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
+}
/*
* Helper functions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7ddda9f205..ccb80d2d1d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -120,7 +120,7 @@ config ROCKCHIP_SERIAL
config SANDBOX_SERIAL
bool "Sandbox UART support"
- depends on SANDBOX && DM
+ depends on SANDBOX
help
Select this to enable a seral UART for sandbox. This is required to
operate correctly, otherwise you will see no serial output from
@@ -140,7 +140,7 @@ config SANDBOX_SERIAL
config UNIPHIER_SERIAL
bool "Support for UniPhier on-chip UART"
- depends on ARCH_UNIPHIER && DM_SERIAL
+ depends on ARCH_UNIPHIER
help
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c
index 43670fc320..11fef279a9 100644
--- a/drivers/video/lg4573.c
+++ b/drivers/video/lg4573.c
@@ -220,7 +220,8 @@ err_claim_bus:
static int do_lgset(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0);
+ lg4573_spi_startup(CONFIG_LG4573_BUS, CONFIG_LG4573_CS, 10000000,
+ SPI_MODE_0);
return 0;
}
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 1c74e97c5e..868c51254d 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -419,8 +419,7 @@ void *video_hw_init (void)
board_disp_init ();
#endif
-#if (defined(CONFIG_LWMON5) || \
- defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
+#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Lamp on */
board_backlight_switch (1);
#endif
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