diff options
Diffstat (limited to 'drivers')
65 files changed, 2053 insertions, 1028 deletions
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index f0d611007a..75d182d27f 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -1,6 +1,5 @@ config DM bool "Enable Driver Model" - depends on !SPL_BUILD help This config option enables Driver Model. This brings in the core support, including scanning of platform data on start-up. If @@ -22,31 +21,28 @@ config SPL_DM config DM_WARN bool "Enable warnings in driver model" + depends on DM + default y help The dm_warn() function can use up quite a bit of space for its strings. By default this is disabled for SPL builds to save space. This will cause dm_warn() to be compiled out - it will do nothing when called. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD config DM_DEVICE_REMOVE bool "Support device removal" + depends on DM + default y help We can save some code space by dropping support for removing a device. This is not normally required in SPL, so by default this option is disabled for SPL. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD config DM_STDIO bool "Support stdio registration" + depends on DM + default y help Normally serial drivers register with stdio so that they can be used as normal output devices. In SPL we don't normally use stdio, so we can omit this feature. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index c0cf64229e..4aa91e4393 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -8,5 +8,5 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB)$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 504f2b07d0..18e2ec8d26 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -12,11 +12,18 @@ #ifndef DESC_H #define DESC_H +#define KEY_BLOB_SIZE 32 +#define MAC_SIZE 16 + /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ #define MAX_CAAM_DESCSIZE 64 +/* Size of DEK Blob descriptor, inclusive of header */ +#define DEK_BLOB_DESCSIZE 9 + /* Block size of any entity covered/uncovered with a KEK/TKEK */ #define KEK_BLOCKSIZE 16 + /* * Supported descriptor command types as they show up * inside a descriptor command word. @@ -273,6 +280,13 @@ #define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) /* + * AAD Definitions + */ +#define AES_KEY_SHIFT 8 +#define LD_CCM_MODE 0x66 +#define KEY_AES_SRC (0x55 << AES_KEY_SHIFT) + +/* * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE * Command Constructs */ @@ -418,6 +432,7 @@ #define OP_PCLID_MASK (0xff << 16) /* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_SECMEM 0x08 #define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) #define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) #define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index bc0107521c..8b25921272 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -7,11 +7,13 @@ #include <common.h> #include <malloc.h> +#include <fsl_sec.h> +#include <asm-generic/errno.h> #include "jobdesc.h" #include "desc.h" #include "jr.h" -int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { int ret, i = 0; u32 *desc; @@ -36,7 +38,7 @@ int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) return ret; } -int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { int ret, i = 0; u32 *desc; @@ -59,3 +61,53 @@ int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) free(desc); return ret; } + +#ifdef CONFIG_CMD_DEKBLOB +int blob_dek(const u8 *src, u8 *dst, u8 len) +{ + int ret, size, i = 0; + u32 *desc; + + int out_sz = WRP_HDR_SIZE + len + KEY_BLOB_SIZE + MAC_SIZE; + + puts("\nEncapsulating provided DEK to form blob\n"); + desc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * DEK_BLOB_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + ret = inline_cnstr_jobdesc_blob_dek(desc, src, dst, len); + if (ret) { + debug("Error in Job Descriptor Construction: %d\n", ret); + } else { + size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + + ret = run_descriptor_jr(desc); + } + + if (ret) { + debug("Error in Encapsulation %d\n", ret); + goto err; + } + + size = roundup(out_sz, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst+size); + + puts("DEK Blob\n"); + for (i = 0; i < out_sz; i++) + printf("%02X", ((uint8_t *)dst)[i]); + printf("\n"); + +err: + free(desc); + return ret; +} +#endif diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index d77f2573d0..c298404f25 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -10,6 +10,9 @@ #include "jobdesc.h" #include "desc.h" #include "jr.h" +#include "fsl_hash.h" +#include <hw_sha.h> +#include <asm-generic/errno.h> #define CRYPTO_MAX_ALG_NAME 80 #define SHA1_DIGEST_SIZE 20 @@ -39,6 +42,122 @@ static struct caam_hash_template driver_hash[] = { }, }; +static enum caam_hash_algos get_hash_type(struct hash_algo *algo) +{ + if (!strcmp(algo->name, driver_hash[SHA1].name)) + return SHA1; + else + return SHA256; +} + +/* Create the context for progressive hashing using h/w acceleration. + * + * @ctxp: Pointer to the pointer of the context for hashing + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -ENOMEM on error + */ +static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo) +{ + *ctxp = calloc(1, sizeof(struct sha_ctx)); + if (*ctxp == NULL) { + debug("Cannot allocate memory for context\n"); + return -ENOMEM; + } + return 0; +} + +/* + * Update sg table for progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * We support at most 32 Scatter/Gather Entries. + * + * @hash_ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_update(void *hash_ctx, const void *buf, + unsigned int size, int is_last, + enum caam_hash_algos caam_algo) +{ + uint32_t final = 0; + dma_addr_t addr = virt_to_phys((void *)buf); + struct sha_ctx *ctx = hash_ctx; + + if (ctx->sg_num >= MAX_SG_32) { + free(ctx); + return -EINVAL; + } + +#ifdef CONFIG_PHYS_64BIT + ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; +#else + ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; +#endif + ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + + sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, + (size & SG_ENTRY_LENGTH_MASK)); + + ctx->sg_num++; + + if (is_last) { + final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) | + SG_ENTRY_FINAL_BIT; + sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final); + } + + return 0; +} + +/* + * Perform progressive hashing on the given buffer and copy hash at + * destination buffer + * + * The context is freed after completion of hash operation. + * + * @hash_ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_finish(void *hash_ctx, void *dest_buf, + int size, enum caam_hash_algos caam_algo) +{ + uint32_t len = 0; + struct sha_ctx *ctx = hash_ctx; + int i = 0, ret = 0; + + if (size < driver_hash[caam_algo].digestsize) { + free(ctx); + return -EINVAL; + } + + for (i = 0; i < ctx->sg_num; i++) + len += (sec_in32(&ctx->sg_tbl[i].len_flag) & + SG_ENTRY_LENGTH_MASK); + + inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, + ctx->hash, + driver_hash[caam_algo].alg_type, + driver_hash[caam_algo].digestsize, + 1); + + ret = run_descriptor_jr(ctx->sha_desc); + + if (ret) + debug("Error %x\n", ret); + else + memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); + + free(ctx); + return ret; +} + int caam_hash(const unsigned char *pbuf, unsigned int buf_len, unsigned char *pout, enum caam_hash_algos algo) { @@ -48,7 +167,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, @@ -75,3 +194,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (caam_hash(pbuf, buf_len, pout, SHA1)) printf("CAAM was not setup properly or it is faulty\n"); } + +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + return caam_hash_init(ctxp, get_hash_type(algo)); +} + +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo)); +} + +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo)); +} diff --git a/drivers/crypto/fsl/fsl_hash.h b/drivers/crypto/fsl/fsl_hash.h new file mode 100644 index 0000000000..f5be651d7a --- /dev/null +++ b/drivers/crypto/fsl/fsl_hash.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef _SHA_H +#define _SHA_H + +#include <fsl_sec.h> +#include <hash.h> +#include "jr.h" + +/* We support at most 32 Scatter/Gather Entries.*/ +#define MAX_SG_32 32 + +/* + * Hash context contains the following fields + * @sha_desc: Sha Descriptor + * @sg_num: number of entries in sg table + * @len: total length of buffer + * @sg_tbl: sg entry table + * @hash: index to the hash calculated + */ +struct sha_ctx { + uint32_t sha_desc[64]; + uint32_t sg_num; + uint32_t len; + struct sg_entry sg_tbl[MAX_SG_32]; + u8 hash[HASH_MAX_DIGEST_SIZE]; +}; + +#endif diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index cc0dcede7b..5695bef6fd 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -9,12 +9,157 @@ */ #include <common.h> +#include <fsl_sec.h> #include "desc_constr.h" #include "jobdesc.h" #include "rsa_caam.h" -#define KEY_BLOB_SIZE 32 -#define MAC_SIZE 16 +#ifdef CONFIG_MX6 +/*! + * Secure memory run command + * + * @param sec_mem_cmd Secure memory command register + * @return cmd_status Secure memory command status register + */ +uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) +{ + uint32_t temp_reg; + + sec_out32(CAAM_SMCJR0, sec_mem_cmd); + + do { + temp_reg = sec_in32(CAAM_SMCSJR0); + } while (temp_reg & CMD_COMPLETE); + + return temp_reg; +} + +/*! + * CAAM page allocation: + * Allocates a partition from secure memory, with the id + * equal to partion_num. This will de-allocate the page + * if it is already allocated. The partition will have + * full access permissions. The permissions are set before, + * running a job descriptor. A memory page of secure RAM + * is allocated for the partition. + * + * @param page Number of the page to allocate. + * @param partition Number of the partition to allocate. + * @return 0 on success, ERROR_IN_PAGE_ALLOC otherwise + */ +int caam_page_alloc(uint8_t page_num, uint8_t partition_num) +{ + uint32_t temp_reg; + + /* + * De-Allocate partition_num if already allocated to ARM core + */ + if (sec_in32(CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) { + temp_reg = secmem_set_cmd(PARTITION(partition_num) | + CMD_PART_DEALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: De-allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + } + + /* set the access rights to allow full access */ + sec_out32(CAAM_SMAG1JR0(partition_num), 0xF); + sec_out32(CAAM_SMAG2JR0(partition_num), 0xF); + sec_out32(CAAM_SMAPJR0(partition_num), 0xFF); + + /* Now need to allocate partition_num of secure RAM. */ + /* De-Allocate page_num by starting with a page inquiry command */ + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY); + + /* if the page is owned, de-allocate it */ + if ((temp_reg & SMCSJR_PO) == PAGE_OWNED) { + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_PAGE_DEALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: Allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + } + + /* Allocate page_num to partition_num */ + temp_reg = secmem_set_cmd(PAGE(page_num) | PARTITION(partition_num) + | CMD_PAGE_ALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: Allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + /* page inquiry command to ensure that the page was allocated */ + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY); + + /* if the page is not owned => problem */ + if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) { + printf("Allocation of page %d in partition %d failed 0x%X\n", + temp_reg, page_num, partition_num); + + return ERROR_IN_PAGE_ALLOC; + } + + return 0; +} + +int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, + uint8_t *dek_blob, uint32_t in_sz) +{ + uint32_t ret = 0; + u32 aad_w1, aad_w2; + /* output blob will have 32 bytes key blob in beginning and + * 16 byte HMAC identifier at end of data blob */ + uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE; + /* Setting HDR for blob */ + uint8_t wrapped_key_hdr[8] = {HDR_TAG, 0x00, WRP_HDR_SIZE + out_sz, + HDR_PAR, HAB_MOD, HAB_ALG, in_sz, HAB_FLG}; + + /* initialize the blob array */ + memset(dek_blob, 0, out_sz + 8); + /* Copy the header into the DEK blob buffer */ + memcpy(dek_blob, wrapped_key_hdr, sizeof(wrapped_key_hdr)); + + /* allocating secure memory */ + ret = caam_page_alloc(PAGE_1, PARTITION_1); + if (ret) + return ret; + + /* Write DEK to secure memory */ + memcpy((uint32_t *)SEC_MEM_PAGE1, (uint32_t *)plain_txt, in_sz); + + unsigned long start = (unsigned long)SEC_MEM_PAGE1 & + ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* Now configure the access rights of the partition */ + sec_out32(CAAM_SMAG1JR0(PARTITION_1), KS_G1); /* set group 1 */ + sec_out32(CAAM_SMAG2JR0(PARTITION_1), 0); /* clear group 2 */ + sec_out32(CAAM_SMAPJR0(PARTITION_1), PERM); /* set perm & locks */ + + /* construct aad for AES */ + aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE; + aad_w2 = 0x0; + + init_job_desc(desc, 0); + + append_cmd(desc, CMD_LOAD | CLASS_2 | KEY_IMM | KEY_ENC | + (0x0c << LDST_OFFSET_SHIFT) | 0x08); + + append_u32(desc, aad_w1); + + append_u32(desc, aad_w2); + + append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + + append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | + OP_PCLID_SECMEM); + + return ret; +} +#endif void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index 84b3edd6e2..112404c74d 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -14,6 +14,20 @@ #define KEY_IDNFR_SZ_BYTES 16 +#ifdef CONFIG_CMD_DEKBLOB +/* inline_cnstr_jobdesc_blob_dek: + * Intializes and constructs the job descriptor for DEK encapsulation + * using the given parameters. + * @desc: reference to the job descriptor + * @plain_txt: reference to the DEK + * @enc_blob: reference where to store the blob + * @in_sz: size in bytes of the DEK + * @return: 0 on success, ECONSTRJDESC otherwise + */ +int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, + uint8_t *enc_blob, uint32_t in_sz); +#endif + void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, u32 alg_type, uint32_t alg_size, int sg_tbl); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f9d4938834..f99d59480c 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -90,11 +90,13 @@ static int jr_init(void) jr.liodn = DEFAULT_JR_LIODN; #endif jr.size = JR_SIZE; - jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t)); + jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(dma_addr_t)); if (!jr.input_ring) return -1; jr.output_ring = - (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring)); + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(struct op_ring)); if (!jr.output_ring) return -1; @@ -163,13 +165,23 @@ static int jr_enqueue(uint32_t *desc_addr, CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) return -1; - jr.input_ring[head] = desc_phys_addr; jr.info[head].desc_phys_addr = desc_phys_addr; jr.info[head].desc_addr = (uint32_t)desc_addr; jr.info[head].callback = (void *)callback; jr.info[head].arg = arg; jr.info[head].op_done = 0; + unsigned long start = (unsigned long)&jr.info[head] & + ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(struct jr_info), + ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + jr.input_ring[head] = desc_phys_addr; + start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + jr.head = (head + 1) & (jr.size - 1); sec_out32(®s->irja, 1); @@ -187,6 +199,13 @@ static int jr_dequeue(void) void *arg = NULL; while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { + unsigned long start = (unsigned long)jr.output_ring & + ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + + sizeof(struct op_ring)*JR_SIZE, + ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + found = 0; dma_addr_t op_desc = jr.output_ring[jr.tail].desc; @@ -333,13 +352,17 @@ static int instantiate_rng(void) memset(&op, 0, sizeof(struct result)); - desc = malloc(sizeof(int) * 6); + desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6); if (!desc) { printf("cannot allocate RNG init descriptor memory\n"); return -1; } inline_cnstr_jobdesc_rng_instantiation(desc); + int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + ret = run_descriptor_jr(desc); if (ret) diff --git a/drivers/crypto/rsa_mod_exp/Makefile b/drivers/crypto/rsa_mod_exp/Makefile index 915b751dbe..ae3dcf3d7a 100644 --- a/drivers/crypto/rsa_mod_exp/Makefile +++ b/drivers/crypto/rsa_mod_exp/Makefile @@ -4,4 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o +obj-$(CONFIG_RSA) += mod_exp_uclass.o +obj-$(CONFIG_RSA_SOFTWARE_EXP) += mod_exp_sw.o diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index c139da6da9..7160da4ec8 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -222,7 +222,7 @@ step2: bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; + (get_ddr_freq(ctrl_num) >> 20)) << 1; total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 03d7ff17dd..690e73dacf 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -17,8 +17,6 @@ #include <fsl_immap.h> #include <asm/io.h> -unsigned int picos_to_mclk(unsigned int picos); - /* * Determine Rtt value. * @@ -78,10 +76,11 @@ static inline int fsl_ddr_get_rtt(void) * 16 for <= 2933MT/s * 18 for higher */ -static inline unsigned int compute_cas_write_latency(void) +static inline unsigned int compute_cas_write_latency( + const unsigned int ctrl_num) { unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (mclk_ps >= 1250) cwl = 9; else if (mclk_ps >= 1070) @@ -111,10 +110,11 @@ static inline unsigned int compute_cas_write_latency(void) * 11 if 0.935ns > tCK >= 0.833ns * 12 if 0.833ns > tCK >= 0.75ns */ -static inline unsigned int compute_cas_write_latency(void) +static inline unsigned int compute_cas_write_latency( + const unsigned int ctrl_num) { unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (mclk_ps >= 2500) cwl = 5; @@ -287,7 +287,8 @@ static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) * Avoid writing for DDR I. The new PQ38 DDR controller * dreams up non-zero default values to be backwards compatible. */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, +static void set_timing_cfg_0(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const dimm_params_t *dimm_params) { @@ -306,7 +307,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #endif #ifdef CONFIG_SYS_FSL_DDR4 @@ -314,15 +315,15 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ trwt_mclk = 2; twrt_mclk = 1; - act_pd_exit_mclk = picos_to_mclk(txp); + act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); pre_pd_exit_mclk = act_pd_exit_mclk; /* * MRS_CYC = max(tMRD, tMOD) * tMRD = 8nCK, tMOD = max(24nCK, 15ns) */ - tmrd_mclk = max(24U, picos_to_mclk(15000)); + tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); #elif defined(CONFIG_SYS_FSL_DDR3) - unsigned int data_rate = get_ddr_freq(0); + unsigned int data_rate = get_ddr_freq(ctrl_num); int txp; unsigned int ip_rev; int odt_overlap; @@ -344,7 +345,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tMRD = 4nCK (8nCK for RDIMM) * tMOD = max(12nCK, 15ns) */ - tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000)); + tmrd_mclk = max((unsigned int)12, + picos_to_mclk(ctrl_num, 15000)); } else { /* * MRS_CYC = tMRD @@ -388,7 +390,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, taxpd_mclk = 1; } else { /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(txp); + act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); /* Mode register MR0[A12] is '1' - fast exit */ pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 1; @@ -424,11 +426,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) +static void set_timing_cfg_3(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) { /* Extended precharge to activate interval (tRP) */ unsigned int ext_pretoact = 0; @@ -447,18 +450,18 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, /* Control Adjust */ unsigned int cntl_adj = 0; - ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; + ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; + ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; + ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; ext_caslat = (2 * cas_latency - 1) >> 4; ext_add_lat = additive_latency >> 4; #ifdef CONFIG_SYS_FSL_DDR4 - ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4; + ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; #else - ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; + ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ #endif - ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + + ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; ddr->timing_cfg_3 = (0 @@ -475,10 +478,11 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) +static void set_timing_cfg_1(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) { /* Precharge-to-activate interval (tRP) */ unsigned char pretoact_mclk; @@ -510,9 +514,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; #endif - pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); - acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); + pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); + acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); + acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); /* * Translate CAS Latency to a DDR controller field value: @@ -547,19 +551,19 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, #endif #ifdef CONFIG_SYS_FSL_DDR4 - refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U); - wrtord_mclk = max(2U, picos_to_mclk(2500)); + refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; + wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); + acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); + wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #else - refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); - wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); + refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; + wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); + acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); + wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else @@ -602,11 +606,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) +static void set_timing_cfg_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) { /* Additive latency */ unsigned char add_lat_mclk; @@ -623,7 +628,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* Window for four activates (tFAW) */ unsigned short four_act; #ifdef CONFIG_SYS_FSL_DDR3 - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #endif /* FIXME add check that this must be less than acttorw_mclk */ @@ -641,13 +646,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR2) wr_lat = cas_latency - 1; #else - wr_lat = compute_cas_write_latency(); + wr_lat = compute_cas_write_latency(ctrl_num); #endif #ifdef CONFIG_SYS_FSL_DDR4 - rd_to_pre = picos_to_mclk(7500); + rd_to_pre = picos_to_mclk(ctrl_num, 7500); #else - rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); + rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); #endif /* * JEDEC has some min requirements for tRTP @@ -665,19 +670,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, wr_data_delay = popts->write_data_delay; #ifdef CONFIG_SYS_FSL_DDR4 cpo = 0; - cke_pls = max(3U, picos_to_mclk(5000)); + cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); #elif defined(CONFIG_SYS_FSL_DDR3) /* * cke pulse = max(3nCK, 7.5ns) for DDR3-800 * max(3nCK, 5.625ns) for DDR3-1066, 1333 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 */ - cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 : - (mclk_ps > 1245 ? 5625 : 5000))); + cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : + (mclk_ps > 1245 ? 5625 : 5000))); #else cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; #endif - four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); + four_act = picos_to_mclk(ctrl_num, + popts->tfaw_window_four_activates_ps); ddr->timing_cfg_2 = (0 | ((add_lat_mclk & 0xf) << 28) @@ -818,7 +824,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const unsigned int unq_mrs_en) { @@ -865,7 +872,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #endif #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) - slow = get_ddr_freq(0) < 1249000000; + slow = get_ddr_freq(ctrl_num) < 1249000000; #endif if (popts->registered_dimm_en) { @@ -915,7 +922,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -926,10 +934,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, unsigned int wr_crc = 0; /* Disable */ unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int cwl = compute_cas_write_latency() - 9; + unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; unsigned int mpr = 0; /* serial */ unsigned int wc_lat; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; @@ -1002,7 +1010,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, } #elif defined(CONFIG_SYS_FSL_DDR3) /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1013,7 +1022,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; + unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; unsigned int pasr = 0; /* partial array self refresh disable */ if (popts->rtt_override) @@ -1077,7 +1086,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, #else /* for DDR2 and DDR1 */ /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1144,7 +1154,8 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ -static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1152,7 +1163,7 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, int i; unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ - unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); esdmode6 = ((tccdl_min - 4) & 0x7) << 10; @@ -1196,14 +1207,15 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, #endif /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) +static void set_ddr_sdram_interval(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) { unsigned int refint; /* Refresh interval */ unsigned int bstopre; /* Precharge interval */ - refint = picos_to_mclk(common_dimm->refresh_rate_ps); + refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); bstopre = popts->bstopre; @@ -1217,7 +1229,8 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1292,7 +1305,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, * 1=fast exit DLL on (tXP) */ - wr_mclk = picos_to_mclk(common_dimm->twr_ps); + wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); if (wr_mclk <= 24) { wr = wr_table[wr_mclk - 10]; } else { @@ -1387,7 +1400,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR3) /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1466,7 +1480,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ dll_on = 1; - wr_mclk = picos_to_mclk(common_dimm->twr_ps); + wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); if (wr_mclk <= 16) { wr = wr_table[wr_mclk - 5]; } else { @@ -1582,7 +1596,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #else /* !CONFIG_SYS_FSL_DDR3 */ /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1654,7 +1669,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_SYS_FSL_DDR1) wr = 0; /* Historical */ #elif defined(CONFIG_SYS_FSL_DDR2) - wr = picos_to_mclk(common_dimm->twr_ps); + wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); #endif dll_res = 0; mode = 0; @@ -1842,15 +1857,16 @@ static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); } -static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm) +static void set_timing_cfg_7(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; - txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000)); - tcksre = max(5U, picos_to_mclk(10000)); - tcksrx = max(5U, picos_to_mclk(10000)); + txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); + tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); + tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); par_lat = 0; cs_to_cmd = 0; @@ -1883,14 +1899,15 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); } -static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, +static void set_timing_cfg_8(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency) { unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; unsigned int acttoact_bg, wrtord_bg, pre_all_rec; - unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + ((ddr->timing_cfg_2 & 0x00040000) >> 14); @@ -1911,11 +1928,11 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, wwt_bg = tccdl - 4; } else { rrt_bg = tccdl - 2; - wwt_bg = tccdl - 4; + wwt_bg = tccdl - 2; } - acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); - wrtord_bg = max(4U, picos_to_mclk(7500)); + acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); + wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); if (popts->otf_burst_chop_en) wrtord_bg += 2; @@ -2147,7 +2164,8 @@ check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) } unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, +compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, @@ -2319,14 +2337,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_eor(ddr, popts); #if !defined(CONFIG_SYS_FSL_DDR1) - set_timing_cfg_0(ddr, popts, dimm_params); + set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); #endif - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency, + set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, additive_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); + set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); + set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, + cas_latency, additive_latency); set_ddr_cdr1(ddr, popts); set_ddr_cdr2(ddr, popts); @@ -2338,15 +2356,15 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) ddr->debug[18] = popts->cswl_override; - set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); + set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); #ifdef CONFIG_SYS_FSL_DDR4 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); - set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); #endif - set_ddr_sdram_interval(ddr, popts, common_dimm); + set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); @@ -2356,8 +2374,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, #ifdef CONFIG_SYS_FSL_DDR4 set_ddr_sdram_cfg_3(ddr, popts); set_timing_cfg_6(ddr); - set_timing_cfg_7(ddr, common_dimm); - set_timing_cfg_8(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_7(ctrl_num, ddr, common_dimm); + set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); set_timing_cfg_9(ddr); set_ddr_dq_mapping(ddr, dimm_params); #endif @@ -2372,7 +2390,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, #ifdef CONFIG_SYS_FSL_DDR_EMU /* disble DDR training for emulator */ ddr->debug[2] = 0x00000400; - ddr->debug[4] = 0xff800000; + ddr->debug[4] = 0xff800800; + ddr->debug[5] = 0x08000800; + ddr->debug[6] = 0x08000800; + ddr->debug[7] = 0x08000800; + ddr->debug[8] = 0x08000800; #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004508 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index 7df27b90b7..7f1c3afcc4 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -228,10 +228,10 @@ compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) * * FIXME: use #define for the retvals */ -unsigned int -ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr1_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; @@ -311,16 +311,16 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); + pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency( + get_memory_clk_period_ps(ctrl_num)); /* Compute timing parameters */ pdimm->trcd_ps = spd->trcd * 250; pdimm->trp_ps = spd->trp * 250; pdimm->tras_ps = spd->tras * 1000; - pdimm->twr_ps = mclk_to_picos(3); - pdimm->twtr_ps = mclk_to_picos(1); + pdimm->twr_ps = mclk_to_picos(ctrl_num, 3); + pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1); pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); pdimm->trrd_ps = spd->trrd * 250; @@ -335,7 +335,7 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ + pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */ pdimm->tdqsq_max_ps = spd->tdqsq * 10; pdimm->tqhs_ps = spd->tqhs * 10; diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index d865df78a8..49cc1a07ff 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -211,10 +211,10 @@ compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) * * FIXME: use #define for the retvals */ -unsigned int -ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr2_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; @@ -310,8 +310,8 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); + pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( + get_memory_clk_period_ps(ctrl_num)); /* Compute timing parameters */ pdimm->trcd_ps = spd->trcd * 250; diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index a4b8c101f5..69177150ec 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -83,10 +83,10 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) * Writes the results to the dimm_params_t structure pointed by pdimm. * */ -unsigned int -ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr3_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; unsigned int mtb_ps; diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index aaddc8fa08..bbfb4ee417 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -119,10 +119,10 @@ compute_ranksize(const struct ddr4_spd_eeprom_s *spd) * Writes the results to the dimm_params_t structure pointed by pdimm. * */ -unsigned int -ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; int i; diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 4eef047343..d9fce7d2f3 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -32,24 +32,44 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) + u32 *eddrtqcr1; +#endif switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; +#endif break; #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; +#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; +#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; +#endif break; #endif default: @@ -60,6 +80,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_LS2085A + /* A008336 only applies to general DDR controllers */ + if ((ctrl_num == 0) || (ctrl_num == 1)) +#endif + ddr_out32(eddrtqcr1, 0x63b30002); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_LS2085A + /* A008514 only applies to DP-DDR controler */ + if (ctrl_num == 2) +#endif + ddr_out32(eddrtqcr1, 0x63b20002); +#endif if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor); @@ -253,7 +287,7 @@ step2: bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 2; + (get_ddr_freq(ctrl_num) >> 20)) << 2; total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 73db444615..b295344c4d 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -13,7 +13,8 @@ #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) static unsigned int -compute_cas_latency(const dimm_params_t *dimm_params, +compute_cas_latency(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) { @@ -22,7 +23,7 @@ compute_cas_latency(const dimm_params_t *dimm_params, unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #ifdef CONFIG_SYS_FSL_DDR3 const unsigned int taamax = 20000; #else @@ -72,12 +73,13 @@ compute_cas_latency(const dimm_params_t *dimm_params, } #else /* for DDR1 and DDR2 */ static unsigned int -compute_cas_latency(const dimm_params_t *dimm_params, +compute_cas_latency(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) { int i; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); unsigned int lowest_good_caslat; unsigned int not_ok; unsigned int temp1, temp2; @@ -212,7 +214,8 @@ compute_cas_latency(const dimm_params_t *dimm_params, * by dimm_params. */ unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, +compute_lowest_common_dimm_parameters(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, const unsigned int number_of_dimms) { @@ -442,7 +445,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, printf("ERROR: Mix different RDIMM detected!\n"); /* calculate cas latency for all DDR types */ - if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms)) + if (compute_cas_latency(ctrl_num, dimm_params, + outpdimm, number_of_dimms)) return 1; /* Determine if all DIMMs ECC capable. */ @@ -518,11 +522,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, #if defined(CONFIG_SYS_FSL_DDR2) if ((outpdimm->lowest_common_spd_caslat < 4) && - (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) { - additive_latency = picos_to_mclk(trcd_ps) - + (picos_to_mclk(ctrl_num, trcd_ps) > + outpdimm->lowest_common_spd_caslat)) { + additive_latency = picos_to_mclk(ctrl_num, trcd_ps) - outpdimm->lowest_common_spd_caslat; - if (mclk_to_picos(additive_latency) > trcd_ps) { - additive_latency = picos_to_mclk(trcd_ps); + if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { + additive_latency = picos_to_mclk(ctrl_num, trcd_ps); debug("setting additive_latency to %u because it was " " greater than tRCD_ps\n", additive_latency); } @@ -534,7 +539,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * * AL <= tRCD(min) */ - if (mclk_to_picos(additive_latency) > trcd_ps) { + if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { printf("Error: invalid additive latency exceeds tRCD(min).\n"); return 1; } diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6f291ebc03..b72b24290e 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -450,7 +450,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->spd_installed_dimms[i][j]); dimm_params_t *pdimm = &(pinfo->dimm_params[i][j]); - retval = compute_dimm_parameters(spd, pdimm, i); + retval = compute_dimm_parameters( + i, spd, pdimm, j); #ifdef CONFIG_SYS_DDR_RAW_TIMING if (!i && !j && retval) { printf("SPD error on controller %d! " @@ -507,10 +508,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, for (i = first_ctrl; i <= last_ctrl; i++) { debug("Computing lowest common DIMM" " parameters for memctl=%u\n", i); - compute_lowest_common_dimm_parameters( - pinfo->dimm_params[i], - &timing_params[i], - CONFIG_DIMM_SLOTS_PER_CTLR); + compute_lowest_common_dimm_parameters + (i, + pinfo->dimm_params[i], + &timing_params[i], + CONFIG_DIMM_SLOTS_PER_CTLR); } case STEP_GATHER_OPTS: @@ -562,12 +564,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, continue; } - compute_fsl_memctl_config_regs( - &pinfo->memctl_opts[i], - &ddr_reg[i], &timing_params[i], - pinfo->dimm_params[i], - dbw_capacity_adjust[i], - size_only); + compute_fsl_memctl_config_regs + (i, + &pinfo->memctl_opts[i], + &ddr_reg[i], &timing_params[i], + pinfo->dimm_params[i], + dbw_capacity_adjust[i], + size_only); } default: @@ -689,6 +692,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) } } +#ifdef CONFIG_FSL_DDR_SYNC_REFRESH + fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl); +#endif + #ifdef CONFIG_PPC /* program LAWs */ for (i = first_ctrl; i <= last_ctrl; i++) { diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 8f4d01ad85..6752d4d29e 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -426,7 +426,7 @@ step2: bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; + (get_ddr_freq(ctrl_num) >> 20)) << 1; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 timeout_save = timeout; #endif @@ -538,12 +538,14 @@ step2: case 1: out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); break; +#if CONFIG_CHIP_SELECTS_PER_CTRL > 2 case 2: out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); break; case 3: out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); break; +#endif } clrbits_be32(&ddr->sdram_cfg, 0x2); } diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 6d098d1fa2..5beb11b02b 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -732,7 +732,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, #endif /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); + debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num)); /* Pick a caslat override. */ popts->cas_latency_override = 0; @@ -785,7 +785,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, * FIXME: width, was considering looking at pdimm->primary_sdram_width */ #if defined(CONFIG_SYS_FSL_DDR1) - popts->tfaw_window_four_activates_ps = mclk_to_picos(1); + popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1); #elif defined(CONFIG_SYS_FSL_DDR2) /* @@ -1036,7 +1036,7 @@ done: if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; - ddr_freq = get_ddr_freq(0) / 1000000; + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if (popts->registered_dimm_en) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 58b519b403..664081b1b8 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -43,9 +43,9 @@ u32 fsl_ddr_get_version(void) * propagation, compute a suitably rounded mclk_ps to compute * a working memory controller configuration. */ -unsigned int get_memory_clk_period_ps(void) +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) { - unsigned int data_rate = get_ddr_freq(0); + unsigned int data_rate = get_ddr_freq(ctrl_num); unsigned int result; /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ @@ -59,10 +59,10 @@ unsigned int get_memory_clk_period_ps(void) } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -unsigned int picos_to_mclk(unsigned int picos) +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) { unsigned long long clks, clks_rem; - unsigned long data_rate = get_ddr_freq(0); + unsigned long data_rate = get_ddr_freq(ctrl_num); /* Short circuit for zero picos */ if (!picos) @@ -88,9 +88,9 @@ unsigned int picos_to_mclk(unsigned int picos) return (unsigned int) clks; } -unsigned int mclk_to_picos(unsigned int mclk) +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) { - return get_memory_clk_period_ps() * mclk; + return get_memory_clk_period_ps(ctrl_num) * mclk; } #ifdef CONFIG_PPC @@ -308,3 +308,58 @@ void board_add_ram_info(int use_default) { detail_board_ddr_info(); } + +#ifdef CONFIG_FSL_DDR_SYNC_REFRESH +#define DDRC_DEBUG20_INIT_DONE 0x80000000 +#define DDRC_DEBUG2_RF 0x00000040 +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl) +{ + unsigned int i; + u32 ddrc_debug20; + u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; + u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; + struct ccsr_ddr __iomem *ddr; + + for (i = first_ctrl; i <= last_ctrl; i++) { + switch (i) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl = %u\n", __func__, i); + return; + } + ddrc_debug20 = ddr_in32(&ddr->debug[19]); + ddrc_debug2_p[i] = &ddr->debug[1]; + while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { + /* keep polling until DDRC init is done */ + udelay(100); + ddrc_debug20 = ddr_in32(&ddr->debug[19]); + } + ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; + } + /* + * Sync refresh + * This is put together to make sure the refresh reqeusts are sent + * closely to each other. + */ + for (i = first_ctrl; i <= last_ctrl; i++) + ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); +} +#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index ad0a7e7c25..0560afa9ff 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -55,6 +55,9 @@ int dfu_init_env_entities(char *interface, char *devstr) char *env_bkp; int ret; +#ifdef CONFIG_SET_DFU_ALT_INFO + set_dfu_alt_info(interface, devstr); +#endif str_env = getenv("dfu_alt_info"); if (!str_env) { error("\"dfu_alt_info\" env variable not defined!\n"); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 62d72fe4c6..fd865e1121 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -16,8 +16,7 @@ #include <fat.h> #include <mmc.h> -static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) - dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; +static unsigned char *dfu_file_buf; static long dfu_file_buf_len; static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) @@ -211,7 +210,7 @@ int dfu_flush_medium_mmc(struct dfu_entity *dfu) if (dfu->layout != DFU_RAW_ADDR) { /* Do stuff here. */ - ret = mmc_file_op(DFU_OP_WRITE, dfu, &dfu_file_buf, + ret = mmc_file_op(DFU_OP_WRITE, dfu, dfu_file_buf, &dfu_file_buf_len); /* Now that we're done */ @@ -263,6 +262,14 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, return ret; } +void dfu_free_entity_mmc(struct dfu_entity *dfu) +{ + if (dfu_file_buf) { + free(dfu_file_buf); + dfu_file_buf = NULL; + } +} + /* * @param s Parameter string containing space-separated arguments: * 1st: @@ -370,6 +377,18 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s) dfu->write_medium = dfu_write_medium_mmc; dfu->flush_medium = dfu_flush_medium_mmc; dfu->inited = 0; + dfu->free_entity = dfu_free_entity_mmc; + + /* Check if file buffer is ready */ + if (!dfu_file_buf) { + dfu_file_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, + CONFIG_SYS_DFU_MAX_FILE_SIZE); + if (!dfu_file_buf) { + error("Could not memalign 0x%x bytes", + CONFIG_SYS_DFU_MAX_FILE_SIZE); + return -ENOMEM; + } + } return 0; } diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aa11f15423..fe9a3b2396 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,10 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DM_GPIO) += gpio-uclass.o endif +/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */ +ifdef CONFIG_TEGRA_GPIO +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 43928b8812..f870cdbddf 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -132,21 +132,6 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int tegra_spl_gpio_direction_output(int gpio, int value) -{ - /* Configure as a GPIO */ - set_config(gpio, 1); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - /* Configure GPIO direction as output. */ - set_direction(gpio, 1); - - return 0; -} - /* * Generic_GPIO primitives. */ @@ -338,12 +323,19 @@ static int gpio_tegra_bind(struct udevice *parent) int bank_count; int bank; int ret; - int len; /* If this is a child device, there is nothing to do here */ if (plat) return 0; + /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +#ifdef CONFIG_SPL_BUILD + ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + bank_count = TEGRA_GPIO_BANKS; +#else + { + int len; + /* * This driver does not make use of interrupts, other than to figure * out the number of GPIO banks @@ -353,6 +345,8 @@ static int gpio_tegra_bind(struct udevice *parent) bank_count = len / 3 / sizeof(u32); ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, parent->of_offset, "reg"); + } +#endif for (bank = 0; bank < bank_count; bank++) { int port; @@ -388,4 +382,5 @@ U_BOOT_DRIVER(gpio_tegra) = { .probe = gpio_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_port_info), .ops = &gpio_tegra_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index a6991bf875..b890806a44 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -230,6 +230,8 @@ static int i2c_bind_driver(struct udevice *bus, uint chip_addr, uint offset_len, snprintf(name, sizeof(name), "generic_%x", chip_addr); str = strdup(name); + if (!str) + return -ENOMEM; ret = device_bind_driver(bus, "i2c_generic_chip_drv", str, &dev); debug("%s: device_bind_driver: ret=%d\n", __func__, ret); if (ret) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0df25c331f..36a8f0d098 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -53,3 +53,11 @@ config DM_CROS_EC but otherwise makes few changes. Since cros_ec also supports LPC (which doesn't support driver model yet), a full conversion is not yet possible. + +config CONFIG_FSL_SEC_MON + bool "Enable FSL SEC_MON Driver" + help + Freescale Security Monitor block is responsible for monitoring + system states. + Security Monitor can be transitioned on any security failures, + like software violations or hardware security violations. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a34972df4e..6028cd43fb 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o +obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c new file mode 100644 index 0000000000..d482a7db9c --- /dev/null +++ b/drivers/misc/fsl_sec_mon.c @@ -0,0 +1,146 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_sec_mon.h> + +int change_sec_mon_state(u32 initial_state, u32 final_state) +{ + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + int timeout = 10; + + if ((sts & HPSR_SSM_ST_MASK) != initial_state) + return -1; + + if (initial_state == HPSR_SSM_ST_TRUST) { + switch (final_state) { + case HPSR_SSM_ST_NON_SECURE: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); + + /* + * poll till SEC_MON is in + * Soft Fail state + */ + while (((sts & HPSR_SSM_ST_MASK) != + HPSR_SSM_ST_SOFT_FAIL)) { + while (timeout) { + sts = sec_mon_in32 + (&sec_mon_regs->hp_stat); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + + timeout = 10; + + printf("SEC_MON state transitioning to Non Secure.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST); + + /* + * poll till SEC_MON is in + * Non Secure state + */ + while (((sts & HPSR_SSM_ST_MASK) != + HPSR_SSM_ST_NON_SECURE)) { + while (timeout) { + sts = sec_mon_in32 + (&sec_mon_regs->hp_stat); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; + } + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + case HPSR_SSM_ST_SOFT_FAIL: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); + + /* + * polling loop till SEC_MON is in + * Soft Fail state + */ + while (((sts & HPSR_SSM_ST_MASK) != + HPSR_SSM_ST_SOFT_FAIL)) { + while (timeout) { + sts = sec_mon_in32 + (&sec_mon_regs->hp_stat); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + default: + return -1; + } + } else if (initial_state == HPSR_SSM_ST_NON_SECURE) { + switch (final_state) { + case HPSR_SSM_ST_SOFT_FAIL: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); + + /* + * polling loop till SEC_MON is in + * Soft Fail state + */ + while (((sts & HPSR_SSM_ST_MASK) != + HPSR_SSM_ST_SOFT_FAIL)) { + while (timeout) { + sts = sec_mon_in32 + (&sec_mon_regs->hp_stat); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + default: + return -1; + } + } + + return 0; +} diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28217..c5e270dd57 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -54,19 +54,21 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */ - char reserved2[160]; /* reserved */ + char reserved2[100]; /* reserved */ + uint vendorspec; /* Vendor Specific register */ + char reserved3[59]; /* reserved */ uint hostver; /* Host controller version register */ - char reserved3[4]; /* reserved */ - uint dmaerraddr; /* DMA error address register */ char reserved4[4]; /* reserved */ - uint dmaerrattr; /* DMA error attribute register */ + uint dmaerraddr; /* DMA error address register */ char reserved5[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved6[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */ - char reserved6[8]; /* reserved */ + char reserved7[8]; /* reserved */ uint tcr; /* Tuning control register */ - char reserved7[28]; /* reserved */ + char reserved8[28]; /* reserved */ uint sddirctl; /* SD direction control register */ - char reserved8[712]; /* reserved */ + char reserved9[712]; /* reserved */ uint scr; /* eSDHC control register */ }; @@ -319,7 +321,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) esdhc_write32(®s->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(®s->mixctrl, - (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(®s->xfertyp, xfertyp); @@ -341,6 +344,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) goto out; } + /* Switch voltage to 1.8V if CMD11 succeeded */ + if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); + + printf("Run CMD11 1.8V switch\n"); + /* Sleep for 5 ms - max time for card to switch to 1.8V */ + udelay(5000); + } + /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 2500; @@ -413,6 +425,10 @@ out: while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) ; } + + /* If this was CMD11, then notify that power cycle is needed */ + if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) + printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); } esdhc_write32(®s->irqstat, -1); @@ -442,7 +458,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break; - pre_div >>= 1; + pre_div >>= mmc->ddr_mode ? 2 : 1; div -= 1; clk = (pre_div << 8) | (div << 4); @@ -508,6 +524,10 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); +#endif + return 0; } @@ -601,6 +621,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) } cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; +#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; +#endif if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index c24221499b..72825c3e2e 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -6,8 +6,6 @@ config SYS_NAND_SELF_INIT This option, if enabled, provides more flexible and linux-like NAND initialization process. -if !SPL_BUILD - config NAND_DENALI bool "Support Denali NAND controller" select SYS_NAND_SELF_INIT @@ -34,9 +32,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES of OOB area before last ECC sector data starts. This is potentially used to preserve the bad block marker in the OOB area. -endif - -if SPL_BUILD +if SPL config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 24123fcfe5..610f9698e1 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -30,13 +30,22 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, static uint8_t cs_next; static __maybe_unused struct nand_ecclayout omap_ecclayout; +#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = + { CONFIG_NAND_OMAP_GPMC_WSCFG }; +#else +/* wscfg is preset to zero since its a static variable */ +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE]; +#endif + /* * Driver configurations */ struct omap_nand_info { struct bch_control *control; enum omap_ecc ecc_scheme; - int cs; + uint8_t cs; + uint8_t ws; /* wait status pin (0,1) */ }; /* We are wasting a bit of memory but al least we are safe */ @@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, /* Check wait pin as dev ready indicator */ static int omap_dev_ready(struct mtd_info *mtd) { - return gpmc_cfg->status & (1 << 8); + register struct nand_chip *this = mtd->priv; + struct omap_nand_info *info = this->priv; + return gpmc_cfg->status & (1 << (8 + info->ws)); } /* @@ -901,8 +912,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) return -EINVAL; } } else { - err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + if (eccstrength == 1) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_HAM1_CODE_SW, mtd->writesize, mtd->oobsize); + } else if (eccstrength == 8) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + mtd->writesize, mtd->oobsize); + } else { + printf("nand: error: unsupported ECC scheme\n"); + return -EINVAL; + } } /* Update NAND handling after ECC mode switch */ @@ -962,6 +983,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; omap_nand_info[cs].control = NULL; omap_nand_info[cs].cs = cs; + omap_nand_info[cs].ws = wscfg[cs]; nand->priv = &omap_nand_info[cs]; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 46c4ac697d..b8b08034eb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o -obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_MACB) += macb.o @@ -65,5 +64,5 @@ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o -obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/ +obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_VSC9953) += vsc9953.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c03e935e2f..cc01604e60 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -253,11 +253,20 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); +#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); +#else + writel(readl(&dma_p->opmode) | FLUSHTXFIFO, + &dma_p->opmode); +#endif writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); +#ifdef CONFIG_DW_AXI_BURST_LEN + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); +#endif + /* Start up the PHY */ if (phy_startup(priv->phydev)) { printf("Could not initialize PHY %s\n", diff --git a/drivers/net/designware.h b/drivers/net/designware.h index ce51102052..49d900cb3f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -68,7 +68,9 @@ struct eth_dma_regs { u32 status; /* 0x14 */ u32 opmode; /* 0x18 */ u32 intenable; /* 0x1c */ - u8 reserved[40]; + u32 reserved1[2]; + u32 axibus; /* 0x28 */ + u32 reserved2[7]; u32 currhosttxdesc; /* 0x48 */ u32 currhostrxdesc; /* 0x4c */ u32 currhosttxbuffaddr; /* 0x50 */ diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl-mc/Makefile index 483408623c..206ac6be07 100644 --- a/drivers/net/fsl_mc/Makefile +++ b/drivers/net/fsl-mc/Makefile @@ -5,4 +5,6 @@ # # Layerscape MC driver -obj-y += mc.o +obj-y += mc.o \ + mc_sys.o \ + dpmng.o diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c new file mode 100644 index 0000000000..cc14c7b755 --- /dev/null +++ b/drivers/net/fsl-mc/dpmng.c @@ -0,0 +1,91 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <fsl-mc/fsl_mc_sys.h> +#include <fsl-mc/fsl_mc_cmd.h> +#include <fsl-mc/fsl_dpmng.h> +#include "fsl_dpmng_cmd.h" + +int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, + MC_CMD_PRI_LOW, 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMNG_RSP_GET_VERSION(cmd, mc_ver_info); + + return 0; +} + +int dpmng_reset_aiop(struct fsl_mc_io *mc_io, int container_id, + int aiop_tile_id) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_AIOP, + MC_CMD_PRI_LOW, 0); + DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_load_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + uint64_t img_iova, + uint32_t img_size) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_LOAD_AIOP, + MC_CMD_PRI_LOW, + 0); + DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, + img_iova); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_run_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + const struct dpmng_aiop_run_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RUN_AIOP, + MC_CMD_PRI_LOW, + 0); + DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_MC_PORTAL, + MC_CMD_PRI_LOW, + 0); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h new file mode 100644 index 0000000000..c9fe021f45 --- /dev/null +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -0,0 +1,49 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_DPMNG_CMD_H +#define __FSL_DPMNG_CMD_H + +/* Command IDs */ +#define DPMNG_CMDID_GET_VERSION 0x831 +#define DPMNG_CMDID_RESET_AIOP 0x832 +#define DPMNG_CMDID_LOAD_AIOP 0x833 +#define DPMNG_CMDID_RUN_AIOP 0x834 +#define DPMNG_CMDID_RESET_MC_PORTAL 0x835 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \ + MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \ + img_iova) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, img_size); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, img_iova); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->cores_mask); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options); \ +} while (0) + +#endif /* __FSL_DPMNG_CMD_H */ diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl-mc/mc.c index df84568a94..74b0085301 100644 --- a/drivers/net/fsl_mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -3,9 +3,12 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #include <errno.h> #include <asm/io.h> -#include <fsl_mc.h> +#include <fsl-mc/fsl_mc.h> +#include <fsl-mc/fsl_mc_sys.h> +#include <fsl-mc/fsl_dpmng.h> DECLARE_GLOBAL_DATA_PTR; static int mc_boot_status; @@ -14,7 +17,7 @@ static int mc_boot_status; * Copying MC firmware or DPL image to DDR */ static int mc_copy_image(const char *title, - u64 image_addr, u32 image_size, u64 mc_ram_addr) + u64 image_addr, u32 image_size, u64 mc_ram_addr) { debug("%s copied to address %p\n", title, (void *)mc_ram_addr); memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); @@ -25,10 +28,9 @@ static int mc_copy_image(const char *title, * MC firmware FIT image parser checks if the image is in FIT * format, verifies integrity of the image and calculates * raw image address and size values. - * Returns 0 if success and 1 if any of the above mentioned + * Returns 0 on success and a negative errno on error. * task fail. **/ - int parse_mc_firmware_fit_image(const void **raw_image_addr, size_t *raw_image_size) { @@ -39,7 +41,7 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr, size_t size; const char *uname = "firmware"; - /* Check if the image is in NOR flash*/ + /* Check if the image is in NOR flash */ #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; #else @@ -50,26 +52,26 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr, format = genimg_get_format(fit_hdr); if (format != IMAGE_FORMAT_FIT) { - debug("Not a FIT image\n"); - return 1; + printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n"); + return -EINVAL; } if (!fit_check_format(fit_hdr)) { - debug("Bad FIT image format\n"); - return 1; + printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n"); + return -EINVAL; } node_offset = fit_image_get_node(fit_hdr, uname); if (node_offset < 0) { - debug("Can not find %s subimage\n", uname); - return 1; + printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n"); + return -ENOENT; } /* Verify MC firmware image */ if (!(fit_image_verify(fit_hdr, node_offset))) { - debug("Bad MC firmware hash"); - return 1; + printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n"); + return -EINVAL; } /* Get address and size of raw image */ @@ -90,12 +92,13 @@ int mc_init(bd_t *bis) u64 mc_dpl_offset; u32 reg_gsr; u32 mc_fw_boot_status; - void *fdt_hdr; + void *dpl_fdt_hdr; int dpl_size; const void *raw_image_addr; size_t raw_image_size = 0; - - BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0); + struct fsl_mc_io mc_io; + int portal_id; + struct mc_version mc_ver_info; /* * The MC private DRAM block was already carved at the end of DRAM @@ -130,25 +133,44 @@ int mc_init(bd_t *bis) /* * Load the MC FW at the beginning of the MC private DRAM block: */ - mc_copy_image( - "MC Firmware", - (u64)raw_image_addr, - raw_image_size, - mc_ram_addr); + mc_copy_image("MC Firmware", + (u64)raw_image_addr, raw_image_size, mc_ram_addr); + + /* + * Get address and size of the DPL blob stored in flash: + */ +#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR + dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" +#endif + + error = fdt_check_header(dpl_fdt_hdr); + if (error != 0) { + printf("fsl-mc: ERROR: Bad DPL image (bad header)\n"); + goto out; + } + + dpl_size = fdt_totalsize(dpl_fdt_hdr); + if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n", + dpl_size); + error = -EINVAL; + goto out; + } /* * Calculate offset in the MC private DRAM block at which the MC DPL * blob is to be placed: */ #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET - BUILD_BUG_ON( - (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); + BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; #else mc_dpl_offset = mc_get_dram_block_size() - - roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096); + roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096); if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) { printf("%s: Invalid MC DPL offset: %llu\n", @@ -158,23 +180,14 @@ int mc_init(bd_t *bis) } #endif - /* Check if DPL image is in NOR flash */ -#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR - fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" -#endif - - dpl_size = fdt_totalsize(fdt_hdr); - /* * Load the MC DPL blob at the far end of the MC private DRAM block: + * + * TODO: Should we place the DPL at a different location to match + * assumptions of MC firmware about its memory layout? */ - mc_copy_image( - "MC DPL blob", - (u64)fdt_hdr, - dpl_size, - mc_ram_addr + mc_dpl_offset); + mc_copy_image("MC DPL blob", + (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); debug("mc_ccsr_regs %p\n", mc_ccsr_regs); @@ -200,6 +213,8 @@ int mc_init(bd_t *bis) */ out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2)); + printf("\nfsl-mc: Booting Management Complex ...\n"); + /* * Deassert reset and release MC core 0 to run */ @@ -219,17 +234,13 @@ int mc_init(bd_t *bis) } if (timeout <= 0) { - printf("%s: timeout booting management complex firmware\n", - __func__); + printf("fsl-mc: timeout booting management complex firmware\n"); /* TODO: Get an error status from an MC CCSR register */ error = -ETIMEDOUT; goto out; } - printf("Management complex booted (boot status: %#x)\n", - mc_fw_boot_status); - if (mc_fw_boot_status != 0x1) { /* * TODO: Identify critical errors from the GSR register's FS @@ -237,8 +248,41 @@ int mc_init(bd_t *bis) * appropriate errno, so that the status property is set to * failure in the fsl,dprc device tree node. */ + printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n", + reg_gsr); } + /* + * TODO: need to obtain the portal_id for the root container from the + * DPL + */ + portal_id = 0; + + /* + * Check that the MC firmware is responding portal commands: + */ + mc_io.mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); + debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", + portal_id, mc_io.mmio_regs); + + error = mc_get_version(&mc_io, &mc_ver_info); + if (error != 0) { + printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", + error); + goto out; + } + + if (MC_VER_MAJOR != mc_ver_info.major) + printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n", + mc_ver_info.major, MC_VER_MAJOR); + + if (MC_VER_MINOR != mc_ver_info.minor) + printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n", + mc_ver_info.minor, MC_VER_MINOR); + + printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", + mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, + mc_fw_boot_status); out: if (error != 0) mc_boot_status = -error; diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c new file mode 100644 index 0000000000..7c8e003ad0 --- /dev/null +++ b/drivers/net/fsl-mc/mc_sys.c @@ -0,0 +1,63 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Author: German Rivera <German.Rivera@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <fsl-mc/fsl_mc_sys.h> +#include <fsl-mc/fsl_mc_cmd.h> +#include <common.h> +#include <errno.h> +#include <asm/io.h> + +#define MC_CMD_HDR_READ_CMDID(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S)) + +/** + * mc_send_command - Send MC command and wait for response + * + * @mc_io: Pointer to MC I/O object to be used + * @cmd: MC command buffer. On input, it contains the command to send to the MC. + * On output, it contains the response from the MC if any. + * + * Depending on the sharing option specified when creating the MC portal + * wrapper, this function will use a spinlock or mutex to ensure exclusive + * access to the MC portal from the point when the command is sent until a + * response is received from the MC. + */ +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd) +{ + enum mc_cmd_status status; + int timeout = 2000; + + mc_write_command(mc_io->mmio_regs, cmd); + + for ( ; ; ) { + status = mc_read_response(mc_io->mmio_regs, cmd); + if (status != MC_CMD_STATUS_READY) + break; + + if (--timeout == 0) { + printf("Error: Timeout waiting for MC response\n"); + return -ETIMEDOUT; + } + + udelay(500); + } + + if (status != MC_CMD_STATUS_OK) { + printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n", + mc_io->mmio_regs, + (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header), + (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), + (unsigned int)status); + + return -EIO; + } + + return 0; +} diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c deleted file mode 100644 index b4822e9504..0000000000 --- a/drivers/net/ks8695eth.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * ks8695eth.c -- KS8695 ethernet driver - * - * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/****************************************************************************/ - -#include <common.h> -#include <malloc.h> -#include <net.h> -#include <asm/io.h> -#include <asm/arch/platform.h> - -/****************************************************************************/ - -/* - * Hardware register access to the KS8695 LAN ethernet port - * (well, it is the 4 port switch really). - */ -#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v) - -/****************************************************************************/ - -/* - * Define the descriptor in-memory data structures. - */ -struct ks8695_txdesc { - uint32_t owner; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -struct ks8695_rxdesc { - uint32_t status; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -/****************************************************************************/ - -/* - * Allocate local data structures to use for receiving and sending - * packets. Just to keep it all nice and simple. - */ - -#define TXDESCS 4 -#define RXDESCS 4 -#define BUFSIZE 2048 - -volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256))); -volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256))); -volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));; - -/****************************************************************************/ - -/* - * Ideally we want to use the MAC address stored in flash. - * But we do some sanity checks in case they are not present - * first. - */ -unsigned char eth_mac[] = { - 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00 -}; - -void ks8695_getmac(void) -{ - unsigned char *fp; - int i; - - /* Check if flash MAC is valid */ - fp = (unsigned char *) 0x0201c000; - for (i = 0; (i < 6); i++) { - if ((fp[i] != 0) && (fp[i] != 0xff)) - break; - } - - /* If we found a valid looking MAC address then use it */ - if (i < 6) - memcpy(ð_mac[0], fp, 6); -} - -/****************************************************************************/ - -static int ks8695_eth_init(struct eth_device *dev, bd_t *bd) -{ - int i; - - debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines first */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); - - ks8695_getmac(); - - /* Set MAC address */ - ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) | - (eth_mac[3] << 16) | (eth_mac[2] << 24))); - ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8))); - - /* Turn the 4 port switch on */ - i = ks8695_read(KS8695_SWITCH_CTRL0); - ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1)); - /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */ - - /* Initialize descriptor rings */ - for (i = 0; (i < TXDESCS); i++) { - ks8695_tx[i].owner = 0; - ks8695_tx[i].ctrl = 0; - ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE]; - ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1]; - } - ks8695_tx[TXDESCS-1].ctrl = 0x02000000; - ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0]; - - for (i = 0; (i < RXDESCS); i++) { - ks8695_rx[i].status = 0x80000000; - ks8695_rx[i].ctrl = BUFSIZE - 4; - ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE]; - ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1]; - } - ks8695_rx[RXDESCS-1].ctrl |= 0x00080000; - ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0]; - - /* The KS8695 is pretty slow reseting the ethernets... */ - udelay(2000000); - - /* Enable the ethernet engine */ - ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]); - ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]); - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_RX, 0x71); - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - - printf("KS8695 ETHERNET: %pM\n", eth_mac); - return 0; -} - -/****************************************************************************/ - -static void ks8695_eth_halt(struct eth_device *dev) -{ - debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); -} - -/****************************************************************************/ - -static int ks8695_eth_recv(struct eth_device *dev) -{ - volatile struct ks8695_rxdesc *dp; - int i, len = 0; - - debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__); - - for (i = 0; (i < RXDESCS); i++) { - dp= &ks8695_rx[i]; - if ((dp->status & 0x80000000) == 0) { - len = (dp->status & 0x7ff) - 4; - NetReceive((void *) dp->addr, len); - dp->status = 0x80000000; - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - break; - } - } - - return len; -} - -/****************************************************************************/ - -static int ks8695_eth_send(struct eth_device *dev, void *packet, int len) -{ - volatile struct ks8695_txdesc *dp; - static int next = 0; - - debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__, - packet, len); - - dp = &ks8695_tx[next]; - memcpy((void *) dp->addr, (void *) packet, len); - - if (len < 64) { - memset((void *) (dp->addr + len), 0, 64-len); - len = 64; - } - - dp->ctrl = len | 0xe0000000; - dp->owner = 0x80000000; - - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_TX_START, 0x1); - - if (++next >= TXDESCS) - next = 0; - - return 0; -} - -/****************************************************************************/ - -int ks8695_eth_initialize(void) -{ - struct eth_device *dev; - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - return -1; - memset(dev, 0, sizeof(*dev)); - - dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX; - dev->init = ks8695_eth_init; - dev->halt = ks8695_eth_halt; - dev->send = ks8695_eth_send; - dev->recv = ks8695_eth_recv; - strcpy(dev->name, "ks8695eth"); - - eth_register(dev); - return 0; -} diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 291c249c86..bcad8f2aec 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver * * SPDX-License-Identifier: GPL-2.0+ @@ -9,8 +9,465 @@ #include <asm/arch/fsl_serdes.h> #include <pci.h> #include <asm/io.h> +#include <errno.h> +#include <malloc.h> #include <asm/pcie_layerscape.h> +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_SIZE +#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ +#endif + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +#define PCIE_LINK_CAP 0x7c +#define PCIE_LINK_SPEED_MASK 0xf +#define PCIE_LINK_STA 0x82 + +#define PCIE_DBI_SIZE (4 * 1024) /* 4K */ + +struct ls_pcie { + int idx; + void __iomem *dbi; + void __iomem *va_cfg0; + void __iomem *va_cfg1; + struct pci_controller hose; +}; + +struct ls_pcie_info { + unsigned long regs; + int pci_num; + u64 cfg0_phys; + u64 cfg0_size; + u64 cfg1_phys; + u64 cfg1_size; + u64 mem_bus; + u64 mem_phys; + u64 mem_size; + u64 io_bus; + u64 io_phys; + u64 io_size; +}; + +#define SET_LS_PCIE_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ + x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ + x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ + x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ + x.pci_num = num; \ +} + +#ifdef CONFIG_LS102XA +#include <asm/arch/immap_ls102xa.h> + +/* PEX1/2 Misc Ports Status Register */ +#define LTSSM_STATE_SHIFT 20 +#define LTSSM_STATE_MASK 0x3f +#define LTSSM_PCIE_L0 0x11 /* L0 state */ + +static int ls_pcie_link_state(struct ls_pcie *pcie) +{ + u32 state; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + + state = in_be32(&scfg->pexmscportsr[pcie->idx]); + state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; + if (state < LTSSM_PCIE_L0) { + debug("....PCIe link error. LTSSM=0x%02x.\n", state); + return 0; + } + + return 1; +} +#else +#define PCIE_LDBG 0x7FC + +static int ls_pcie_link_state(struct ls_pcie *pcie) +{ + u32 state; + + state = readl(pcie->dbi + PCIE_LDBG); + if (state) + return 1; + + debug("....PCIe link error.\n"); + return 0; +} +#endif + +static int ls_pcie_link_up(struct ls_pcie *pcie) +{ + int state; + u32 cap; + + state = ls_pcie_link_state(pcie); + if (state) + return state; + + /* Try to download speed to gen1 */ + cap = readl(pcie->dbi + PCIE_LINK_CAP); + writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP); + udelay(2000); + state = ls_pcie_link_state(pcie); + if (state) + return state; + + writel(cap, pcie->dbi + PCIE_LINK_CAP); + + return 0; +} + +static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) +{ + writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, + pcie->dbi + PCIE_ATU_VIEWPORT); + writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); +} + +static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) +{ + writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, + pcie->dbi + PCIE_ATU_VIEWPORT); + writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); +} + +static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type, + u64 phys, u64 bus_addr, pci_size_t size) +{ + writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); + writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE); + writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE); + writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT); + writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET); + writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); + writel(type, pcie->dbi + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2); +} + +static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info) +{ +#ifdef DEBUG + int i; +#endif + + /* ATU 0 : OUTBOUND : CFG0 */ + ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_CFG0, + info->cfg0_phys, + 0, + info->cfg0_size); + /* ATU 1 : OUTBOUND : CFG1 */ + ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_CFG1, + info->cfg1_phys, + 0, + info->cfg1_size); + /* ATU 2 : OUTBOUND : MEM */ + ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2, + PCIE_ATU_TYPE_MEM, + info->mem_phys, + info->mem_bus, + info->mem_size); + /* ATU 3 : OUTBOUND : IO */ + ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3, + PCIE_ATU_TYPE_IO, + info->io_phys, + info->io_bus, + info->io_size); + +#ifdef DEBUG + for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) { + writel(PCIE_ATU_REGION_OUTBOUND | i, + pcie->dbi + PCIE_ATU_VIEWPORT); + debug("iATU%d:\n", i); + debug("\tLOWER PHYS 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_LOWER_BASE)); + debug("\tUPPER PHYS 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_UPPER_BASE)); + debug("\tLOWER BUS 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET)); + debug("\tUPPER BUS 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET)); + debug("\tLIMIT 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_LIMIT)); + debug("\tCR1 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_CR1)); + debug("\tCR2 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_CR2)); + } +#endif +} + +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +{ + /* Do not skip controller */ + return 0; +} + +static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d) +{ + if (PCI_DEV(d) > 0) + return -EINVAL; + + return 0; +} + +static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 *val) +{ + struct ls_pcie *pcie = hose->priv_data; + u32 busdev, *addr; + + if (ls_pcie_addr_valid(hose, d)) { + *val = 0xffffffff; + return -EINVAL; + } + + if (PCI_BUS(d) == hose->first_busno) { + addr = pcie->dbi + (where & ~0x3); + } else { + busdev = PCIE_ATU_BUS(PCI_BUS(d)) | + PCIE_ATU_DEV(PCI_DEV(d)) | + PCIE_ATU_FUNC(PCI_FUNC(d)); + + if (PCI_BUS(d) == hose->first_busno + 1) { + ls_pcie_cfg0_set_busdev(pcie, busdev); + addr = pcie->va_cfg0 + (where & ~0x3); + } else { + ls_pcie_cfg1_set_busdev(pcie, busdev); + addr = pcie->va_cfg1 + (where & ~0x3); + } + } + + *val = readl(addr); + + return 0; +} + +static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 val) +{ + struct ls_pcie *pcie = hose->priv_data; + u32 busdev, *addr; + + if (ls_pcie_addr_valid(hose, d)) + return -EINVAL; + + if (PCI_BUS(d) == hose->first_busno) { + addr = pcie->dbi + (where & ~0x3); + } else { + busdev = PCIE_ATU_BUS(PCI_BUS(d)) | + PCIE_ATU_DEV(PCI_DEV(d)) | + PCIE_ATU_FUNC(PCI_FUNC(d)); + + if (PCI_BUS(d) == hose->first_busno + 1) { + ls_pcie_cfg0_set_busdev(pcie, busdev); + addr = pcie->va_cfg0 + (where & ~0x3); + } else { + ls_pcie_cfg1_set_busdev(pcie, busdev); + addr = pcie->va_cfg1 + (where & ~0x3); + } + } + + writel(val, addr); + + return 0; +} + +static void ls_pcie_setup_ctrl(struct ls_pcie *pcie, + struct ls_pcie_info *info) +{ + struct pci_controller *hose = &pcie->hose; + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); + + ls_pcie_setup_atu(pcie, info); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0); + + /* program correct class for RC */ + pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE, + PCI_CLASS_BRIDGE_PCI); +} + +int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) +{ + struct ls_pcie *pcie; + struct pci_controller *hose; + int num = dev - PCIE1; + pci_dev_t pdev = PCI_BDF(busno, 0, 0); + int i, linkup, ep_mode; + u8 header_type; + u16 temp16; + + if (!is_serdes_configured(dev)) { + printf("PCIe%d: disabled\n", num + 1); + return busno; + } + + pcie = malloc(sizeof(*pcie)); + if (!pcie) + return busno; + memset(pcie, 0, sizeof(*pcie)); + + hose = &pcie->hose; + hose->priv_data = pcie; + hose->first_busno = busno; + pcie->idx = num; + pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE); + pcie->va_cfg0 = map_physmem(info->cfg0_phys, + info->cfg0_size, + MAP_NOCACHE); + pcie->va_cfg1 = map_physmem(info->cfg1_phys, + info->cfg1_size, + MAP_NOCACHE); + + /* outbound memory */ + pci_set_region(&hose->regions[0], + (pci_size_t)info->mem_bus, + (phys_size_t)info->mem_phys, + (pci_size_t)info->mem_size, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(&hose->regions[1], + (pci_size_t)info->io_bus, + (phys_size_t)info->io_phys, + (pci_size_t)info->io_size, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(&hose->regions[2], + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, + PCI_REGION_SYS_MEMORY); + + hose->region_count = 3; + + for (i = 0; i < hose->region_count; i++) + debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", + i, + (u64)hose->regions[i].phys_start, + (u64)hose->regions[i].bus_start, + (u64)hose->regions[i].size, + hose->regions[i].flags); + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + ls_pcie_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + ls_pcie_write_config); + + pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type); + ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; + printf("PCIe%u: %s ", info->pci_num, + ep_mode ? "Endpoint" : "Root Complex"); + + linkup = ls_pcie_link_up(pcie); + + if (!linkup) { + /* Let the user know there's no PCIe link */ + printf("no link, regs @ 0x%lx\n", info->regs); + hose->last_busno = hose->first_busno; + return busno; + } + + /* Print the negotiated PCIe link width */ + pci_hose_read_config_word(hose, dev, PCIE_LINK_STA, &temp16); + printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, + (temp16 & 0xf), info->regs); + + if (ep_mode) + return busno; + + ls_pcie_setup_ctrl(pcie, info); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + printf("PCIe%x: Bus %02x - %02x\n", + info->pci_num, hose->first_busno, hose->last_busno); + + return hose->last_busno + 1; +} + +int ls_pcie_init_board(int busno) +{ + struct ls_pcie_info info; + +#ifdef CONFIG_PCIE1 + SET_LS_PCIE_INFO(info, 1); + busno = ls_pcie_init_ctrl(busno, PCIE1, &info); +#endif + +#ifdef CONFIG_PCIE2 + SET_LS_PCIE_INFO(info, 2); + busno = ls_pcie_init_ctrl(busno, PCIE2, &info); +#endif + +#ifdef CONFIG_PCIE3 + SET_LS_PCIE_INFO(info, 3); + busno = ls_pcie_init_ctrl(busno, PCIE3, &info); +#endif + +#ifdef CONFIG_PCIE4 + SET_LS_PCIE_INFO(info, 4); + busno = ls_pcie_init_ctrl(busno, PCIE4, &info); +#endif + + return busno; +} + +void pci_init_board(void) +{ + ls_pcie_init_board(0); +} + #ifdef CONFIG_OF_BOARD_SETUP #include <libfdt.h> #include <fdt_support.h> @@ -38,6 +495,14 @@ void ft_pcie_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCIE2 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); #endif + + #ifdef CONFIG_PCIE3 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); + #endif + + #ifdef CONFIG_PCIE4 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); + #endif } #else @@ -45,7 +510,3 @@ void ft_pcie_setup(void *blob, bd_t *bd) { } #endif - -void pci_init_board(void) -{ -} diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c index 3e07f23c20..c2c3988804 100644 --- a/drivers/power/axp221.c +++ b/drivers/power/axp221.c @@ -385,6 +385,22 @@ int axp221_get_sid(unsigned int *sid) return 0; } +int axp_get_vbus(void) +{ + int ret; + u8 val; + + ret = axp221_init(); + if (ret) + return ret; + + ret = pmic_bus_read(AXP221_POWER_STATUS, &val); + if (ret) + return ret; + + return (val & AXP221_POWER_STATUS_VBUS_USABLE) ? 1 : 0; +} + static int axp_drivebus_setup(void) { int ret; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 63b0cbf5da..b385852eee 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index eb00f1ca8a..03beab5a14 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -80,7 +80,7 @@ static inline int serial_in_shift(unsigned char *addr, int shift) #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) return in_be32(addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) - return readb(addr + (1 << reg_shift) - 1); + return readb(addr + (1 << shift) - 1); #else return readb(addr); #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 95c992a5a3..9f78492298 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize); serial_initfunc(imx_serial_initialize); serial_initfunc(iop480_serial_initialize); serial_initfunc(jz_serial_initialize); -serial_initfunc(ks8695_serial_initialize); serial_initfunc(leon2_serial_initialize); serial_initfunc(leon3_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); @@ -220,7 +219,6 @@ void serial_initialize(void) imx_serial_initialize(); iop480_serial_initialize(); jz_serial_initialize(); - ks8695_serial_initialize(); leon2_serial_initialize(); leon3_serial_initialize(); lh7a40x_serial_initialize(); diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c deleted file mode 100644 index 13adabd112..0000000000 --- a/drivers/serial/serial_ks8695.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * serial.c -- KS8695 serial driver - * - * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> -#include <serial.h> -#include <linux/compiler.h> - -#ifndef CONFIG_SERIAL1 -#error "Bad: you didn't configure serial ..." -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define the UART hardware register access structure. - */ -struct ks8695uart { - unsigned int RX; /* 0x00 - Receive data (r) */ - unsigned int TX; /* 0x04 - Transmit data (w) */ - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ - unsigned int LCR; /* 0x0c - Line Control (r/w) */ - unsigned int MCR; /* 0x10 - Modem Control (r/w) */ - unsigned int LSR; /* 0x14 - Line Status (r/w) */ - unsigned int MSR; /* 0x18 - Modem Status (r/w) */ - unsigned int BD; /* 0x1c - Baud Rate (r/w) */ - unsigned int SR; /* 0x20 - Status (r/w) */ -}; - -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) -#define KS8695_UART_CLK 25000000 - - -/* - * Under some circumstances we want to be "quiet" and not issue any - * serial output - though we want u-boot to otherwise work and behave - * the same. By default be noisy. - */ -int serial_console = 1; - - -static void ks8695_serial_setbrg(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ - uartp->BD = KS8695_UART_CLK / gd->baudrate; - uartp->LCR = KS8695_UART_LINEC_WLEN8; -} - -static int ks8695_serial_init(void) -{ - serial_console = 1; - serial_setbrg(); - return 0; -} - -static void ks8695_serial_raw_putc(const char c) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - int i; - - for (i = 0; (i < 0x100000); i++) { - if (uartp->LSR & KS8695_UART_LINES_TXFE) - break; - } - - uartp->TX = c; -} - -static void ks8695_serial_putc(const char c) -{ - if (serial_console) { - ks8695_serial_raw_putc(c); - if (c == '\n') - ks8695_serial_raw_putc('\r'); - } -} - -static int ks8695_serial_tstc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - if (serial_console) - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); - return 0; -} - -static int ks8695_serial_getc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) - ; - return (uartp->RX); -} - -static struct serial_device ks8695_serial_drv = { - .name = "ks8695_serial", - .start = ks8695_serial_init, - .stop = NULL, - .setbrg = ks8695_serial_setbrg, - .putc = ks8695_serial_putc, - .puts = default_serial_puts, - .getc = ks8695_serial_getc, - .tstc = ks8695_serial_tstc, -}; - -void ks8695_serial_initialize(void) -{ - serial_register(&ks8695_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ks8695_serial_drv; -} diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 3641c9f834..8693c1ed14 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -69,7 +69,7 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) if (port->clk_mode == EXT_CLK) { unsigned short dl = DL_VALUE(baudrate, clk); sci_out(port, DL, dl); - /* Need wait: Clock * 1/dl $B!_(B 1/16 */ + /* Need wait: Clock * 1/dl * 1/16 */ udelay((1000000 * dl * 16 / clk) * 1000 + 1); } else { sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 528aa7351d..941e6eda4c 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -227,7 +227,8 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 -# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else # error CPU subtype not defined #endif @@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ +#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index e8a1608b99..a6bd27facf 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation + * Copyright (C) 2012-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,31 +13,25 @@ #include <serial.h> #include <fdtdec.h> -#define UART_REG(x) \ - u8 x; \ - u8 postpad_##x[3]; - /* * Note: Register map is slightly different from that of 16550. */ struct uniphier_serial { - UART_REG(rbr); /* 0x00 */ - UART_REG(ier); /* 0x04 */ - UART_REG(iir); /* 0x08 */ - UART_REG(fcr); /* 0x0c */ - u8 mcr; /* 0x10 */ - u8 lcr; - u16 __postpad; - UART_REG(lsr); /* 0x14 */ - UART_REG(msr); /* 0x18 */ - u32 __none1; - u32 __none2; - u16 dlr; - u16 __postpad2; + u32 rx; /* In: Receive buffer */ +#define tx rx /* Out: Transmit buffer */ + u32 ier; /* Interrupt Enable Register */ + u32 iir; /* In: Interrupt ID Register */ + u32 char_fcr; /* Charactor / FIFO Control Register */ + u32 lcr_mcr; /* Line/Modem Control Register */ +#define LCR_SHIFT 8 +#define LCR_MASK (0xff << (LCR_SHIFT)) + u32 lsr; /* In: Line Status Register */ + u32 msr; /* In: Modem Status Register */ + u32 __rsv0; + u32 __rsv1; + u32 dlr; /* Divisor Latch Register */ }; -#define thr rbr - struct uniphier_serial_private_data { struct uniphier_serial __iomem *membase; }; @@ -52,11 +46,9 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) const unsigned int mode_x_div = 16; unsigned int divisor; - writeb(UART_LCR_WLEN8, &port->lcr); - divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate); - writew(divisor, &port->dlr); + writel(divisor, &port->dlr); return 0; } @@ -65,20 +57,20 @@ static int uniphier_serial_getc(struct udevice *dev) { struct uniphier_serial __iomem *port = uniphier_serial_port(dev); - if (!(readb(&port->lsr) & UART_LSR_DR)) + if (!(readl(&port->lsr) & UART_LSR_DR)) return -EAGAIN; - return readb(&port->rbr); + return readl(&port->rx); } static int uniphier_serial_putc(struct udevice *dev, const char c) { struct uniphier_serial __iomem *port = uniphier_serial_port(dev); - if (!(readb(&port->lsr) & UART_LSR_THRE)) + if (!(readl(&port->lsr) & UART_LSR_THRE)) return -EAGAIN; - writeb(c, &port->thr); + writel(c, &port->tx); return 0; } @@ -88,21 +80,29 @@ static int uniphier_serial_pending(struct udevice *dev, bool input) struct uniphier_serial __iomem *port = uniphier_serial_port(dev); if (input) - return readb(&port->lsr) & UART_LSR_DR; + return readl(&port->lsr) & UART_LSR_DR; else - return !(readb(&port->lsr) & UART_LSR_THRE); + return !(readl(&port->lsr) & UART_LSR_THRE); } static int uniphier_serial_probe(struct udevice *dev) { + u32 tmp; struct uniphier_serial_private_data *priv = dev_get_priv(dev); struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + struct uniphier_serial __iomem *port; - priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial)); - - if (!priv->membase) + port = map_sysmem(plat->base, sizeof(struct uniphier_serial)); + if (!port) return -ENOMEM; + priv->membase = port; + + tmp = readl(&port->lcr_mcr); + tmp &= ~LCR_MASK; + tmp |= UART_LCR_WLEN8 << LCR_SHIFT; + writel(tmp, &port->lcr_mcr); + return 0; } diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 310175acfe..751ec9e010 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -55,6 +55,7 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) static struct f_fastboot *fastboot_func; static unsigned int download_size; static unsigned int download_bytes; +static bool is_high_speed; static struct usb_endpoint_descriptor fs_ep_in = { .bLength = USB_DT_ENDPOINT_SIZE, @@ -136,6 +137,7 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) int id; struct usb_gadget *gadget = c->cdev->gadget; struct f_fastboot *f_fb = func_to_fastboot(f); + const char *s; /* DYNAMIC interface numbers assignments */ id = usb_interface_id(c, f); @@ -161,6 +163,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + s = getenv("serial#"); + if (s) + g_dnl_set_serialnumber((char *)s); + return 0; } @@ -219,10 +225,13 @@ static int fastboot_set_alt(struct usb_function *f, __func__, f->name, interface, alt); /* make sure we don't enable the ep twice */ - if (gadget->speed == USB_SPEED_HIGH) + if (gadget->speed == USB_SPEED_HIGH) { ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); - else + is_high_speed = true; + } else { ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); + is_high_speed = false; + } if (ret) { puts("failed to enable out ep\n"); return ret; @@ -370,13 +379,20 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(void) +static unsigned int rx_bytes_expected(unsigned int maxpacket) { int rx_remain = download_size - download_bytes; + int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; + if (rx_remain < maxpacket) { + rx_remain = maxpacket; + } else if (rx_remain % maxpacket != 0) { + rem = rx_remain % maxpacket; + rx_remain = rx_remain + (maxpacket - rem); + } return rx_remain; } @@ -388,6 +404,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; unsigned int pre_dot_num, now_dot_num; + unsigned int max; if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -425,7 +442,9 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - req->length = rx_bytes_expected(); + max = is_high_speed ? hs_ep_out.wMaxPacketSize : + fs_ep_out.wMaxPacketSize; + req->length = rx_bytes_expected(max); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -438,6 +457,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; char response[RESPONSE_LEN]; + unsigned int max; strsep(&cmd, ":"); download_size = simple_strtoul(cmd, NULL, 16); @@ -453,7 +473,9 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - req->length = rx_bytes_expected(); + max = is_high_speed ? hs_ep_out.wMaxPacketSize : + fs_ep_out.wMaxPacketSize; + req->length = rx_bytes_expected(max); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -513,6 +535,50 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) } #endif +static void cb_oem(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; +#ifdef CONFIG_FASTBOOT_FLASH + if (strncmp("format", cmd + 4, 6) == 0) { + char cmdbuf[32]; + sprintf(cmdbuf, "gpt write mmc %x $partitions", + CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (run_command(cmdbuf, 0)) + fastboot_tx_write_str("FAIL"); + else + fastboot_tx_write_str("OKAY"); + } else +#endif + if (strncmp("unlock", cmd + 4, 8) == 0) { + fastboot_tx_write_str("FAILnot implemented"); + } + else { + fastboot_tx_write_str("FAILunknown oem command"); + } +} + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_erase(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + error("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + strcpy(response, "FAILno flash device defined"); + +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + fb_mmc_erase(cmd, response); +#endif + fastboot_tx_write_str(response); +} +#endif + struct cmd_dispatch_info { char *cmd; void (*cb)(struct usb_ep *ep, struct usb_request *req); @@ -539,8 +605,15 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = { { .cmd = "flash", .cb = cb_flash, + }, { + .cmd = "erase", + .cb = cb_erase, }, #endif + { + .cmd = "oem", + .cb = cb_oem, + }, }; static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 30d1457638..24a595fb42 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -17,6 +17,14 @@ config USB_XHCI if USB_XHCI_HCD +config USB_XHCI_UNIPHIER + bool "Support for Panasonic UniPhier on-chip xHCI USB controller" + depends on ARCH_UNIPHIER + default y + ---help--- + Enables support for the on-chip xHCI controller on Panasonic + UniPhier SoCs. + endif config USB_EHCI_HCD @@ -47,7 +55,7 @@ if USB_EHCI_HCD config USB_EHCI_UNIPHIER bool "Support for Panasonic UniPhier on-chip EHCI USB controller" - depends on ARCH_UNIPHIER + depends on ARCH_UNIPHIER && OF_CONTROL default y ---help--- Enables support for the on-chip EHCI controller on Panasonic diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 66d6e9a6d2..eb6f34b53c 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o +obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o # designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c index 32a4375279..b5ec296918 100644 --- a/drivers/usb/host/ehci-uniphier.c +++ b/drivers/usb/host/ehci-uniphier.c @@ -7,12 +7,12 @@ #include <common.h> #include <linux/err.h> +#include <asm/io.h> #include <usb.h> -#include <asm/arch/ehci-uniphier.h> +#include <mach/mio-regs.h> +#include <fdtdec.h> #include "ehci.h" -#ifdef CONFIG_OF_CONTROL -#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; #define FDT gd->fdt_blob @@ -35,18 +35,19 @@ static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) return -ENODEV; /* not found */ } -#else -static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) + +static void uniphier_ehci_reset(int index, int on) { - *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base; - return 0; + u32 tmp; + + tmp = readl(MIO_USB_RSTCTRL(index)); + if (on) + tmp &= ~MIO_USB_RSTCTRL_XRST; + else + tmp |= MIO_USB_RSTCTRL_XRST; + writel(tmp, MIO_USB_RSTCTRL(index)); } -#endif -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index a77c8bc919..3f86fdca89 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -182,7 +182,7 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); } -void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) { clrsetbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c new file mode 100644 index 0000000000..08b15e0ad1 --- /dev/null +++ b/drivers/usb/host/xhci-uniphier.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <usb.h> +#include <fdtdec.h> +#include "xhci.h" + +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base) +{ + DECLARE_GLOBAL_DATA_PTR; + int node_list[2]; + fdt_addr_t addr; + int count; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", + COMPAT_PANASONIC_XHCI, node_list, + ARRAY_SIZE(node_list)); + + if (index >= count) + return -ENODEV; + + addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg"); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + *base = (struct xhci_hccr *)addr; + + return 0; +} + +#define USB3_RST_CTRL 0x00100040 +#define IOMMU_RST_N (1 << 5) +#define LINK_RST_N (1 << 4) + +static void uniphier_xhci_reset(void __iomem *base, int on) +{ + u32 tmp; + + tmp = readl(base + USB3_RST_CTRL); + + if (on) + tmp &= ~(IOMMU_RST_N | LINK_RST_N); + else + tmp |= IOMMU_RST_N | LINK_RST_N; + + writel(tmp, base + USB3_RST_CTRL); +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + int ret; + struct xhci_hccr *cr; + struct xhci_hcor *or; + + ret = get_uniphier_xhci_base(index, &cr); + if (ret < 0) + return ret; + + uniphier_xhci_reset(cr, 0); + + or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase)); + + *hccr = cr; + *hcor = or; + + return 0; +} + +void xhci_hcd_stop(int index) +{ + int ret; + struct xhci_hccr *cr; + + ret = get_uniphier_xhci_base(index, &cr); + if (ret < 0) + return; + + uniphier_xhci_reset(cr, 1); +} diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 98f4830912..31a280edba 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -321,6 +321,7 @@ static int omap2430_musb_init(struct musb *musb) { u32 l; int status = 0; + unsigned long int start; #ifndef __UBOOT__ struct device *dev = musb->controller; struct omap2430_glue *glue = dev_get_drvdata(dev->parent); @@ -331,6 +332,21 @@ static int omap2430_musb_init(struct musb *musb) (struct omap_musb_board_data *)musb->controller; #endif + /* Reset the controller */ + musb_writel(musb->mregs, OTG_SYSCONFIG, SOFTRST); + + start = get_timer(0); + + while (1) { + l = musb_readl(musb->mregs, OTG_SYSCONFIG); + if ((l & SOFTRST) == 0) + break; + + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + dev_err(musb->controller, "MUSB reset is taking too long\n"); + return -ENODEV; + } + } #ifndef __UBOOT__ /* We require some kind of external transceiver, hooked diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index fe45db1e06..4d8c15a5e0 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -27,6 +27,15 @@ #include <asm-generic/gpio.h> #include "linux-compat.h" #include "musb_core.h" +#ifdef CONFIG_AXP152_POWER +#include <axp152.h> +#endif +#ifdef CONFIG_AXP209_POWER +#include <axp209.h> +#endif +#ifdef CONFIG_AXP221_POWER +#include <axp221.h> +#endif /****************************************************************************** ****************************************************************************** @@ -228,29 +237,44 @@ static int sunxi_musb_init(struct musb *musb) if (is_host_enabled(musb)) { int vbus_det = sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET); - if (vbus_det == -1) { - eprintf("Error invalid Vusb-det pin\n"); - return -EINVAL; - } - err = gpio_request(vbus_det, "vbus0_det"); - if (err) - return err; +#ifdef AXP_VBUS_DETECT + if (!strcmp(CONFIG_USB0_VBUS_DET, "axp_vbus_detect")) { + err = axp_get_vbus(); + if (err < 0) + return err; + } else { +#endif + if (vbus_det == -1) { + eprintf("Error invalid Vusb-det pin\n"); + return -EINVAL; + } + + err = gpio_request(vbus_det, "vbus0_det"); + if (err) + return err; + + err = gpio_direction_input(vbus_det); + if (err) { + gpio_free(vbus_det); + return err; + } + + err = gpio_get_value(vbus_det); + if (err) { + gpio_free(vbus_det); + return -EIO; + } - err = gpio_direction_input(vbus_det); - if (err) { gpio_free(vbus_det); - return err; +#ifdef AXP_VBUS_DETECT } +#endif - err = gpio_get_value(vbus_det); if (err) { eprintf("Error: A charger is plugged into the OTG\n"); - gpio_free(vbus_det); return -EIO; } - - gpio_free(vbus_det); } err = sunxi_usbc_request_resources(0); diff --git a/drivers/video/Makefile b/drivers/video/Makefile index af2d47bd75..22a316b536 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o -obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index ab9894102d..6f956499d7 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -127,6 +127,12 @@ int am335xfb_init(struct am335x_lcdpanel *panel) memset((void *)gd->fb_base, 0, 0x20); *(unsigned int *)gd->fb_base = 0x4000; + /* turn ON display through powercontrol function if accessible */ + if (0 != panel->panel_power_ctrl) + panel->panel_power_ctrl(1); + + debug("am335x-fb: wait for stable power ...\n"); + mdelay(panel->pup_delay); lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN; lcdhw->raster_ctrl = 0; lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE; @@ -159,11 +165,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel) gd->fb_base += 0x20; /* point fb behind palette */ - /* turn ON display through powercontrol function if accessible */ - if (0 != panel->panel_power_ctrl) { - mdelay(panel->pon_delay); - panel->panel_power_ctrl(1); - } + debug("am335x-fb: waiting picture to be stable.\n."); + mdelay(panel->pon_delay); return 0; } diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h index 8a0b131495..7f799d1f31 100644 --- a/drivers/video/am335x-fb.h +++ b/drivers/video/am335x-fb.h @@ -55,9 +55,14 @@ struct am335x_lcdpanel { unsigned int vsw; /* Vertical Sync Pulse Width */ unsigned int pxl_clk_div; /* Pixel clock divider*/ unsigned int pol; /* polarity of sync, clock signals */ + unsigned int pup_delay; /* + * time in ms after power on to + * initialization of lcd-controller + * (VCC ramp up time) + */ unsigned int pon_delay; /* - * time in ms for turning on lcd after - * initializing lcd-controller + * time in ms after initialization of + * lcd-controller (pic stabilization) */ void (*panel_power_ctrl)(int); /* fp for power on/off display */ }; diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c deleted file mode 100644 index bb7a7497cc..0000000000 --- a/drivers/video/mb86r0xgdc.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic - * controller. - */ - -#include <common.h> - -#include <malloc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <video_fb.h> -#include "videomodes.h" - -/* - * 4MB (at the end of system RAM) - */ -#define VIDEO_MEM_SIZE 0x400000 - -#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ - -/* - * Graphic Device - */ -static GraphicDevice mb86r0x; - -static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, - u32 *videomem) -{ - struct ctfb_res_modes var_mode; - u32 dcm1, dcm2, dcm3; - u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; - u8 hsw, vsw; - u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; - u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; - unsigned long div; - int bpp; - - bpp = video_get_params(&var_mode, modestr); - - if (bpp == 0) { - var_mode.xres = 640; - var_mode.yres = 480; - var_mode.pixclock = 39721; /* 25MHz */ - var_mode.left_margin = 48; - var_mode.right_margin = 16; - var_mode.upper_margin = 33; - var_mode.lower_margin = 10; - var_mode.hsync_len = 96; - var_mode.vsync_len = 2; - var_mode.sync = 0; - var_mode.vmode = 0; - bpp = 15; - } - - /* Fill memory with white */ - memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); - - mb86r0x.winSizeX = var_mode.xres; - mb86r0x.winSizeY = var_mode.yres; - - /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ - div = 660000 / (1000000000L / var_mode.pixclock); - if (div > 64) - div = 64; - if (0 == div) - div = 1; - - dcm1 = (div - 1) << 8; - dcm2 = 0x00000000; - if (var_mode.sync & FB_SYNC_CLK_INV) - dcm3 = 0x00000100; - else - dcm3 = 0x00000000; - - htp = var_mode.left_margin + var_mode.xres + - var_mode.hsync_len + var_mode.right_margin; - hdp = var_mode.xres; - hdb = var_mode.xres; - hsp = var_mode.xres + var_mode.right_margin; - hsw = var_mode.hsync_len; - - vsw = var_mode.vsync_len; - vtr = var_mode.upper_margin + var_mode.yres + - var_mode.vsync_len + var_mode.lower_margin; - vsp = var_mode.yres + var_mode.lower_margin; - vdp = var_mode.yres; - - l2m = ((var_mode.yres - 1) << (0)) | - (((var_mode.xres * 2) / 64) << (16)) | - ((1) << (31)); - - l2em = (1 << 0) | (1 << 1); - - l2oa0 = mb86r0x.frameAdrs; - l2da0 = mb86r0x.frameAdrs; - l2oa1 = mb86r0x.frameAdrs; - l2da1 = mb86r0x.frameAdrs; - l2dx = 0; - l2dy = 0; - l2wx = 0; - l2wy = 0; - l2ww = var_mode.xres; - l2wh = var_mode.yres - 1; - - writel(dcm1, &dsp->dcm1); - writel(dcm2, &dsp->dcm2); - writel(dcm3, &dsp->dcm3); - - writew(htp, &dsp->htp); - writew(hdp, &dsp->hdp); - writew(hdb, &dsp->hdb); - writew(hsp, &dsp->hsp); - writeb(hsw, &dsp->hsw); - - writeb(vsw, &dsp->vsw); - writew(vtr, &dsp->vtr); - writew(vsp, &dsp->vsp); - writew(vdp, &dsp->vdp); - - writel(l2m, &dsp->l2m); - writel(l2em, &dsp->l2em); - writel(l2oa0, &dsp->l2oa0); - writel(l2da0, &dsp->l2da0); - writel(l2oa1, &dsp->l2oa1); - writel(l2da1, &dsp->l2da1); - writew(l2dx, &dsp->l2dx); - writew(l2dy, &dsp->l2dy); - writew(l2wx, &dsp->l2wx); - writew(l2wy, &dsp->l2wy); - writew(l2ww, &dsp->l2ww); - writew(l2wh, &dsp->l2wh); - - writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); -} - -void *video_hw_init(void) -{ - struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; - GraphicDevice *pGD = &mb86r0x; - char *s; - u32 *vid; - - memset(pGD, 0, sizeof(GraphicDevice)); - - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->gdfBytesPP = 2; - pGD->memSize = VIDEO_MEM_SIZE; - pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; - - vid = (u32 *)pGD->frameAdrs; - - s = getenv("videomode"); - if (s != NULL) - dsp_init(&gdc->dsp0, s, vid); - - s = getenv("videomode1"); - if (s != NULL) - dsp_init(&gdc->dsp1, s, vid); - - return pGD; -} diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 1dc0f5aa10..482a4bd5be 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) obj-y += imx_watchdog.o endif -obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c deleted file mode 100644 index 3d3f366c02..0000000000 --- a/drivers/watchdog/tnetv107x_wdt.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * TNETV107X: Watchdog timer implementation (for reset) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> - -#define MAX_DIV 0xFFFE0001 - -struct wdt_regs { - u32 kick_lock; -#define KICK_LOCK_1 0x5555 -#define KICK_LOCK_2 0xaaaa - u32 kick; - - u32 change_lock; -#define CHANGE_LOCK_1 0x6666 -#define CHANGE_LOCK_2 0xbbbb - u32 change; - - u32 disable_lock; -#define DISABLE_LOCK_1 0x7777 -#define DISABLE_LOCK_2 0xcccc -#define DISABLE_LOCK_3 0xdddd - u32 disable; - - u32 prescale_lock; -#define PRESCALE_LOCK_1 0x5a5a -#define PRESCALE_LOCK_2 0xa5a5 - u32 prescale; -}; - -static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; - -#define wdt_reg_read(reg) __raw_readl(®s->reg) -#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg) - -static int write_prescale_reg(unsigned long prescale_value) -{ - wdt_reg_write(prescale_lock, PRESCALE_LOCK_1); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(prescale_lock, PRESCALE_LOCK_2); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(prescale, prescale_value); - - return 0; -} - -static int write_change_reg(unsigned long initial_timer_value) -{ - wdt_reg_write(change_lock, CHANGE_LOCK_1); - if ((wdt_reg_read(change_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(change_lock, CHANGE_LOCK_2); - if ((wdt_reg_read(change_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(change, initial_timer_value); - - return 0; -} - -static int wdt_control(unsigned long disable_value) -{ - wdt_reg_write(disable_lock, DISABLE_LOCK_1); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_2); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x2) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_3); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(disable, disable_value); - return 0; -} - -static int wdt_set_period(unsigned long msec) -{ - unsigned long change_value, count_value; - unsigned long prescale_value = 1; - unsigned long refclk_khz, maxdiv; - int ret; - - refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); - maxdiv = (MAX_DIV / refclk_khz); - - if ((!msec) || (msec > maxdiv)) - return -1; - - count_value = refclk_khz * msec; - if (count_value > 0xffff) { - change_value = count_value / 0xffff + 1; - prescale_value = count_value / change_value; - } else { - change_value = count_value; - } - - ret = write_prescale_reg(prescale_value - 1); - if (ret) - return ret; - - ret = write_change_reg(change_value); - if (ret) - return ret; - - return 0; -} - -unsigned long last_wdt = -1; - -int wdt_start(unsigned long msecs) -{ - int ret; - ret = wdt_control(0); - if (ret) - return ret; - ret = wdt_set_period(msecs); - if (ret) - return ret; - ret = wdt_control(1); - if (ret) - return ret; - ret = wdt_kick(); - last_wdt = msecs; - return ret; -} - -int wdt_stop(void) -{ - last_wdt = -1; - return wdt_control(0); -} - -int wdt_kick(void) -{ - wdt_reg_write(kick_lock, KICK_LOCK_1); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(kick_lock, KICK_LOCK_2); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(kick, 1); - return 0; -} - -void reset_cpu(ulong addr) -{ - clk_enable(TNETV107X_LPSC_WDT_ARM); - wdt_start(1); - wdt_kick(); -} |
