diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ax88796.h | 46 | ||||
| -rw-r--r-- | drivers/net/ne2000.c | 276 | ||||
| -rw-r--r-- | drivers/net/ne2000.h | 30 | ||||
| -rw-r--r-- | drivers/net/ne2000_base.h | 315 | ||||
| -rw-r--r-- | drivers/net/pcnet.c | 672 | ||||
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 3 | ||||
| -rw-r--r-- | drivers/usb/usb_ohci.c | 30 | ||||
| -rw-r--r-- | drivers/video/cfb_console.c | 5 |
8 files changed, 733 insertions, 644 deletions
diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h index 069ae80fa8..0e6f8a201c 100644 --- a/drivers/net/ax88796.h +++ b/drivers/net/ax88796.h @@ -23,24 +23,24 @@ #ifndef __DRIVERS_AX88796L_H__ #define __DRIVERS_AX88796L_H__ -#define DP_DATA (0x10 << 1) -#define START_PG 0x40 /* First page of TX buffer */ -#define START_PG2 0x48 -#define STOP_PG 0x80 /* Last page +1 of RX ring */ -#define TX_PAGES 12 -#define RX_START (START_PG+TX_PAGES) -#define RX_END STOP_PG +#define DP_DATA (0x10 << 1) +#define START_PG 0x40 /* First page of TX buffer */ +#define START_PG2 0x48 +#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define TX_PAGES 12 +#define RX_START (START_PG+TX_PAGES) +#define RX_END STOP_PG #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE -#define AX88796L_BYTE_ACCESS 0x00001000 -#define AX88796L_OFFSET 0x00000400 -#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ +#define AX88796L_BYTE_ACCESS 0x00001000 +#define AX88796L_OFFSET 0x00000400 +#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ AX88796L_BYTE_ACCESS + AX88796L_OFFSET -#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) -#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) +#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) +#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) -#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) +#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) #define EECS_HIGH (AX88796L_MEMR |= 0x10) #define EECS_LOW (AX88796L_MEMR &= 0xef) @@ -53,7 +53,7 @@ #define PAGE0_SET (AX88796L_CR &= 0x3f) #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) -#define BIT_DUMMY 0 +#define BIT_DUMMY 0 #define MAC_EEP_READ 1 #define MAC_EEP_WRITE 2 #define MAC_EEP_ERACE 3 @@ -62,20 +62,20 @@ /* R7780MP Specific code */ #if defined(CONFIG_R7780MP) -#define ISA_OFFSET 0x1400 -#define DP_IN(_b_, _o_, _d_) (_d_) = \ +#define ISA_OFFSET 0x1400 +#define DP_IN(_b_, _o_, _d_) (_d_) = \ *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) #define DP_OUT(_b_, _o_, _d_) \ *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) #else /* Please change for your target boards */ -#define ISA_OFFSET 0x0000 -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) -#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#define ISA_OFFSET 0x0000 +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) #endif diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index 99baeea3e8..d09da78295 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -57,13 +57,13 @@ and are covered by the appropriate copyright disclaimers included herein. ========================================================================== #####DESCRIPTIONBEGIN#### -Author(s): gthomas -Contributors: gthomas, jskov, rsandifo -Date: 2001-06-13 +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 Purpose: Description: -FIXME: Will fail if pinged with large packets (1520 bytes) +FIXME: Will fail if pinged with large packets (1520 bytes) Add promisc config Add SNMP @@ -77,24 +77,26 @@ Add SNMP #include <net.h> #include <malloc.h> -#define mdelay(n) udelay((n)*1000) +#define mdelay(n) udelay((n)*1000) /* forward definition of function used for the uboot interface */ void uboot_push_packet_len(int len); void uboot_push_tx_done(int key, int val); /* - ------------------------------------------------------------------------ - Debugging details - - Set to perms of: - 0 disables all debug output - 1 for process debug output - 2 for added data IO output: get_reg, put_reg - 4 for packet allocation/free output - 8 for only startup status, so we can tell we're installed OK -*/ -/*#define DEBUG 0xf*/ + * Debugging details + * + * Set to perms of: + * 0 disables all debug output + * 1 for process debug output + * 2 for added data IO output: get_reg, put_reg + * 4 for packet allocation/free output + * 8 for only startup status, so we can tell we're installed OK + */ +#if 0 +#define DEBUG 0xf +#else #define DEBUG 0 +#endif #if DEBUG & 1 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) @@ -128,27 +130,28 @@ dp83902a_init(void) DEBUG_FUNCTION(); base = dp->base; - if (!base) return false; /* No device found */ + if (!base) + return false; /* No device found */ DEBUG_LINE(); #if defined(NE2000_BASIC_INIT) /* AX88796L doesn't need */ /* Prepare ESA */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ /* Use the address from the serial EEPROM */ for (i = 0; i < 6; i++) DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", - "eeprom", - dp->esa[0], - dp->esa[1], - dp->esa[2], - dp->esa[3], - dp->esa[4], - dp->esa[5] ); + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); #endif /* NE2000_BASIC_INIT */ return true; @@ -162,7 +165,7 @@ dp83902a_stop(void) DEBUG_FUNCTION(); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ @@ -170,11 +173,11 @@ dp83902a_stop(void) } /* - This function is called to "start up" the interface. It may be called - multiple times, even when the hardware is already running. It will be - called whenever something "hardware oriented" changes and should leave - the hardware ready to send/receive packets. -*/ + * This function is called to "start up" the interface. It may be called + * multiple times, even when the hardware is already running. It will be + * called whenever something "hardware oriented" changes and should leave + * the hardware ready to send/receive packets. + */ static void dp83902a_start(u8 * enaddr) { @@ -196,16 +199,16 @@ dp83902a_start(u8 * enaddr) dp->tx_started = false; dp->running = true; DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ - dp->rx_next = dp->rx_buf_start-1; + dp->rx_next = dp->rx_buf_start - 1; dp->running = true; DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ - DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ dp->running = true; - for (i = 0; i < ETHER_ADDR_LEN; i++) { + for (i = 0; i < ETHER_ADDR_LEN; i++) { /* FIXME */ /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + * 0x1400)) = enaddr[i];*/ @@ -214,15 +217,15 @@ dp83902a_start(u8 * enaddr) /* Enable and start device */ DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ - DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ dp->running = true; } /* - This routine is called to start the transmitter. It is split out from the - data handling routine so it may be called either when data becomes first - available or when an Tx interrupt occurs -*/ + * This routine is called to start the transmitter. It is split out from the + * data handling routine so it may be called either when data becomes first + * available or when an Tx interrupt occurs + */ static void dp83902a_start_xmit(int start_page, int len) @@ -249,9 +252,9 @@ dp83902a_start_xmit(int start_page, int len) } /* - This routine is called to send data to the hardware. It is known a-priori - that there is free buffer space (dp->tx_next). -*/ + * This routine is called to send data to the hardware. It is known a-priori + * that there is free buffer space (dp->tx_next). + */ static void dp83902a_send(u8 *data, int total_len, u32 key) { @@ -265,7 +268,8 @@ dp83902a_send(u8 *data, int total_len, u32 key) DEBUG_FUNCTION(); len = pkt_len = total_len; - if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME; + if (pkt_len < IEEE_8023_MIN_FRAME) + pkt_len = IEEE_8023_MIN_FRAME; start_page = dp->tx_next; if (dp->tx_next == dp->tx_buf1) { @@ -284,17 +288,19 @@ dp83902a_send(u8 *data, int total_len, u32 key) printf("TX prep page %d len %d\n", start_page, pkt_len); #endif - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ { - /* Dummy read. The manual sez something slightly different, */ - /* but the code is extended a bit to do what Hitachi's monitor */ - /* does (i.e., also read data). */ + /* + * Dummy read. The manual sez something slightly different, + * but the code is extended a bit to do what Hitachi's monitor + * does (i.e., also read data). + */ u16 tmp; int len = 1; - DP_OUT(base, DP_RSAL, 0x100-len); - DP_OUT(base, DP_RSAH, (start_page-1) & 0xff); + DP_OUT(base, DP_RSAL, 0x100 - len); + DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); DP_OUT(base, DP_RBCL, len); DP_OUT(base, DP_RBCH, 0); DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); @@ -302,8 +308,10 @@ dp83902a_send(u8 *data, int total_len, u32 key) } #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* Stall for a bit before continuing to work around random data */ - /* corruption problems on some platforms. */ + /* + * Stall for a bit before continuing to work around random data + * corruption problems on some platforms. + */ CYGACC_CALL_IF_DELAY_US(1); #endif @@ -336,16 +344,18 @@ dp83902a_send(u8 *data, int total_len, u32 key) printf(" + %d bytes of padding\n", pkt_len - total_len); #endif /* Padding to 802.3 length was required */ - for (i = total_len; i < pkt_len;) { + for (i = total_len; i < pkt_len;) { i++; DP_OUT_DATA(dp->data, 0); } } #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* After last data write, delay for a bit before accessing the */ - /* device again, or we may get random data corruption in the last */ - /* datum (on some platforms). */ + /* + * After last data write, delay for a bit before accessing the + * device again, or we may get random data corruption in the last + * datum (on some platforms). + */ CYGACC_CALL_IF_DELAY_US(1); #endif @@ -360,21 +370,21 @@ dp83902a_send(u8 *data, int total_len, u32 key) /* Start transmit if not already going */ if (!dp->tx_started) { if (start_page == dp->tx1) { - dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ } else { - dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ } dp83902a_start_xmit(start_page, pkt_len); } } /* - This function is called when a packet has been received. It's job is - to prepare to unload the packet from the hardware. Once the length of - the packet is known, the upper layer of the driver can be told. When - the upper layer is ready to unload the packet, the internal function - 'dp83902a_recv' will be called to actually fetch it from the hardware. -*/ + * This function is called when a packet has been received. It's job is + * to prepare to unload the packet from the hardware. Once the length of + * the packet is known, the upper layer of the driver can be told. When + * the upper layer is ready to unload the packet, the internal function + * 'dp83902a_recv' will be called to actually fetch it from the hardware. + */ static void dp83902a_RxEvent(void) { @@ -407,9 +417,9 @@ dp83902a_RxEvent(void) DP_OUT(base, DP_RSAH, pkt); if (dp->rx_next == pkt) { if (cur == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */ + DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ return; } dp->rx_next = pkt; @@ -420,13 +430,13 @@ dp83902a_RxEvent(void) #endif /* read header (get data size)*/ - for (i = 0; i < sizeof(rcv_hdr);) { + for (i = 0; i < sizeof(rcv_hdr);) { DP_IN_DATA(dp->data, rcv_hdr[i++]); } #if DEBUG & 5 printf("rx hdr %02x %02x %02x %02x\n", - rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); #endif len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); @@ -434,19 +444,19 @@ dp83902a_RxEvent(void) uboot_push_packet_len(len); if (rcv_hdr[1] == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */ + DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ } } /* - This function is called as a result of the "eth_drv_recv()" call above. - It's job is to actually fetch data for a packet from the hardware once - memory buffers have been allocated for the packet. Note that the buffers - may come in pieces, using a scatter-gather list. This allows for more - efficient processing in the upper layers of the stack. -*/ + * This function is called as a result of the "eth_drv_recv()" call above. + * It's job is to actually fetch data for a packet from the hardware once + * memory buffers have been allocated for the packet. Note that the buffers + * may come in pieces, using a scatter-gather list. This allows for more + * efficient processing in the upper layers of the stack. + */ static void dp83902a_recv(u8 *data, int len) { @@ -478,7 +488,7 @@ dp83902a_recv(u8 *data, int len) #endif saved = false; - for (i = 0; i < 1; i++) { + for (i = 0; i < 1; i++) { if (data) { mlen = len; #if DEBUG & 4 @@ -545,8 +555,10 @@ dp83902a_TxEvent(void) uboot_push_tx_done(key, 0); } -/* Read the tally counters to clear them. Called in response to a CNT */ -/* interrupt. */ +/* + * Read the tally counters to clear them. Called in response to a CNT + * interrupt. + */ static void dp83902a_ClearCounters(void) { @@ -560,8 +572,10 @@ dp83902a_ClearCounters(void) DP_OUT(base, DP_ISR, DP_ISR_CNT); } -/* Deal with an overflow condition. This code follows the procedure set */ -/* out in section 7.0 of the datasheet. */ +/* + * Deal with an overflow condition. This code follows the procedure set + * out in section 7.0 of the datasheet. + */ static void dp83902a_Overflow(void) { @@ -581,9 +595,11 @@ dp83902a_Overflow(void) DP_OUT(base, DP_TCR, DP_TCR_LOCAL); DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); - /* Read in as many packets as we can and acknowledge any and receive */ - /* interrupts. Since the buffer has overflowed, a receive event of */ - /* some kind will have occured. */ + /* + * Read in as many packets as we can and acknowledge any and receive + * interrupts. Since the buffer has overflowed, a receive event of + * some kind will have occured. + */ dp83902a_RxEvent(); DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); @@ -591,8 +607,10 @@ dp83902a_Overflow(void) DP_OUT(base, DP_ISR, DP_ISR_OFLW); DP_OUT(base, DP_TCR, DP_TCR_NORMAL); - /* If a transmit command was issued, but no transmit event has occured, */ - /* restart it here. */ + /* + * If a transmit command was issued, but no transmit event has occured, + * restart it here. + */ DP_IN(base, DP_ISR, isr); if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); @@ -609,25 +627,33 @@ dp83902a_poll(void) DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); DP_IN(base, DP_ISR, isr); while (0 != isr) { - /* The CNT interrupt triggers when the MSB of one of the error */ - /* counters is set. We don't much care about these counters, but */ - /* we should read their values to reset them. */ + /* + * The CNT interrupt triggers when the MSB of one of the error + * counters is set. We don't much care about these counters, but + * we should read their values to reset them. + */ if (isr & DP_ISR_CNT) { dp83902a_ClearCounters(); } - /* Check for overflow. It's a special case, since there's a */ - /* particular procedure that must be followed to get back into */ - /* a running state.a */ + /* + * Check for overflow. It's a special case, since there's a + * particular procedure that must be followed to get back into + * a running state.a + */ if (isr & DP_ISR_OFLW) { dp83902a_Overflow(); } else { - /* Other kinds of interrupts can be acknowledged simply by */ - /* clearing the relevant bits of the ISR. Do that now, then */ - /* handle the interrupts we care about. */ - DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + /* + * Other kinds of interrupts can be acknowledged simply by + * clearing the relevant bits of the ISR. Do that now, then + * handle the interrupts we care about. + */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ if (!dp->running) break; /* Is this necessary? */ - /* Check for tx_started on TX event since these may happen */ - /* spuriously it seems. */ + /* + * Check for tx_started on TX event since these may happen + * spuriously it seems. + */ if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { dp83902a_TxEvent(); } @@ -658,8 +684,8 @@ typedef struct hw_info_t { #define HAS_MII 0x40 #define USE_SHMEM 0x80 /* autodetected */ -#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ -#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ +#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ +#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ #define MII_PHYID_REV_MASK 0xfffffff0 #define MII_PHYID_REG1 0x02 #define MII_PHYID_REG2 0x03 @@ -669,7 +695,7 @@ static hw_info_t hw_info[] = { { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, - DELAY_OUTPUT | HAS_IBM_MISC }, + DELAY_OUTPUT | HAS_IBM_MISC }, { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, @@ -677,48 +703,48 @@ static hw_info_t hw_info[] = { { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, - DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, + DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, @@ -744,11 +770,11 @@ u32 nic_base; static u8 *pbuf = NULL; static int pkey = -1; -static int initialized=0; +static int initialized = 0; void uboot_push_packet_len(int len) { PRINTK("pushed len = %d\n", len); - if (len>=2000) { + if (len >= 2000) { printf("NE2000: packet too big\n"); return; } @@ -779,7 +805,7 @@ int eth_init(bd_t *bd) { #ifdef CONFIG_DRIVER_NE2000_CCR { - vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; + vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; PRINTK("CCR before is %x\n", *p); *p = CONFIG_DRIVER_NE2000_VAL; @@ -811,7 +837,7 @@ int eth_init(bd_t *bd) { return -1; dp83902a_start(dev_addr); - initialized=1; + initialized = 1; return 0; } @@ -821,7 +847,7 @@ void eth_halt() { PRINTK("### eth_halt\n"); if(initialized) dp83902a_stop(); - initialized=0; + initialized = 0; } int eth_rx() { diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h index d324a00084..6049482868 100644 --- a/drivers/net/ne2000.h +++ b/drivers/net/ne2000.h @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -7,9 +7,9 @@ are GPL, so this is, of course, GPL. ========================================================================== - dev/dp83902a.h + dev/dp83902a.h - National Semiconductor DP83902a ethernet chip + National Semiconductor DP83902a ethernet chip ========================================================================== ####ECOSGPLCOPYRIGHTBEGIN#### @@ -57,9 +57,9 @@ are GPL, so this is, of course, GPL. ========================================================================== #####DESCRIPTIONBEGIN#### - Author(s): gthomas - Contributors: gthomas, jskov - Date: 2001-06-13 + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 Purpose: Description: @@ -79,17 +79,17 @@ are GPL, so this is, of course, GPL. /* Enable NE2000 basic init function */ #define NE2000_BASIC_INIT -#define DP_DATA 0x10 -#define START_PG 0x50 /* First page of TX buffer */ -#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define DP_DATA 0x10 +#define START_PG 0x50 /* First page of TX buffer */ +#define STOP_PG 0x80 /* Last page +1 of RX ring */ -#define RX_START 0x50 -#define RX_END 0x80 +#define RX_START 0x50 +#define RX_END 0x80 -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) -#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) -#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) static void pcnet_reset_8390(void) { diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h index 1badf62bf2..990d7488c4 100644 --- a/drivers/net/ne2000_base.h +++ b/drivers/net/ne2000_base.h @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -8,9 +8,9 @@ are GPL, so this is, of course, GPL. ========================================================================== - dev/dp83902a.h + dev/dp83902a.h - National Semiconductor DP83902a ethernet chip + National Semiconductor DP83902a ethernet chip ========================================================================== ####ECOSGPLCOPYRIGHTBEGIN#### @@ -58,9 +58,9 @@ are GPL, so this is, of course, GPL. ========================================================================== #####DESCRIPTIONBEGIN#### - Author(s): gthomas - Contributors: gthomas, jskov - Date: 2001-06-13 + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 Purpose: Description: @@ -76,6 +76,9 @@ are GPL, so this is, of course, GPL. These can be overridden by the platform header */ +#ifndef __NE2000_BASE_H__ +#define __NE2000_BASE_H__ + #define bool int #define false 0 @@ -92,191 +95,191 @@ are GPL, so this is, of course, GPL. /* H/W infomation struct */ typedef struct hw_info_t { - u32 offset; - u8 a0, a1, a2; - u32 flags; + u32 offset; + u8 a0, a1, a2; + u32 flags; } hw_info_t; typedef struct dp83902a_priv_data { - u8* base; - u8* data; - u8* reset; - int tx_next; /* First free Tx page */ - int tx_int; /* Expecting interrupt from this buffer */ - int rx_next; /* First free Rx page */ - int tx1, tx2; /* Page numbers for Tx buffers */ - u32 tx1_key, tx2_key; /* Used to ack when packet sent */ - int tx1_len, tx2_len; - bool tx_started, running, hardwired_esa; - u8 esa[6]; - void* plf_priv; - - /* Buffer allocation */ - int tx_buf1, tx_buf2; - int rx_buf_start, rx_buf_end; + u8* base; + u8* data; + u8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + u32 tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + u8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; } dp83902a_priv_data_t; /* - ------------------------------------------------------------------------ - Some forward declarations -*/ + * Some forward declarations + */ int get_prom( u8* mac_addr); static void dp83902a_poll(void); /* ------------------------------------------------------------------------ */ /* Register offsets */ -#define DP_CR 0x00 -#define DP_CLDA0 0x01 -#define DP_PSTART 0x01 /* write */ -#define DP_CLDA1 0x02 -#define DP_PSTOP 0x02 /* write */ -#define DP_BNDRY 0x03 -#define DP_TSR 0x04 -#define DP_TPSR 0x04 /* write */ -#define DP_NCR 0x05 -#define DP_TBCL 0x05 /* write */ -#define DP_FIFO 0x06 -#define DP_TBCH 0x06 /* write */ -#define DP_ISR 0x07 -#define DP_CRDA0 0x08 -#define DP_RSAL 0x08 /* write */ -#define DP_CRDA1 0x09 -#define DP_RSAH 0x09 /* write */ -#define DP_RBCL 0x0a /* write */ -#define DP_RBCH 0x0b /* write */ -#define DP_RSR 0x0c -#define DP_RCR 0x0c /* write */ -#define DP_FER 0x0d -#define DP_TCR 0x0d /* write */ -#define DP_CER 0x0e -#define DP_DCR 0x0e /* write */ -#define DP_MISSED 0x0f -#define DP_IMR 0x0f /* write */ -#define DP_DATAPORT 0x10 /* "eprom" data port */ - -#define DP_P1_CR 0x00 -#define DP_P1_PAR0 0x01 -#define DP_P1_PAR1 0x02 -#define DP_P1_PAR2 0x03 -#define DP_P1_PAR3 0x04 -#define DP_P1_PAR4 0x05 -#define DP_P1_PAR5 0x06 -#define DP_P1_CURP 0x07 -#define DP_P1_MAR0 0x08 -#define DP_P1_MAR1 0x09 -#define DP_P1_MAR2 0x0a -#define DP_P1_MAR3 0x0b -#define DP_P1_MAR4 0x0c -#define DP_P1_MAR5 0x0d -#define DP_P1_MAR6 0x0e -#define DP_P1_MAR7 0x0f - -#define DP_P2_CR 0x00 -#define DP_P2_PSTART 0x01 -#define DP_P2_CLDA0 0x01 /* write */ -#define DP_P2_PSTOP 0x02 -#define DP_P2_CLDA1 0x02 /* write */ -#define DP_P2_RNPP 0x03 -#define DP_P2_TPSR 0x04 -#define DP_P2_LNPP 0x05 -#define DP_P2_ACH 0x06 -#define DP_P2_ACL 0x07 -#define DP_P2_RCR 0x0c -#define DP_P2_TCR 0x0d -#define DP_P2_DCR 0x0e -#define DP_P2_IMR 0x0f +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f /* Command register - common to all pages */ -#define DP_CR_STOP 0x01 /* Stop: software reset */ -#define DP_CR_START 0x02 /* Start: initialize device */ -#define DP_CR_TXPKT 0x04 /* Transmit packet */ -#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ -#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ -#define DP_CR_SEND 0x18 /* Send packet */ -#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ -#define DP_CR_PAGE0 0x00 /* Page select */ -#define DP_CR_PAGE1 0x40 -#define DP_CR_PAGE2 0x80 -#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ /* Data configuration register */ -#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ -#define DP_DCR_BOS 0x02 /* 1=Little Endian */ -#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ -#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ -#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ -#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ -#define DP_DCR_FIFO_2 0x20 -#define DP_DCR_FIFO_4 0x40 -#define DP_DCR_FIFO_6 0x60 +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 -#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) /* Interrupt status register */ -#define DP_ISR_RxP 0x01 /* Packet received */ -#define DP_ISR_TxP 0x02 /* Packet transmitted */ -#define DP_ISR_RxE 0x04 /* Receive error */ -#define DP_ISR_TxE 0x08 /* Transmit error */ -#define DP_ISR_OFLW 0x10 /* Receive overflow */ -#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ -#define DP_ISR_RDC 0x40 /* Remote DMA complete */ -#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ /* Interrupt mask register */ -#define DP_IMR_RxP 0x01 /* Packet received */ -#define DP_IMR_TxP 0x02 /* Packet transmitted */ -#define DP_IMR_RxE 0x04 /* Receive error */ -#define DP_IMR_TxE 0x08 /* Transmit error */ -#define DP_IMR_OFLW 0x10 /* Receive overflow */ -#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ -#define DP_IMR_RDC 0x40 /* Remote DMA complete */ +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ -#define DP_IMR_All 0x3F /* Everything but remote DMA */ +#define DP_IMR_All 0x3F /* Everything but remote DMA */ /* Receiver control register */ -#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ -#define DP_RCR_AR 0x02 /* Accept runt packets */ -#define DP_RCR_AB 0x04 /* Accept broadcast packets */ -#define DP_RCR_AM 0x08 /* Accept multicast packets */ -#define DP_RCR_PROM 0x10 /* Promiscuous mode */ -#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ /* Receiver status register */ -#define DP_RSR_RxP 0x01 /* Packet received */ -#define DP_RSR_CRC 0x02 /* CRC error */ -#define DP_RSR_FRAME 0x04 /* Framing error */ -#define DP_RSR_FO 0x08 /* FIFO overrun */ -#define DP_RSR_MISS 0x10 /* Missed packet */ -#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ -#define DP_RSR_DIS 0x40 /* Receiver disabled */ -#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ /* Transmitter control register */ -#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ -#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ -#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ -#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ -#define DP_TCR_OUTLOOP 0x08 /* External loopback */ -#define DP_TCR_ATD 0x10 /* Auto transmit disable */ -#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ /* Transmit status register */ -#define DP_TSR_TxP 0x01 /* Packet transmitted */ -#define DP_TSR_COL 0x04 /* Collision (at least one) */ -#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ -#define DP_TSR_CRS 0x10 /* Lost carrier */ -#define DP_TSR_FU 0x20 /* FIFO underrun */ -#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ -#define DP_TSR_OWC 0x80 /* Collision outside normal window */ - -#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ -#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ +#endif /* __NE2000_BASE_H__ */ diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 4e270c9f7b..386fa50bda 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -30,7 +30,7 @@ #include <pci.h> #if 0 -#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ +#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ #endif #if PCNET_DEBUG_LEVEL > 0 @@ -70,42 +70,42 @@ /* The PCNET Rx and Tx ring descriptors. */ struct pcnet_rx_head { - u32 base; - s16 buf_length; - s16 status; - u32 msg_length; - u32 reserved; + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; }; struct pcnet_tx_head { - u32 base; - s16 length; - s16 status; - u32 misc; - u32 reserved; + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; }; /* The PCNET 32-Bit initialization block, described in databook. */ struct pcnet_init_block { - u16 mode; - u16 tlen_rlen; - u8 phys_addr[6]; - u16 reserved; - u32 filter[2]; - /* Receive and transmit ring base, along with extra bits. */ - u32 rx_ring; - u32 tx_ring; - u32 reserved2; + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; + u32 reserved2; }; typedef struct pcnet_priv { - struct pcnet_rx_head rx_ring[RX_RING_SIZE]; - struct pcnet_tx_head tx_ring[TX_RING_SIZE]; - struct pcnet_init_block init_block; - /* Receive Buffer space */ - unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; - int cur_rx; - int cur_tx; + struct pcnet_rx_head rx_ring[RX_RING_SIZE]; + struct pcnet_tx_head tx_ring[TX_RING_SIZE]; + struct pcnet_init_block init_block; + /* Receive Buffer space */ + unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + int cur_rx; + int cur_tx; } pcnet_priv_t; static pcnet_priv_t *lp; @@ -118,57 +118,121 @@ static pcnet_priv_t *lp; static u16 pcnet_read_csr (struct eth_device *dev, int index) { - outw (index, dev->iobase+PCNET_RAP); - return inw (dev->iobase+PCNET_RDP); + outw (index, dev->iobase + PCNET_RAP); + return inw (dev->iobase + PCNET_RDP); } static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase+PCNET_RAP); - outw (val, dev->iobase+PCNET_RDP); + outw (index, dev->iobase + PCNET_RAP); + outw (val, dev->iobase + PCNET_RDP); } static u16 pcnet_read_bcr (struct eth_device *dev, int index) { - outw (index, dev->iobase+PCNET_RAP); - return inw (dev->iobase+PCNET_BDP); + outw (index, dev->iobase + PCNET_RAP); + return inw (dev->iobase + PCNET_BDP); } static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase+PCNET_RAP); - outw (val, dev->iobase+PCNET_BDP); + outw (index, dev->iobase + PCNET_RAP); + outw (val, dev->iobase + PCNET_BDP); } static void pcnet_reset (struct eth_device *dev) { - inw (dev->iobase+PCNET_RESET); + inw (dev->iobase + PCNET_RESET); } static int pcnet_check (struct eth_device *dev) { - outw (88, dev->iobase+PCNET_RAP); - return (inw (dev->iobase+PCNET_RAP) == 88); + outw (88, dev->iobase + PCNET_RAP); + return (inw (dev->iobase + PCNET_RAP) == 88); } -static int pcnet_init( struct eth_device* dev, bd_t *bis); -static int pcnet_send (struct eth_device* dev, volatile void *packet, - int length); -static int pcnet_recv (struct eth_device* dev); -static void pcnet_halt (struct eth_device* dev); -static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num); +static int pcnet_init (struct eth_device *dev, bd_t * bis); +static int pcnet_send (struct eth_device *dev, volatile void *packet, + int length); +static int pcnet_recv (struct eth_device *dev); +static void pcnet_halt (struct eth_device *dev); +static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) static struct pci_device_id supported[] = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, - { } + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, + {} }; -int pcnet_initialize(bd_t *bis) +int pcnet_initialize (bd_t * bis) { +<<<<<<< HEAD:drivers/net/pcnet.c + pci_dev_t devbusfn; + struct eth_device *dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1 ("\npcnet_initialize...\n"); + + for (dev_nr = 0;; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { + break; + } + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device *) malloc (sizeof *dev); + dev->priv = (void *) devbusfn; + sprintf (dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (unsigned int *) &dev->iobase); + dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word (devbusfn, PCI_COMMAND, command); + pci_read_config_word (devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); + free (dev); + continue; + } + + pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe (dev, bis, dev_nr) < 0) { + free (dev); + continue; + } + + /* + * Setup device structure and register the driver. + */ + dev->init = pcnet_init; + dev->halt = pcnet_halt; + dev->send = pcnet_send; + dev->recv = pcnet_recv; + + eth_register (dev); +======= pci_dev_t devbusfn; struct eth_device* dev; u16 command, status; @@ -196,6 +260,7 @@ int pcnet_initialize(bd_t *bis) * Setup the PCI device. */ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); + dev->iobase=pci_io_to_phys(devbusfn,dev->iobase); dev->iobase &= ~0xf; PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", @@ -219,308 +284,311 @@ int pcnet_initialize(bd_t *bis) if (pcnet_probe(dev, bis, dev_nr) < 0) { free(dev); continue; +>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c } - /* - * Setup device structure and register the driver. - */ - dev->init = pcnet_init; - dev->halt = pcnet_halt; - dev->send = pcnet_send; - dev->recv = pcnet_recv; - - eth_register(dev); - } - - udelay(10 * 1000); + udelay (10 * 1000); - return dev_nr; + return dev_nr; } -static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr) +static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) { - int chip_version; - char *chipname; + int chip_version; + char *chipname; + #ifdef PCNET_HAS_PROM - int i; + int i; #endif - /* Reset the PCnet controller */ - pcnet_reset(dev); - - /* Check if register access is working */ - if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { - printf("%s: CSR register access check failed\n", dev->name); - return -1; - } - - /* Identify the chip */ - chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16); - if ((chip_version & 0xfff) != 0x003) - return -1; - chip_version = (chip_version >> 12) & 0xffff; - switch (chip_version) { + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Check if register access is working */ + if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { + printf ("%s: CSR register access check failed\n", dev->name); + return -1; + } + + /* Identify the chip */ + chip_version = + pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); + if ((chip_version & 0xfff) != 0x003) + return -1; + chip_version = (chip_version >> 12) & 0xffff; + switch (chip_version) { + case 0x2621: + chipname = "PCnet/PCI II 79C970A"; /* PCI */ + break; #ifdef CONFIG_PCNET_79C973 - case 0x2625: - chipname = "PCnet/FAST III 79C973"; /* PCI */ - break; + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + break; #endif #ifdef CONFIG_PCNET_79C975 - case 0x2627: - chipname = "PCnet/FAST III 79C975"; /* PCI */ - break; + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + break; #endif - default: - printf("%s: PCnet version %#x not supported\n", - dev->name, chip_version); - return -1; - } + default: + printf ("%s: PCnet version %#x not supported\n", + dev->name, chip_version); + return -1; + } - PCNET_DEBUG1("AMD %s\n", chipname); + PCNET_DEBUG1 ("AMD %s\n", chipname); #ifdef PCNET_HAS_PROM - /* - * In most chips, after a chip reset, the ethernet address is read from - * the station address PROM at the base address and programmed into the - * "Physical Address Registers" CSR12-14. - */ - for (i = 0; i < 3; i++) { - unsigned int val; - val = pcnet_read_csr(dev, i+12) & 0x0ffff; - /* There may be endianness issues here. */ - dev->enetaddr[2*i ] = val & 0x0ff; - dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff; - } + /* + * In most chips, after a chip reset, the ethernet address is read from + * the station address PROM at the base address and programmed into the + * "Physical Address Registers" CSR12-14. + */ + for (i = 0; i < 3; i++) { + unsigned int val; + + val = pcnet_read_csr (dev, i + 12) & 0x0ffff; + /* There may be endianness issues here. */ + dev->enetaddr[2 * i] = val & 0x0ff; + dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; + } #endif /* PCNET_HAS_PROM */ - return 0; + return 0; } -static int pcnet_init(struct eth_device* dev, bd_t *bis) +static int pcnet_init (struct eth_device *dev, bd_t * bis) { - int i, val; - u32 addr; + int i, val; + u32 addr; - PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); + PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); - /* Switch pcnet to 32bit mode */ - pcnet_write_bcr (dev, 20, 2); + /* Switch pcnet to 32bit mode */ + pcnet_write_bcr (dev, 20, 2); #ifdef CONFIG_PN62 - /* Setup LED registers */ - val = pcnet_read_bcr (dev, 2) | 0x1000; - pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ - pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ - pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ - pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ - pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ + /* Setup LED registers */ + val = pcnet_read_bcr (dev, 2) | 0x1000; + pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ + pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ + pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ + pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ + pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ #endif - /* Set/reset autoselect bit */ - val = pcnet_read_bcr (dev, 2) & ~2; - val |= 2; - pcnet_write_bcr (dev, 2, val); - - /* Enable auto negotiate, setup, disable fd */ - val = pcnet_read_bcr(dev, 32) & ~0x98; - val |= 0x20; - pcnet_write_bcr(dev, 32, val); - - /* - * We only maintain one structure because the drivers will never - * be used concurrently. In 32bit mode the RX and TX ring entries - * must be aligned on 16-byte boundaries. - */ - if (lp == NULL) { - addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); - addr = (addr + 0xf) & ~0xf; - lp = (pcnet_priv_t *)addr; - } - - lp->init_block.mode = cpu_to_le16(0x0000); - lp->init_block.filter[0] = 0x00000000; - lp->init_block.filter[1] = 0x00000000; - - /* - * Initialize the Rx ring. - */ - lp->cur_rx = 0; - for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16(0x8000); - PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", - i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, - lp->rx_ring[i].status); - } - - /* - * Initialize the Tx ring. The Tx buffer address is filled in as - * needed, but we do need to clear the upper ownership bit. - */ - lp->cur_tx = 0; - for (i = 0; i < TX_RING_SIZE; i++) { - lp->tx_ring[i].base = 0; - lp->tx_ring[i].status = 0; - } - - /* - * Setup Init Block. - */ - PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); - - for (i = 0; i < 6; i++) { - lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); - } - - lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | - RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); - - PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); - - /* - * Tell the controller where the Init Block is located. - */ - addr = PCI_TO_MEM(dev, &lp->init_block); - pcnet_write_csr(dev, 1, addr & 0xffff); - pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); - - pcnet_write_csr (dev, 4, 0x0915); - pcnet_write_csr (dev, 0, 0x0001); /* start */ - - /* Wait for Init Done bit */ - for (i = 10000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x0100) - break; - udelay(10); - } - if (i <= 0) { - printf("%s: TIMEOUT: controller init failed\n", dev->name); - pcnet_reset (dev); - return -1; - } + /* Set/reset autoselect bit */ + val = pcnet_read_bcr (dev, 2) & ~2; + val |= 2; + pcnet_write_bcr (dev, 2, val); - /* - * Finally start network controller operation. - */ - pcnet_write_csr (dev, 0, 0x0002); + /* Enable auto negotiate, setup, disable fd */ + val = pcnet_read_bcr (dev, 32) & ~0x98; + val |= 0x20; + pcnet_write_bcr (dev, 32, val); - return 0; -} + /* + * We only maintain one structure because the drivers will never + * be used concurrently. In 32bit mode the RX and TX ring entries + * must be aligned on 16-byte boundaries. + */ + if (lp == NULL) { + addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); + addr = (addr + 0xf) & ~0xf; + lp = (pcnet_priv_t *) addr; + } -static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) -{ - int i, status; - struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + lp->init_block.mode = cpu_to_le16 (0x0000); + lp->init_block.filter[0] = 0x00000000; + lp->init_block.filter[1] = 0x00000000; - PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); + /* + * Initialize the Rx ring. + */ + lp->cur_rx = 0; + for (i = 0; i < RX_RING_SIZE; i++) { + lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); + lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); + lp->rx_ring[i].status = cpu_to_le16 (0x8000); + PCNET_DEBUG1 + ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, + lp->rx_ring[i].base, lp->rx_ring[i].buf_length, + lp->rx_ring[i].status); + } - /* Wait for completion by testing the OWN bit */ - for (i = 1000; i > 0; i--) { - status = le16_to_cpu(entry->status); - if ((status & 0x8000) == 0) - break; - udelay(100); - PCNET_DEBUG2("."); - } - if (i <= 0) { - printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", - dev->name, lp->cur_tx, status); - pkt_len = 0; - goto failure; - } - - /* - * Setup Tx ring. Caution: the write order is important here, - * set the status with the "ownership" bits last. - */ - status = 0x8300; - entry->length = le16_to_cpu(-pkt_len); - entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE(dev, packet); - entry->status = le16_to_cpu(status); - - /* Trigger an immediate send poll. */ - pcnet_write_csr (dev, 0, 0x0008); - - failure: - if (++lp->cur_tx >= TX_RING_SIZE) + /* + * Initialize the Tx ring. The Tx buffer address is filled in as + * needed, but we do need to clear the upper ownership bit. + */ lp->cur_tx = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + lp->tx_ring[i].base = 0; + lp->tx_ring[i].status = 0; + } - PCNET_DEBUG2("done\n"); - return pkt_len; -} + /* + * Setup Init Block. + */ + PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); -static int pcnet_recv(struct eth_device* dev) -{ - struct pcnet_rx_head *entry; - int pkt_len = 0; - u16 status; + for (i = 0; i < 6; i++) { + lp->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); + } + + lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); + lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); + + PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + lp->init_block.tlen_rlen, + lp->init_block.rx_ring, lp->init_block.tx_ring); - while (1) { - entry = &lp->rx_ring[lp->cur_rx]; /* - * If we own the next entry, it's a new packet. Send it up. + * Tell the controller where the Init Block is located. */ - if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) { - break; + addr = PCI_TO_MEM (dev, &lp->init_block); + pcnet_write_csr (dev, 1, addr & 0xffff); + pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); + + pcnet_write_csr (dev, 4, 0x0915); + pcnet_write_csr (dev, 0, 0x0001); /* start */ + + /* Wait for Init Done bit */ + for (i = 10000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x0100) + break; + udelay (10); } - status >>= 8; - - if (status != 0x03) { /* There was an error. */ - - printf("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1(" (status=0x%x)", status); - if (status & 0x20) printf(" Frame"); - if (status & 0x10) printf(" Overflow"); - if (status & 0x08) printf(" CRC"); - if (status & 0x04) printf(" Fifo"); - printf(" Error\n"); - entry->status &= le16_to_cpu(0x03ff); - - } else { - - pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; - if (pkt_len < 60) { - printf("%s: Rx%d: invalid packet length %d\n", - dev->name, lp->cur_rx, pkt_len); - } else { - NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); - PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]); - } + if (i <= 0) { + printf ("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset (dev); + return -1; } - entry->status |= cpu_to_le16(0x8000); - if (++lp->cur_rx >= RX_RING_SIZE) - lp->cur_rx = 0; - } - return pkt_len; + /* + * Finally start network controller operation. + */ + pcnet_write_csr (dev, 0, 0x0002); + + return 0; } -static void pcnet_halt(struct eth_device* dev) +static int pcnet_send (struct eth_device *dev, volatile void *packet, + int pkt_len) { - int i; + int i, status; + struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + + PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, + packet); + + /* Wait for completion by testing the OWN bit */ + for (i = 1000; i > 0; i--) { + status = le16_to_cpu (entry->status); + if ((status & 0x8000) == 0) + break; + udelay (100); + PCNET_DEBUG2 ("."); + } + if (i <= 0) { + printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); + pkt_len = 0; + goto failure; + } + + /* + * Setup Tx ring. Caution: the write order is important here, + * set the status with the "ownership" bits last. + */ + status = 0x8300; + entry->length = le16_to_cpu (-pkt_len); + entry->misc = 0x00000000; + entry->base = PCI_TO_MEM_LE (dev, packet); + entry->status = le16_to_cpu (status); - PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); + /* Trigger an immediate send poll. */ + pcnet_write_csr (dev, 0, 0x0008); - /* Reset the PCnet controller */ - pcnet_reset (dev); + failure: + if (++lp->cur_tx >= TX_RING_SIZE) + lp->cur_tx = 0; - /* Wait for Stop bit */ - for (i = 1000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x4) - break; - udelay(10); - } - if (i <= 0) { - printf("%s: TIMEOUT: controller reset failed\n", dev->name); - } + PCNET_DEBUG2 ("done\n"); + return pkt_len; } +static int pcnet_recv (struct eth_device *dev) +{ + struct pcnet_rx_head *entry; + int pkt_len = 0; + u16 status; + + while (1) { + entry = &lp->rx_ring[lp->cur_rx]; + /* + * If we own the next entry, it's a new packet. Send it up. + */ + if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { + break; + } + status >>= 8; + + if (status != 0x03) { /* There was an error. */ + + printf ("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1 (" (status=0x%x)", status); + if (status & 0x20) + printf (" Frame"); + if (status & 0x10) + printf (" Overflow"); + if (status & 0x08) + printf (" CRC"); + if (status & 0x04) + printf (" Fifo"); + printf (" Error\n"); + entry->status &= le16_to_cpu (0x03ff); + + } else { + + pkt_len = + (le32_to_cpu (entry->msg_length) & 0xfff) - 4; + if (pkt_len < 60) { + printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); + } else { + NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); + PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, + lp->rx_buf[lp->cur_rx]); + } + } + entry->status |= cpu_to_le16 (0x8000); + + if (++lp->cur_rx >= RX_RING_SIZE) + lp->cur_rx = 0; + } + return pkt_len; +} + +static void pcnet_halt (struct eth_device *dev) +{ + int i; + + PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); + + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Wait for Stop bit */ + for (i = 1000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x4) + break; + udelay (10); + } + if (i <= 0) { + printf ("%s: TIMEOUT: controller reset failed\n", dev->name); + } +} #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 68e45e17b3..7dc33be899 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -182,7 +182,8 @@ fsl_pci_init(struct pci_controller *hose) /* Clear all error indications */ - pci->pme_msg_det = 0xffffffff; + if (bridge) + pci->pme_msg_det = 0xffffffff; pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c index 5c201b3b45..ee0f2e45b1 100644 --- a/drivers/usb/usb_ohci.c +++ b/drivers/usb/usb_ohci.c @@ -86,11 +86,11 @@ * e.g. PCI controllers need this */ #ifdef CFG_OHCI_SWAP_REG_ACCESS -# define readl(a) __swap_32(*((vu_long *)(a))) -# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a)) +# define readl(a) __swap_32(*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) #else -# define readl(a) (*((vu_long *)(a))) -# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) +# define readl(a) (*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) #endif /* CFG_OHCI_SWAP_REG_ACCESS */ #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) @@ -138,28 +138,14 @@ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_a (struct ohci *hc) + { return readl (&hc->regs->roothub.a); } static inline u32 roothub_b (struct ohci *hc) { return readl (&hc->regs->roothub.b); } static inline u32 roothub_status (struct ohci *hc) { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } +static inline u32 roothub_portstatus (struct ohci *hc, int i) + { return readl (&hc->regs->roothub.portstatus[i]); } /* forward declaration */ static int hc_interrupt (void); diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 4f73067251..68b9861d41 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -849,6 +849,7 @@ int video_display_bitmap (ulong bmp_image, int x, int y) if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { printf ("Error: no valid bmp.gz image at %lx\n", bmp_image); + free(dst); return 1; } #else @@ -869,6 +870,10 @@ int video_display_bitmap (ulong bmp_image, int x, int y) if (compression != BMP_BI_RGB) { printf ("Error: compression type %ld not supported\n", compression); +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) + free(dst); +#endif return 1; } |
