diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/armada100_fec.c | 736 | ||||
| -rw-r--r-- | drivers/net/armada100_fec.h | 232 | ||||
| -rw-r--r-- | drivers/net/davinci_emac.c | 12 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.c | 170 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.h | 9 | ||||
| -rw-r--r-- | drivers/net/xilinx_emaclite.c | 85 |
7 files changed, 1148 insertions, 97 deletions
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 39f036ec6d..1f9436053a 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libnet.o COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o +COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c new file mode 100644 index 0000000000..fbf97632c6 --- /dev/null +++ b/drivers/net/armada100_fec.c @@ -0,0 +1,736 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Contributor: Mahavir Jain <mjain@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/types.h> +#include <asm/byteorder.h> +#include <linux/err.h> +#include <linux/mii.h> +#include <asm/io.h> +#include <asm/arch/armada100.h> +#include "armada100_fec.h" + +#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ + +#ifdef DEBUG +static int eth_dump_regs(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + unsigned int i = 0; + + printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr)); + printf("offset: smi, value: 0x%x\n", readl(®s->smi)); + for (i = 0x400; i <= 0x4e4; i += 4) + printf("offset: 0x%x, value: 0x%x\n", + i, readl(ARMD1_FEC_BASE + i)); + return 0; +} +#endif + +static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) +{ + u32 timeout = PHY_WAIT_ITERATIONS; + u32 reg_val; + + while (--timeout) { + reg_val = readl(reg); + if (cond && (reg_val & flag)) + break; + else if (!cond && !(reg_val & flag)) + break; + udelay(PHY_WAIT_MICRO_SECONDS); + } + return !timeout; +} + +static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, + u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + u32 val; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + val = readl(®s->phyadr); + *value = val & 0x1f; + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n", + __func__, phy_addr); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n", + __func__, phy_reg); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); + + /* now wait for the data to be valid */ + if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) { + val = readl(®s->smi); + printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", + __func__, val); + return -1; + } + val = readl(®s->smi); + *value = val & 0xffff; + + return 0; +} + +static int smi_reg_write(const char *devname, + u8 phy_addr, u8 phy_reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { + clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f); + return 0; + } + + /* check parameters */ + if (phy_addr > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__); + return -EINVAL; + } + if (phy_reg > PHY_MASK) { + printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__); + return -EINVAL; + } + + /* wait for the SMI register to become available */ + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); + return -1; + } + + writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff), + ®s->smi); + return 0; +} + +/* + * Abort any transmit and receive operations and put DMA + * in idle state. AT and AR bits are cleared upon entering + * in IDLE state. So poll those bits to verify operation. + */ +static void abortdma(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int delay; + int maxretries = 40; + u32 tmp; + + while (--maxretries) { + writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd); + udelay(100); + + delay = 10; + while (--delay) { + tmp = readl(®s->sdma_cmd); + if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))) + break; + udelay(10); + } + if (delay) + break; + } + + if (!maxretries) + printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__); +} + +static inline u32 nibble_swapping_32_bit(u32 x) +{ + return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); +} + +static inline u32 nibble_swapping_16_bit(u32 x) +{ + return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4); +} + +static inline u32 flip_4_bits(u32 x) +{ + return ((x & 0x01) << 3) | ((x & 0x002) << 1) + | ((x & 0x04) >> 1) | ((x & 0x008) >> 3); +} + +/* + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * Outputs + * return the calculated entry. + */ +static u32 hash_function(u32 mach, u32 macl) +{ + u32 hashresult; + u32 addrh; + u32 addrl; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrhswapped; + u32 addrlswapped; + + addrh = nibble_swapping_16_bit(mach); + addrl = nibble_swapping_32_bit(macl); + + addrhswapped = flip_4_bits(addrh & 0xf) + + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); + + addrlswapped = flip_4_bits(addrl & 0xf) + + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) + + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) + + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) + + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) + + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) + + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) + + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); + + addrh = addrhswapped; + addrl = addrlswapped; + + addr0 = (addrl >> 2) & 0x03f; + addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); + addr2 = (addrl >> 15) & 0x1ff; + addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); + + hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + hashresult = hashresult & 0x07ff; + return hashresult; +} + +/* + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * mach - the 2 most significant bytes of the MAC address. + * macl - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * 0 if success. + * -ENOSPC if table full + */ +static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, + u32 macl, u32 rd, u32 skip, int del) +{ + struct addr_table_entry_t *entry, *start; + u32 newhi; + u32 newlo; + u32 i; + + newlo = (((mach >> 4) & 0xf) << 15) + | (((mach >> 0) & 0xf) << 11) + | (((mach >> 12) & 0xf) << 7) + | (((mach >> 8) & 0xf) << 3) + | (((macl >> 20) & 0x1) << 31) + | (((macl >> 16) & 0xf) << 27) + | (((macl >> 28) & 0xf) << 23) + | (((macl >> 24) & 0xf) << 19) + | (skip << HTESKIP) | (rd << HTERDBIT) + | HTEVALID; + + newhi = (((macl >> 4) & 0xf) << 15) + | (((macl >> 0) & 0xf) << 11) + | (((macl >> 12) & 0xf) << 7) + | (((macl >> 8) & 0xf) << 3) + | (((macl >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + start = (struct addr_table_entry_t *)(darmdfec->htpr); + entry = start + hash_function(mach, macl); + for (i = 0; i < HOP_NUMBER; i++) { + if (!(entry->lo & HTEVALID)) { + break; + } else { + /* if same address put in same position */ + if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) + && (entry->hi == newhi)) + break; + } + if (entry == start + 0x7ff) + entry = start; + else + entry++; + } + + if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && + (entry->hi != newhi) && del) + return 0; + + if (i == HOP_NUMBER) { + if (!del) { + printf("ARMD100 FEC: (%s) table section is full\n", + __func__); + return -ENOSPC; + } else { + return 0; + } + } + + /* + * Update the selected entry + */ + if (del) { + entry->hi = 0; + entry->lo = 0; + } else { + entry->hi = newhi; + entry->lo = newlo; + } + + return 0; +} + +/* + * Create an addressTable entry from MAC address info + * found in the specifed net_device struct + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + */ +static void update_hash_table_mac_address(struct armdfec_device *darmdfec, + u8 *oaddr, u8 *addr) +{ + u32 mach; + u32 macl; + + /* Delete old entry */ + if (oaddr) { + mach = (oaddr[0] << 8) | oaddr[1]; + macl = (oaddr[2] << 24) | (oaddr[3] << 16) | + (oaddr[4] << 8) | oaddr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE); + } + + /* Add new entry */ + mach = (addr[0] << 8) | addr[1]; + macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD); +} + +/* Address Table Initialization */ +static void init_hashtable(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); + writel((u32)darmdfec->htpr, ®s->htpr); +} + +/* + * This detects PHY chip from address 0-31 by reading PHY status + * registers. PHY chip can be connected at any of this address. + */ +static int ethernet_phy_detect(struct eth_device *dev) +{ + u32 val; + u16 tmp, mii_status; + u8 addr; + + for (addr = 0; addr < 32; addr++) { + if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) + /* try next phy */ + continue; + + /* invalid MII status. More validation required here... */ + if (mii_status == 0 || mii_status == 0xffff) + /* try next phy */ + continue; + + if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) + /* try next phy */ + continue; + + val = tmp << 16; + if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) + /* try next phy */ + continue; + + val |= tmp; + + if ((val & 0xfffffff0) != 0) + return addr; + } + return -1; +} + +static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec) +{ + struct rx_desc *p_rx_desc; + int i; + + /* initialize the Rx descriptors ring */ + p_rx_desc = darmdfec->p_rxdesc; + for (i = 0; i < RINGSZ; i++) { + p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rx_desc->buf_size = PKTSIZE_ALIGN; + p_rx_desc->byte_cnt = 0; + p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; + if (i == (RINGSZ - 1)) { + p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; + } else { + p_rx_desc->nxtdesc_p = (struct rx_desc *) + ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc = p_rx_desc->nxtdesc_p; + } + } + darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; +} + +static int armdfec_init(struct eth_device *dev, bd_t *bd) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + int phy_adr; + + armdfec_init_rx_desc_ring(darmdfec); + + /* Disable interrupts */ + writel(0, ®s->im); + writel(0, ®s->ic); + /* Write to ICR to clear interrupts. */ + writel(0, ®s->iwc); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Initialize address hash table */ + init_hashtable(dev); + + /* SDMA configuration */ + writel(SDCR_BSZ8 | /* Burst size = 32 bytes */ + SDCR_RIFB | /* Rx interrupt on frame */ + SDCR_BLMT | /* Little endian transmit */ + SDCR_BLMR | /* Little endian receive */ + SDCR_RC_MAX_RETRANS, /* Max retransmit count */ + ®s->sdma_conf); + /* Port Configuration */ + writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */ + + /* Set extended port configuration */ + writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */ + PCXR_DSCP_EN | /* Enable DSCP in IP */ + PCXR_MFL_1536 | /* Set MTU = 1536 */ + PCXR_FLP | /* do not force link pass */ + PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ + ®s->pconf_ext); + + update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); + + /* Update TX and RX queue descriptor register */ + writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]); + writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]); + writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]); + + /* Enable Interrupts */ + writel(ALL_INTS, ®s->im); + + /* Enable Ethernet Port */ + setbits_le32(®s->pconf, PCR_EN); + + /* Enable RX DMA engine */ + setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); + +#ifdef DEBUG + eth_dump_regs(dev); +#endif + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) + +#if defined(CONFIG_PHY_BASE_ADR) + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR); +#else + /* Search phy address from range 0-31 */ + phy_adr = ethernet_phy_detect(dev); + if (phy_adr < 0) { + printf("ARMD100 FEC: PHY not detected at address range 0-31\n"); + return -1; + } else { + debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr); + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr); + } +#endif + +#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) + /* Wait up to 5s for the link status */ + for (i = 0; i < 5; i++) { + u16 phy_adr; + + miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); + /* Return if we get link up */ + if (miiphy_link(dev->name, phy_adr)) + return 0; + udelay(1000000); + } + + printf("ARMD100 FEC: No link on %s\n", dev->name); + return -1; +#endif +#endif + return 0; +} + +static void armdfec_halt(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + + /* Stop RX DMA */ + clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); + + /* + * Abort any transmit and receive operations and put DMA + * in idle state. + */ + abortdma(dev); + + /* Disable interrupts */ + writel(0, ®s->im); + writel(0, ®s->ic); + writel(0, ®s->iwc); + + /* Disable Port */ + clrbits_le32(®s->pconf, PCR_EN); +} + +static int armdfec_send(struct eth_device *dev, volatile void *dataptr, + int datasize) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct armdfec_reg *regs = darmdfec->regs; + struct tx_desc *p_txdesc = darmdfec->p_txdesc; + void *p = (void *)dataptr; + int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; + u32 cmd_sts; + + /* Copy buffer if it's misaligned */ + if ((u32)dataptr & 0x07) { + if (datasize > PKTSIZE_ALIGN) { + printf("ARMD100 FEC: Non-aligned data too large (%d)\n", + datasize); + return -1; + } + memcpy(darmdfec->p_aligned_txbuf, p, datasize); + p = darmdfec->p_aligned_txbuf; + } + + p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; + p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; + p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; + p_txdesc->cmd_sts |= TX_EN_INT; + p_txdesc->buf_ptr = p; + p_txdesc->byte_cnt = datasize; + + /* Apply send command using high priority TX queue */ + writel((u32)p_txdesc, ®s->txcdp[TXQ]); + writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd); + + /* + * wait for packet xmit completion + */ + cmd_sts = readl(&p_txdesc->cmd_sts); + while (cmd_sts & BUF_OWNED_BY_DMA) { + /* return fail if error is detected */ + if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == + (TX_ERROR | TX_LAST_DESC)) { + printf("ARMD100 FEC: (%s) in xmit packet\n", __func__); + return -1; + } + cmd_sts = readl(&p_txdesc->cmd_sts); + if (!(retry--)) { + printf("ARMD100 FEC: (%s) xmit packet timeout!\n", + __func__); + return -1; + } + } + + return 0; +} + +static int armdfec_recv(struct eth_device *dev) +{ + struct armdfec_device *darmdfec = to_darmdfec(dev); + struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; + u32 cmd_sts; + u32 timeout = 0; + + /* wait untill rx packet available or timeout */ + do { + if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) { + timeout++; + } else { + debug("ARMD100 FEC: %s time out...\n", __func__); + return -1; + } + } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); + + if (p_rxdesc_curr->byte_cnt != 0) { + debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x" + "(cmd_sts= %08x)\n", __func__, + (u32)p_rxdesc_curr->byte_cnt, + (u32)p_rxdesc_curr->buf_ptr, + (u32)p_rxdesc_curr->cmd_sts); + } + + /* + * In case received a packet without first/last bits on + * OR the error summary bit is on, + * the packets needs to be dropeed. + */ + cmd_sts = readl(&p_rxdesc_curr->cmd_sts); + + if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != + (RX_FIRST_DESC | RX_LAST_DESC)) { + printf("ARMD100 FEC: (%s) Dropping packet spread on" + " multiple descriptors\n", __func__); + } else if (cmd_sts & RX_ERROR) { + printf("ARMD100 FEC: (%s) Dropping packet with errors\n", + __func__); + } else { + /* !!! call higher layer processing */ + debug("ARMD100 FEC: (%s) Sending Received packet to" + " upper layer (NetReceive)\n", __func__); + + /* + * let the upper layer handle the packet, subtract offset + * as two dummy bytes are added in received buffer see + * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit. + */ + NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), + (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); + } + /* + * free these descriptors and point next in the ring + */ + p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; + p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; + p_rxdesc_curr->byte_cnt = 0; + + writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr); + + return 0; +} + +int armada100_fec_register(unsigned long base_addr) +{ + struct armdfec_device *darmdfec; + struct eth_device *dev; + + darmdfec = malloc(sizeof(struct armdfec_device)); + if (!darmdfec) + goto error; + + memset(darmdfec, 0, sizeof(struct armdfec_device)); + + darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); + if (!darmdfec->htpr) + goto error1; + + darmdfec->p_rxdesc = memalign(PKTALIGN, + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); + + if (!darmdfec->p_rxdesc) + goto error1; + + darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1); + if (!darmdfec->p_rxbuf) + goto error1; + + darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); + if (!darmdfec->p_aligned_txbuf) + goto error1; + + darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1); + if (!darmdfec->p_txdesc) + goto error1; + + dev = &darmdfec->dev; + /* Assign ARMADA100 Fast Ethernet Controller Base Address */ + darmdfec->regs = (void *)base_addr; + + /* must be less than NAMESIZE (16) */ + strcpy(dev->name, "armd-fec0"); + + dev->init = armdfec_init; + dev->halt = armdfec_halt; + dev->send = armdfec_send; + dev->recv = armdfec_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, smi_reg_read, smi_reg_write); +#endif + return 0; + +error1: + free(darmdfec->p_aligned_txbuf); + free(darmdfec->p_rxbuf); + free(darmdfec->p_rxdesc); + free(darmdfec->htpr); +error: + free(darmdfec); + printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__); + return -1; +} diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h new file mode 100644 index 0000000000..e2df4fcb87 --- /dev/null +++ b/drivers/net/armada100_fec.h @@ -0,0 +1,232 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Contributor: Mahavir Jain <mjain@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_FEC_H__ +#define __ARMADA100_FEC_H__ + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define PORT_NUM 0x0 + +/* RX & TX descriptor command */ +#define BUF_OWNED_BY_DMA (1<<31) + +/* RX descriptor status */ +#define RX_EN_INT (1<<23) +#define RX_FIRST_DESC (1<<17) +#define RX_LAST_DESC (1<<16) +#define RX_ERROR (1<<15) + +/* TX descriptor command */ +#define TX_EN_INT (1<<23) +#define TX_GEN_CRC (1<<22) +#define TX_ZERO_PADDING (1<<18) +#define TX_FIRST_DESC (1<<17) +#define TX_LAST_DESC (1<<16) +#define TX_ERROR (1<<15) + +/* smi register */ +#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ +#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ +#define SMI_OP_W (0<<26) /* Write operation */ +#define SMI_OP_R (1<<26) /* Read operation */ + +#define HASH_ADD 0 +#define HASH_DELETE 1 +#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ +#define HOP_NUMBER 12 + +#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ +#define PHY_WAIT_MICRO_SECONDS 10 + +#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ +#define ETH_EXTRA_HEADER (6+6+2+4) + /* dest+src addr+protocol id+crc */ +#define MAX_PKT_SIZE 1536 + + +/* Bit definitions of the SDMA Config Reg */ +#define SDCR_BSZ_OFF 12 +#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF) +#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF) +#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF) +#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF) +#define SDCR_BLMR (1<<6) +#define SDCR_BLMT (1<<7) +#define SDCR_RIFB (1<<9) +#define SDCR_RC_OFF 2 +#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) + +/* SDMA_CMD */ +#define SDMA_CMD_AT (1<<31) +#define SDMA_CMD_TXDL (1<<24) +#define SDMA_CMD_TXDH (1<<23) +#define SDMA_CMD_AR (1<<15) +#define SDMA_CMD_ERD (1<<7) + + +/* Bit definitions of the Port Config Reg */ +#define PCR_HS (1<<12) +#define PCR_EN (1<<7) +#define PCR_PM (1<<0) + +/* Bit definitions of the Port Config Extend Reg */ +#define PCXR_2BSM (1<<28) +#define PCXR_DSCP_EN (1<<21) +#define PCXR_MFL_1518 (0<<14) +#define PCXR_MFL_1536 (1<<14) +#define PCXR_MFL_2048 (2<<14) +#define PCXR_MFL_64K (3<<14) +#define PCXR_FLP (1<<11) +#define PCXR_PRIO_TX_OFF 3 +#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF) + +/* + * * Bit definitions of the Interrupt Cause Reg + * * and Interrupt MASK Reg is the same + * */ +#define ICR_RXBUF (1<<0) +#define ICR_TXBUF_H (1<<2) +#define ICR_TXBUF_L (1<<3) +#define ICR_TXEND_H (1<<6) +#define ICR_TXEND_L (1<<7) +#define ICR_RXERR (1<<8) +#define ICR_TXERR_H (1<<10) +#define ICR_TXERR_L (1<<11) +#define ICR_TX_UDR (1<<13) +#define ICR_MII_CH (1<<28) + +#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ + ICR_TXERR_H | ICR_TXERR_L |\ + ICR_TXEND_H | ICR_TXEND_L |\ + ICR_RXBUF | ICR_RXERR | ICR_MII_CH) + +#define PHY_MASK 0x0000001f + +#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev) +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \ + (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN) + +#define RX_BUF_OFFSET 0x2 +#define RXQ 0x0 /* RX Queue 0 */ +#define TXQ 0x1 /* TX Queue 1 */ + +struct addr_table_entry_t { + u32 lo; + u32 hi; +}; + +/* Bit fields of a Hash Table Entry */ +enum hash_table_entry { + HTEVALID = 1, + HTESKIP = 2, + HTERD = 4, + HTERDBIT = 2 +}; + +struct tx_desc { + u32 cmd_sts; /* Command/status field */ + u16 reserved; + u16 byte_cnt; /* buffer byte count */ + u8 *buf_ptr; /* pointer to buffer for this descriptor */ + struct tx_desc *nextdesc_p; /* Pointer to next descriptor */ +}; + +struct rx_desc { + u32 cmd_sts; /* Descriptor command status */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u16 buf_size; /* Buffer size */ + u8 *buf_ptr; /* Descriptor buffer pointer */ + struct rx_desc *nxtdesc_p; /* Next descriptor pointer */ +}; + +/* + * Armada100 Fast Ethernet controller Registers + * Refer Datasheet Appendix A.22 + */ +struct armdfec_reg { + u32 phyadr; /* PHY Address */ + u32 pad1[3]; + u32 smi; /* SMI */ + u32 pad2[0xFB]; + u32 pconf; /* Port configuration */ + u32 pad3; + u32 pconf_ext; /* Port configuration extend */ + u32 pad4; + u32 pcmd; /* Port Command */ + u32 pad5; + u32 pstatus; /* Port Status */ + u32 pad6; + u32 spar; /* Serial Parameters */ + u32 pad7; + u32 htpr; /* Hash table pointer */ + u32 pad8; + u32 fcsal; /* Flow control source address low */ + u32 pad9; + u32 fcsah; /* Flow control source address high */ + u32 pad10; + u32 sdma_conf; /* SDMA configuration */ + u32 pad11; + u32 sdma_cmd; /* SDMA command */ + u32 pad12; + u32 ic; /* Interrupt cause */ + u32 iwc; /* Interrupt write to clear */ + u32 im; /* Interrupt mask */ + u32 pad13; + u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code + Point to Priority 0 Low */ + u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */ + u32 pad14[3]; + struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor + Pointer */ + u32 pad15[4]; + struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor + Pointer */ + u32 pad16[0x0C]; + struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor + Pointer */ +}; + +struct armdfec_device { + struct eth_device dev; + struct armdfec_reg *regs; + struct tx_desc *p_txdesc; + struct rx_desc *p_rxdesc; + struct rx_desc *p_rxdesc_curr; + u8 *p_rxbuf; + u8 *p_aligned_txbuf; + u8 *htpr; /* hash pointer */ +}; + +#endif /* __ARMADA100_FEC_H__ */ diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index c0b8929258..a8905b88f1 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -680,6 +680,9 @@ int davinci_emac_initialize(void) davinci_eth_mdio_enable(); + /* let the EMAC detect the PHYs */ + udelay(5000); + for (i = 0; i < 256; i++) { if (readl(&adap_mdio->ALIVE)) break; @@ -711,6 +714,13 @@ int davinci_emac_initialize(void) phy_id |= tmp & 0x0000ffff; switch (phy_id) { + case PHY_KSZ8873: + sprintf(phy.name, "KSZ8873 @ 0x%02x", active_phy_addr); + phy.init = ksz8873_init_phy; + phy.is_phy_connected = ksz8873_is_phy_connected; + phy.get_link_speed = ksz8873_get_link_speed; + phy.auto_negotiate = ksz8873_auto_negotiate; + break; case PHY_LXT972: sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); phy.init = lxt972_init_phy; @@ -740,7 +750,7 @@ int davinci_emac_initialize(void) phy.auto_negotiate = gen_auto_negotiate; } - printf("Ethernet PHY: %s\n", phy.name); + debug("Ethernet PHY: %s\n", phy.name); miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); return(1); diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ab90afa41e..cfe2176b33 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -38,6 +38,10 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE MII100 +#endif + #undef DEBUG struct nbuf { @@ -47,18 +51,6 @@ struct nbuf { uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ }; -struct fec_priv gfec = { - .eth = (struct ethernet_regs *)IMX_FEC_BASE, - .xcv_type = MII100, - .rbd_base = NULL, - .rbd_index = 0, - .tbd_base = NULL, - .tbd_index = 0, - .bd = NULL, - .rdb_ptr = NULL, - .base_ptr = NULL, -}; - /* * MII-interface related functions */ @@ -67,6 +59,7 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, { struct eth_device *edev = eth_get_dev_by_name(dev); struct fec_priv *fec = (struct fec_priv *)edev->priv; + struct ethernet_regs *eth = fec->eth; uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ @@ -76,18 +69,18 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, * reading from any PHY's register is done by properly * programming the FEC's MII data register. */ - writel(FEC_IEVENT_MII, &fec->eth->ievent); + writel(FEC_IEVENT_MII, ð->ievent); reg = regAddr << FEC_MII_DATA_RA_SHIFT; phy = phyAddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | - phy | reg, &fec->eth->mii_data); + phy | reg, ð->mii_data); /* * wait for the related interrupt */ start = get_timer(0); - while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { + while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Read MDIO failed...\n"); return -1; @@ -97,12 +90,12 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * clear mii interrupt bit */ - writel(FEC_IEVENT_MII, &fec->eth->ievent); + writel(FEC_IEVENT_MII, ð->ievent); /* * it's now safe to read the PHY's register */ - *retVal = readl(&fec->eth->mii_data); + *retVal = readl(ð->mii_data); debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, regAddr, *retVal); return 0; @@ -117,13 +110,14 @@ static void fec_mii_setspeed(struct fec_priv *fec) writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, &fec->eth->mii_speed); debug("fec_init: mii_speed %#lx\n", - fec->eth->mii_speed); + readl(&fec->eth->mii_speed)); } static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, uint16_t data) { struct eth_device *edev = eth_get_dev_by_name(dev); struct fec_priv *fec = (struct fec_priv *)edev->priv; + struct ethernet_regs *eth = fec->eth; uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ @@ -133,13 +127,13 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, phy = phyAddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | - FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data); + FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); /* * wait for the MII interrupt */ start = get_timer(0); - while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { + while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Write MDIO failed...\n"); return -1; @@ -149,7 +143,7 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * clear MII interrupt bit */ - writel(FEC_IEVENT_MII, &fec->eth->ievent); + writel(FEC_IEVENT_MII, ð->ievent); debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, regAddr, data); @@ -158,33 +152,40 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, static int miiphy_restart_aneg(struct eth_device *dev) { + struct fec_priv *fec = (struct fec_priv *)dev->priv; + int ret = 0; + /* * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ #ifdef CONFIG_MX27 - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF); + miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); #endif - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + miiphy_write(dev->name, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); /* * Set the auto-negotiation advertisement register bits */ - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE, + miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3); - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + miiphy_write(dev->name, fec->phy_id, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); - return 0; + if (fec->mii_postcall) + ret = fec->mii_postcall(fec->phy_id); + + return ret; } static int miiphy_wait_aneg(struct eth_device *dev) { uint32_t start; uint16_t status; + struct fec_priv *fec = (struct fec_priv *)dev->priv; /* * Wait for AN completion @@ -196,7 +197,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) return -1; } - if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, + if (miiphy_read(dev->name, fec->phy_id, MII_BMSR, &status)) { printf("%s: Autonegotiation failed. status: 0x%04x\n", dev->name, status); @@ -384,8 +385,8 @@ static int fec_open(struct eth_device *edev) #endif miiphy_wait_aneg(edev); - miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); - miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); + miiphy_speed(edev->name, fec->phy_id); + miiphy_duplex(edev->name, fec->phy_id); /* * Enable SmartDMA receive task @@ -400,6 +401,9 @@ static int fec_init(struct eth_device *dev, bd_t* bd) { uint32_t base; struct fec_priv *fec = (struct fec_priv *)dev->priv; + uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; + uint32_t rcntrl; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); @@ -442,19 +446,21 @@ static int fec_init(struct eth_device *dev, bd_t* bd) /* * Set FEC-Lite receive control register(R_CNTRL): */ - if (fec->xcv_type == SEVENWIRE) { - /* - * Frame length=1518; 7-wire mode - */ - writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */ - } else { - /* - * Frame length=1518; MII mode; - */ - writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ + /* Start with frame length = 1518, common for all modes. */ + rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; + if (fec->xcv_type == SEVENWIRE) + rcntrl |= FEC_RCNTRL_FCE; + else if (fec->xcv_type == RMII) + rcntrl |= FEC_RCNTRL_RMII; + else /* MII mode */ + rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; + + writel(rcntrl, &fec->eth->r_cntrl); + + if (fec->xcv_type == MII10 || fec->xcv_type == MII100) fec_mii_setspeed(fec); - } + /* * Set Opcode/Pause Duration Register */ @@ -468,9 +474,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd) /* clear MIB RAM */ - long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200); - while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC)) - *mib_ptr++ = 0; + for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) + writel(0, i); /* FIFO receive start register */ writel(0x520, &fec->eth->r_fstart); @@ -504,7 +509,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) */ static void fec_halt(struct eth_device *dev) { - struct fec_priv *fec = &gfec; + struct fec_priv *fec = (struct fec_priv *)dev->priv; int counter = 0xffff; /* @@ -685,19 +690,32 @@ static int fec_recv(struct eth_device *dev) return len; } -static int fec_probe(bd_t *bd) +static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) { struct eth_device *edev; - struct fec_priv *fec = &gfec; + struct fec_priv *fec; unsigned char ethaddr[6]; + uint32_t start; + int ret = 0; /* create and fill edev struct */ edev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!edev) { - puts("fec_mxc: not enough malloc memory\n"); - return -ENOMEM; + puts("fec_mxc: not enough malloc memory for eth_device\n"); + ret = -ENOMEM; + goto err1; + } + + fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); + if (!fec) { + puts("fec_mxc: not enough malloc memory for fec_priv\n"); + ret = -ENOMEM; + goto err2; } + memset(edev, 0, sizeof(*edev)); + memset(fec, 0, sizeof(*fec)); + edev->priv = fec; edev->init = fec_init; edev->send = fec_send; @@ -705,15 +723,21 @@ static int fec_probe(bd_t *bd) edev->halt = fec_halt; edev->write_hwaddr = fec_set_hwaddr; - fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; + fec->eth = (struct ethernet_regs *)base_addr; fec->bd = bd; - fec->xcv_type = MII100; + fec->xcv_type = CONFIG_FEC_XCV_TYPE; /* Reset chip. */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); - while (readl(&fec->eth->ecntrl) & 1) + start = get_timer(0); + while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("FEC MXC: Timeout reseting chip\n"); + goto err3; + } udelay(10); + } /* * Set interrupt mask register @@ -731,29 +755,63 @@ static int fec_probe(bd_t *bd) /* * Frame length=1518; MII mode; */ - writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */ + writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | + FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); fec_mii_setspeed(fec); - sprintf(edev->name, "FEC"); + if (dev_id == -1) { + sprintf(edev->name, "FEC"); + fec->dev_id = 0; + } else { + sprintf(edev->name, "FEC%i", dev_id); + fec->dev_id = dev_id; + } + fec->phy_id = phy_id; miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); eth_register(edev); if (fec_get_hwaddr(edev, ethaddr) == 0) { - printf("got MAC address from fuse: %pM\n", ethaddr); + debug("got MAC address from fuse: %pM\n", ethaddr); memcpy(edev->enetaddr, ethaddr, 6); } - return 0; + return ret; + +err3: + free(fec); +err2: + free(edev); +err1: + return ret; } +#ifndef CONFIG_FEC_MXC_MULTI int fecmxc_initialize(bd_t *bd) { int lout = 1; debug("eth_init: fec_probe(bd)\n"); - lout = fec_probe(bd); + lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); return lout; } +#endif + +int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) +{ + int lout = 1; + + debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); + lout = fec_probe(bd, dev_id, phy_id, addr); + + return lout; +} + +int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) +{ + struct fec_priv *fec = (struct fec_priv *)dev->priv; + fec->mii_postcall = cb; + return 0; +} diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 1ba51617dd..8b26645173 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -32,6 +32,8 @@ #ifndef __FEC_MXC_H #define __FEC_MXC_H +void imx_get_mac_from_fuse(unsigned char *mac); + /** * Layout description of the FEC */ @@ -194,6 +196,7 @@ struct ethernet_regs { #define FEC_RCNTRL_PROM 0x00000008 #define FEC_RCNTRL_BC_REJ 0x00000010 #define FEC_RCNTRL_FCE 0x00000020 +#define FEC_RCNTRL_RMII 0x00000100 #define FEC_TCNTRL_GTS 0x00000001 #define FEC_TCNTRL_HBC 0x00000002 @@ -257,7 +260,8 @@ struct fec_bd { enum xceiver_type { SEVENWIRE, /* 7-wire */ MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ + MII100, /* MII 100Mbps */ + RMII /* RMII */ }; /** @@ -273,6 +277,9 @@ struct fec_priv { bd_t *bd; void *rdb_ptr; void *base_ptr; + int dev_id; + int phy_id; + int (*mii_postcall)(int); }; /** diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 3c7c2501cb..8e574cd7ca 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -63,14 +63,10 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL -typedef struct { - u32 baseaddress; /* Base address for device (IPIF) */ +struct xemaclite { u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ - uchar deviceid; /* Unique ID of device - for future */ -} xemaclite; - -static xemaclite emaclite; +}; static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ @@ -136,44 +132,44 @@ static void emaclite_halt(struct eth_device *dev) static int emaclite_init(struct eth_device *dev, bd_t *bis) { debug ("EmacLite Initialization Started\n"); - memset (&emaclite, 0, sizeof (xemaclite)); - emaclite.baseaddress = dev->iobase; /* * TX - TX_PING & TX_PONG initialization */ /* Restart PING TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); + out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); /* Copy MAC address */ xemaclite_alignedwrite (dev->enetaddr, - emaclite.baseaddress, ENET_ADDR_LENGTH); + dev->iobase, ENET_ADDR_LENGTH); /* Set the length */ - out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); /* Update the MAC address in the EMAC Lite */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) & - XEL_TSR_PROG_MAC_ADDR) != 0) ; + while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & + XEL_TSR_PROG_MAC_ADDR) != 0) + ; #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG /* The same operation with PONG TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress + + out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); + xemaclite_alignedwrite(dev->enetaddr, dev->iobase + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, + out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; + while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) + ; #endif /* * RX - RX_PING & RX_PONG initialization */ /* Write out the value to flush the RX buffer */ - out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, + out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, XEL_RSR_RECV_IE_MASK); #endif @@ -181,22 +177,24 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) return 0; } -static int xemaclite_txbufferavailable (xemaclite *instanceptr) +static int xemaclite_txbufferavailable(struct eth_device *dev) { u32 reg; u32 txpingbusy; u32 txpongbusy; + struct xemaclite *emaclite = dev->priv; + /* * Read the other buffer register * and determine if the other buffer is available */ - reg = in_be32 (instanceptr->baseaddress + - instanceptr->nexttxbuffertouse + 0); + reg = in_be32 (dev->iobase + + emaclite->nexttxbuffertouse + 0); txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == XEL_TSR_XMIT_BUSY_MASK); - reg = in_be32 (instanceptr->baseaddress + - (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); + reg = in_be32 (dev->iobase + + (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == XEL_TSR_XMIT_BUSY_MASK); @@ -207,13 +205,14 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) { u32 reg; u32 baseaddress; + struct xemaclite *emaclite = dev->priv; u32 maxtry = 1000; if (len > ENET_MAX_MTU) len = ENET_MAX_MTU; - while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { + while (!xemaclite_txbufferavailable(dev) && maxtry) { udelay (10); maxtry--; } @@ -221,16 +220,16 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) if (!maxtry) { printf ("Error: Timeout waiting for ethernet TX buffer\n"); /* Restart PING TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); + out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + + out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); #endif return -1; } /* Determine the expected TX buffer address */ - baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse); + baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); /* Determine if the expected buffer address is empty */ reg = in_be32 (baseaddress + XEL_TSR_OFFSET); @@ -239,7 +238,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; + emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; #endif debug ("Send packet from 0x%x\n", baseaddress); /* Write the frame to the buffer */ @@ -262,7 +261,7 @@ static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - debug ("Send packet from 0x%x\n", baseaddress); + debug("Send packet from 0x%x\n", baseaddress); /* Write the frame to the buffer */ xemaclite_alignedwrite ((void *) ptr, baseaddress, len); out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & @@ -285,13 +284,14 @@ static int emaclite_recv(struct eth_device *dev) u32 length; u32 reg; u32 baseaddress; + struct xemaclite *emaclite = dev->priv; - baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; + baseaddress = dev->iobase + emaclite->nextrxbuffertouse; reg = in_be32 (baseaddress + XEL_RSR_OFFSET); debug ("Testing data at address 0x%x\n", baseaddress); if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; + emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; #endif } else { #ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG @@ -344,16 +344,23 @@ static int emaclite_recv(struct eth_device *dev) int xilinx_emaclite_initialize (bd_t *bis, int base_addr) { struct eth_device *dev; + struct xemaclite *emaclite; - dev = malloc(sizeof(*dev)); + dev = calloc(1, sizeof(*dev)); if (dev == NULL) return -1; - memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "Xilinx_Emaclite"); + emaclite = calloc(1, sizeof(struct xemaclite)); + if (emaclite == NULL) { + free(dev); + return -1; + } + + dev->priv = emaclite; + + sprintf(dev->name, "Xelite.%x", base_addr); dev->iobase = base_addr; - dev->priv = 0; dev->init = emaclite_init; dev->halt = emaclite_halt; dev->send = emaclite_send; |
