diff options
Diffstat (limited to 'board')
45 files changed, 1163 insertions, 2178 deletions
diff --git a/board/friendlyarm/mini2440/Makefile b/board/armltd/vexpress64/Makefile index f3671071b5..e009141a42 100644 --- a/board/friendlyarm/mini2440/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -1,8 +1,8 @@ # -# (C) Copyright 2012 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -obj-y := mini2440.o +obj-y := vexpress64.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c new file mode 100644 index 0000000000..2ec3bc9835 --- /dev/null +++ b/board/armltd/vexpress64/vexpress64.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2013 + * David Feng <fenghua@phytium.com.cn> + * Sharma Bhupesh <bhupesh.sharma@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index 0388226db4..cfc64fe51d 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -10,6 +10,7 @@ #include <netdev.h> #include <asm/blackfin.h> #include <asm/io.h> +#include <asm/sdh.h> #include <asm/portmux.h> #include "soft_switch.h" diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg index 577dabf1d2..597d3914ca 100644 --- a/board/freescale/b4860qds/b4_rcw.cfg +++ b/board/freescale/b4860qds/b4_rcw.cfg @@ -2,6 +2,6 @@ aa55aa55 010e0100 # serdes protocol 0x2A_0x98 140e0018 0f001218 00000000 00000000 -54980000 9000a000 f8025000 a9000000 +54980000 9000a000 e8104000 a9000000 01000000 00000000 00000000 0001b1f8 00000000 14000020 00000000 00000011 diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 669fe8ad32..c8ecf5de59 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 02655e9baf..07febc2b37 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile index 889c4938c0..1f399d2496 100644 --- a/board/freescale/common/p_corenet/Makefile +++ b/board/freescale/common/p_corenet/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-y += law.o obj-$(CONFIG_PCI) += pci.o obj-y += tlb.o diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a7af0f6756..a3d36b35d5 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 966abb24a6..5f3d6fd28b 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -354,7 +354,7 @@ int board_eth_init(bd_t *bis) puts("No address specified for VSC7385 microcode.\n"); #endif - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 624398a25d..10b1a6d179 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -3,7 +3,7 @@ 09010000 00200400 09138000 00000000 091380c0 00000100 -#Configure CPC1 as 512KB SRAM +#Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 09010f00 08000000 diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 2aa176c7a2..de3ea5c2aa 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -239,3 +239,8 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } + +int board_need_mem_reset(void) +{ + return 1; +} diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c deleted file mode 100644 index 59ed0548e7..0000000000 --- a/board/friendlyarm/mini2440/mini2440.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2009 - * Michel Pollet <buserror@gmail.com> - * - * (C) Copyright 2012 - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/s3c2440.h> -#include <asm/arch/iomux.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <netdev.h> -#include "mini2440.h" - -DECLARE_GLOBAL_DATA_PTR; - -static inline void pll_delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_early_init_f(void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ - clk_power->clkdivn = CLKDIVN_VAL; - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - /* some delay between MPLL and UPLL */ - pll_delay(100); - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - pll_delay(10000); - - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* IOMUX Port H : UART Configuration */ - gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | - IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; - - gpio_direction_output(GPH8, 0); - gpio_direction_output(GPH9, 0); - gpio_direction_output(GPH10, 0); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; - - return 0; -} - -int dram_init(void) -{ - struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); - - /* - * Configuring bus width and timing - * Initialize clocks for each bank 0..5 - * Bank 3 and 4 are used for DM9000 - */ - writel(BANK_CONF, &memctl->bwscon); - writel(B0_CONF, &memctl->bankcon[0]); - writel(B1_CONF, &memctl->bankcon[1]); - writel(B2_CONF, &memctl->bankcon[2]); - writel(B3_CONF, &memctl->bankcon[3]); - writel(B4_CONF, &memctl->bankcon[4]); - writel(B5_CONF, &memctl->bankcon[5]); - - /* Bank 6 and 7 are used for DRAM */ - writel(SDRAM_64MB, &memctl->bankcon[6]); - writel(SDRAM_64MB, &memctl->bankcon[7]); - - writel(MEM_TIMING, &memctl->refresh); - writel(BANKSIZE_CONF, &memctl->banksize); - writel(B6_MRSR, &memctl->mrsrb6); - writel(B7_MRSR, &memctl->mrsrb7); - - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_DRIVER_DM9000 - return dm9000_initialize(bis); -#else - return 0; -#endif -} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h deleted file mode 100644 index db386eac01..0000000000 --- a/board/friendlyarm/mini2440/mini2440.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef __MINI2440_BOARD_CONF_H__ -#define __MINI2440_BOARD_CONF_H__ - -/* PLL Parameters */ -#define CLKDIVN_VAL 7 -#define M_MDIV 0x7f -#define M_PDIV 0x2 -#define M_SDIV 0x1 - -#define U_M_MDIV 0x38 -#define U_M_PDIV 0x2 -#define U_M_SDIV 0x2 - -/* BWSCON */ -#define DW8 0x0 -#define DW16 0x1 -#define DW32 0x2 -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* - * Bank Configuration - */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* 0clk */ -#define B0_PMC 0x0 /* normal */ - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x3 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x1 -#define B4_Tah 0x3 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0x0 -#define B5_Tcos 0x0 -#define B5_Tacc 0x7 -#define B5_Tcoh 0x0 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -/* - * SDRAM Configuration - */ -#define SDRAM_MT 0x3 /* SDRAM */ -#define SDRAM_Trcd 0x0 /* 2clk */ -#define SDRAM_SCAN_9 0x1 /* 9bit */ -#define SDRAM_SCAN_10 0x2 /* 10bit */ - -#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) - -/* - * Refresh Parameter - */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x0 /* unused */ -#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ - -/* - * MRSR Parameter - */ -#define BL 0x0 -#define BT 0x0 -#define CL 0x3 /* 3 clocks */ -#define TM 0x0 -#define WBL 0x0 - -/* - * BankSize Parameter - */ -#define BK76MAP 0x2 /* 128MB/128MB */ -#define SCLK_EN 0x1 /* SCLK active */ -#define SCKE_EN 0x1 /* SDRAM power down mode enable */ -#define BURST_EN 0x1 /* Burst enable */ - -/* - * Register values - */ -#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ - (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ - (B7_BWSCON<<28))) - -#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ - (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) -#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ - (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) -#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ - (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) -#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ - (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) -#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ - (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) -#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ - (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) - -#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ - (Trc<<18) + (Tchr<<16) + REFCNT - -#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) -#define B6_MRSR (CL<<4) -#define B7_MRSR (CL<<4) - -#endif diff --git a/board/linkstation/Makefile b/board/linkstation/Makefile deleted file mode 100644 index 3eeba7dcaa..0000000000 --- a/board/linkstation/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = linkstation.o ide.o hwctl.o avr.o diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c deleted file mode 100644 index 62e586ba09..0000000000 --- a/board/linkstation/avr.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * avr.c - * - * AVR functions - * - * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <ns16550.h> -#include <stdio_dev.h> - -/* Button codes from the AVR */ -#define PWRR 0x20 /* Power button release */ -#define PWRP 0x21 /* Power button push */ -#define RESR 0x22 /* Reset button release */ -#define RESP 0x23 /* Reset button push */ -#define AVRINIT 0x33 /* Init complete */ -#define AVRRESET 0x31 /* Reset request */ - -/* LED commands */ -#define PWRBLINKSTRT '[' /* Blink power LED */ -#define PWRBLINKSTOP 'Z' /* Solid power LED */ -#define HDDLEDON 'W' /* HDD LED on */ -#define HDDLEDOFF 'V' /* HDD LED off */ -#define HDDBLINKSTRT 'Y' /* HDD LED start blink */ -#define HDDBLINKSTOP 'X' /* HDD LED stop blink */ - -/* Timings for LEDs blinking to show choice */ -#define PULSETIME 250 /* msecs */ -#define LONGPAUSE (5 * PULSETIME) - -/* Button press times */ -#define PUSHHOLD 1000 /* msecs */ -#define NOBUTTON (6 * (LONGPAUSE+PULSETIME)) - -/* Boot and console choices */ -#define MAX_BOOT_CHOICE 3 - -static char *consoles[] = { - "serial", -#if defined(CONFIG_NETCONSOLE) - "nc", -#endif -}; -#define MAX_CONS_CHOICE (sizeof(consoles)/sizeof(char *)) - -#if !defined(CONFIG_NETCONSOLE) -#define DEF_CONS_CHOICE 0 -#else -#define DEF_CONS_CHOICE 1 -#endif - -#define perror(fmt, args...) printf("%s: " fmt, __FUNCTION__ , ##args) - -extern void miconCntl_SendCmd(unsigned char dat); -extern void miconCntl_DisWDT(void); - -static int boot_stop; - -static int boot_choice = 1; -static int cons_choice = DEF_CONS_CHOICE; - -static char envbuffer[16]; - -void init_AVR_DUART (void) -{ - NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2; - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600; - - /* - * AVR port init sequence taken from - * the original Linkstation init code - * Normal U-Boot serial reinit doesn't - * work because the AVR uses even parity - */ - AVR_port->lcr = 0x00; - AVR_port->ier = 0x00; - AVR_port->lcr = UART_LCR_BKSE; - AVR_port->dll = clock_divisor & 0xff; - AVR_port->dlm = (clock_divisor >> 8) & 0xff; - AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS; - AVR_port->mcr = 0x00; - AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR; - - miconCntl_DisWDT(); - - boot_stop = 0; - miconCntl_SendCmd(PWRBLINKSTRT); -} - -static inline int avr_tstc(void) -{ - return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2)); -} - -static inline char avr_getc(void) -{ - return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2)); -} - -static int push_timeout(char button_code) -{ - ulong push_start = get_timer(0); - while (get_timer(push_start) <= PUSHHOLD) - if (avr_tstc() && avr_getc() == button_code) - return 0; - return 1; -} - -static void next_boot_choice(void) -{ - ulong return_start; - ulong pulse_start; - int on_times; - int button_on; - int led_state; - char c; - - button_on = 0; - return_start = get_timer(0); - - on_times = boot_choice; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - - while (get_timer(return_start) <= NOBUTTON || button_on) { - if (avr_tstc()) { - c = avr_getc(); - if (c == PWRP) - button_on = 1; - else if (c == PWRR) { - button_on = 0; - return_start = get_timer(0); - if (++boot_choice > MAX_BOOT_CHOICE) - boot_choice = 1; - sprintf(envbuffer, "bootcmd%d", boot_choice); - if (getenv(envbuffer)) { - sprintf(envbuffer, "run bootcmd%d", boot_choice); - setenv("bootcmd", envbuffer); - } - on_times = boot_choice; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - } else { - perror("Unexpected code: 0x%02X\n", c); - } - } - if (on_times && get_timer(pulse_start) > PULSETIME) { - if (led_state == 1) { - --on_times; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - } else { - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - } - pulse_start = get_timer(0); - } - if (!on_times && get_timer(pulse_start) > LONGPAUSE) { - on_times = boot_choice; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - } - } - if (led_state) - miconCntl_SendCmd(HDDLEDOFF); -} - -void next_cons_choice(int console) -{ - ulong return_start; - ulong pulse_start; - int on_times; - int button_on; - int led_state; - char c; - - button_on = 0; - cons_choice = console; - return_start = get_timer(0); - - on_times = cons_choice+1; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - pulse_start = get_timer(0); - - while (get_timer(return_start) <= NOBUTTON || button_on) { - if (avr_tstc()) { - c = avr_getc(); - if (c == RESP) - button_on = 1; - else if (c == RESR) { - button_on = 0; - return_start = get_timer(0); - cons_choice = (cons_choice + 1) % MAX_CONS_CHOICE; - console_assign(stdin, consoles[cons_choice]); - console_assign(stdout, consoles[cons_choice]); - console_assign(stderr, consoles[cons_choice]); - on_times = cons_choice+1; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - } else { - perror("Unexpected code: 0x%02X\n", c); - } - } - if (on_times && get_timer(pulse_start) > PULSETIME) { - if (led_state == 0) { - --on_times; - led_state = 1; - miconCntl_SendCmd(HDDLEDON); - } else { - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - } - pulse_start = get_timer(0); - } - if (!on_times && get_timer(pulse_start) > LONGPAUSE) { - on_times = cons_choice+1; - led_state = 0; - miconCntl_SendCmd(HDDLEDOFF); - pulse_start = get_timer(0); - } - } - if (led_state); - miconCntl_SendCmd(HDDLEDOFF); -} - -int avr_input(void) -{ - char avr_button; - - if (!avr_tstc()) - return 0; - - avr_button = avr_getc(); - switch (avr_button) { - case PWRP: - if (push_timeout(PWRR)) { - /* Timeout before power button release */ - boot_stop = ~boot_stop; - if (boot_stop) - miconCntl_SendCmd(PWRBLINKSTOP); - else - miconCntl_SendCmd(PWRBLINKSTRT); - /* Wait for power button release */ - while (avr_getc() != PWRR) - ; - } else - /* Power button released */ - next_boot_choice(); - break; - case RESP: - /* Wait for Reset button release */ - while (avr_getc() != RESR) - ; - next_cons_choice(cons_choice); - break; - case AVRINIT: - return 0; - default: - perror("Unexpected code: 0x%02X\n", avr_button); - return 0; - } - if (boot_stop) - return (-3); - else - return (-2); -} - -void avr_StopBoot(void) -{ - boot_stop = ~0; - miconCntl_SendCmd(PWRBLINKSTOP); -} diff --git a/board/linkstation/hwctl.c b/board/linkstation/hwctl.c deleted file mode 100644 index d2090be1ad..0000000000 --- a/board/linkstation/hwctl.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * hwctl.c - * - * LinkStation HW Control Driver - * - * Copyright (C) 2001-2004 BUFFALO INC. - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL), incorporated herein by reference. - * Drivers based on or derived from this code fall under the GPL and must - * retain the authorship, copyright and license notice. This file is not - * a complete program and may only be used when the entire operating - * system is licensed under the GPL. - * - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/io.h> - -#define AVR_PORT CONFIG_SYS_NS16550_COM2 - -/* 2005.5.10 BUFFALO add */ -/*--------------------------------------------------------------*/ -static inline void miconCntl_SendUart(unsigned char dat) -{ - out_8((unsigned char *)AVR_PORT, dat); - mdelay(1); -} - -/*--------------------------------------------------------------*/ -void miconCntl_SendCmd(unsigned char dat) -{ - int i; - - for (i=0; i<4; i++){ - miconCntl_SendUart(dat); - } -} - -/*--------------------------------------------------------------*/ -void miconCntl_FanLow(void) -{ -#ifdef CONFIG_HTGL - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -void miconCntl_FanHigh(void) -{ -#ifdef CONFIG_HTGL - miconCntl_SendCmd(0x5D); -#endif -} - -/*--------------------------------------------------------------*/ -/* 1000Mbps */ -void miconCntl_Eth1000M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x93); - else - miconCntl_SendCmd(0x92); -#else - if (up) - miconCntl_SendCmd(0x5D); - else - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* 100Mbps */ -void miconCntl_Eth100M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x91); - else - miconCntl_SendCmd(0x90); -#else - if (up) - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* 10Mbps */ -void miconCntl_Eth10M(int up) -{ -#ifdef CONFIG_HTGL - if (up) - miconCntl_SendCmd(0x8F); - else - miconCntl_SendCmd(0x8E); -#else - if (up) - miconCntl_SendCmd(0x5C); -#endif -} - -/*--------------------------------------------------------------*/ -/* */ -void miconCntl_5f(void) -{ - miconCntl_SendCmd(0x5F); - mdelay(100); -} - -/*--------------------------------------------------------------*/ -/* "reboot start" signal */ -void miconCntl_Reboot(void) -{ - miconCntl_SendCmd(0x43); -} - -/*--------------------------------------------------------------*/ -/* Disable watchdog timer */ -void miconCntl_DisWDT(void) -{ - miconCntl_SendCmd(0x41); /* A */ - miconCntl_SendCmd(0x46); /* F */ - miconCntl_SendCmd(0x4A); /* J */ - miconCntl_SendCmd(0x3E); /* > */ - miconCntl_SendCmd(0x56); /* V */ - miconCntl_SendCmd(0x3E); /* > */ - miconCntl_SendCmd(0x5A); /* Z */ - miconCntl_SendCmd(0x56); /* V */ - miconCntl_SendCmd(0x4B); /* K */ -} diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c deleted file mode 100644 index 7b3fe65cff..0000000000 --- a/board/linkstation/ide.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* ide.c - ide support functions */ - - -#include <common.h> - -#ifdef CONFIG_CMD_IDE -#include <ata.h> -#include <ide.h> -#include <pci.h> - -#define IT8212_PCI_CpuCONTROL 0x5e -#define IT8212_PCI_PciModeCONTROL 0x50 -#define IT8212_PCI_IdeIoCONFIG 0x40 -#define IT8212_PCI_IdeBusSkewCONTROL 0x4c -#define IT8212_PCI_IdeDrivingCURRENT 0x42 - -extern struct pci_controller hose; - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0); - if (devbusfn == -1) - devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0); - if (devbusfn != -1) { - u32 ide_bus_offset32; - - status = 0; - - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - &ide_bus_offset32); - ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe; - ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[0] & 0xfffffffe, - PCI_REGION_IO); - if (CONFIG_SYS_IDE_MAXBUS > 1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) &ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[1] & 0xfffffffe, - PCI_REGION_IO); - } - } - - if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) { - pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01); - pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00); - pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047); -#ifdef CONFIG_IT8212_SECONDARY_ENABLE - pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3); -#else - pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031); -#endif - pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204); -/* __LS_COMMENT__ BUFFALO changed 2004.11.10 changed for EMI */ - pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */ - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00); - } - - return (status); -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* CONFIG_CMD_IDE */ diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c deleted file mode 100644 index 75cda8681f..0000000000 --- a/board/linkstation/linkstation.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linkstation.c - * - * Misc LinkStation specific functions - * - * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <version.h> -#include <mpc824x.h> -#include <asm/io.h> -#include <ns16550.h> -#include <netdev.h> - -#ifdef CONFIG_PCI -#include <pci.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern void init_AVR_DUART(void); - -int checkboard (void) -{ - char *p; - bd_t *bd = gd->bd; - - init_AVR_DUART(); - - if ((p = getenv ("console_nr")) != NULL) { - unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; - } - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE)); -} - -/* - * Initialize PCI Devices - */ -#ifdef CONFIG_PCI - -#ifndef CONFIG_PCI_PNP - -static struct pci_config_table pci_linkstation_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0b, 0, /* AN983B or RTL8110S */ - /* ethernet controller */ - pci_cfgfunc_config_device, { PCI_ETH_IOADDR, - PCI_ETH_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0c, 0, /* SII680 or IT8211AF */ - /* ide controller */ - pci_cfgfunc_config_device, { PCI_IDE_IOADDR, - PCI_IDE_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ - pci_cfgfunc_config_device, { PCI_USB0_IOADDR, - PCI_USB0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ - pci_cfgfunc_config_device, { PCI_USB1_IOADDR, - PCI_USB1_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ - pci_cfgfunc_config_device, { PCI_USB2_IOADDR, - PCI_USB2_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_linkstation_config_table, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); - - /* Reset USB 1.1 */ - /* Haven't seen any change without these on a HG, maybe it is - * needed on other models */ - out_le32((volatile unsigned*)(PCI_USB0_MEMADDR + 8), 1); - out_le32((volatile unsigned*)(PCI_USB1_MEMADDR + 8), 1); -} -#endif /* CONFIG_PCI */ - -#define UART_DCR 0x80004511 -int board_early_init_f (void) -{ - /* set DUART mode */ - out_8((volatile u8*)UART_DCR, 1); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile deleted file mode 100644 index 8ec5f25613..0000000000 --- a/board/logicpd/zoom2/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := zoom2.o -obj-y += debug_board.o -obj-y += zoom2_serial.o -obj-$(CONFIG_STATUS_LED) += led.o diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk deleted file mode 100644 index 1c382f7189..0000000000 --- a/board/logicpd/zoom2/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, <www.ti.com> -# -# Zoom II uses OMAP3 (ARM-CortexA8) CPU -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 0x80000000 (bank0) -# 0xA0000000 (bank1) -# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c deleted file mode 100644 index 071f41074b..0000000000 --- a/board/logicpd/zoom2/debug_board.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/mux.h> -#include <asm/gpio.h> - -#define DEBUG_BOARD_CONNECTED 1 -#define DEBUG_BOARD_NOT_CONNECTED 0 - -static int debug_board_connected = DEBUG_BOARD_CONNECTED; - -static void zoom2_debug_board_detect (void) -{ - int val = 0; - - if (!gpio_request(158, "")) { - /* - * GPIO to query for debug board - * 158 db board query - */ - gpio_direction_input(158); - val = gpio_get_value(158); - } - - if (!val) - debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; -} - -int zoom2_debug_board_connected (void) -{ - static int first_time = 1; - - if (first_time) { - zoom2_debug_board_detect (); - first_time = 0; - } - return debug_board_connected; -} diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c deleted file mode 100644 index 5d37ac15f2..0000000000 --- a/board/logicpd/zoom2/led.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <status_led.h> -#include <asm/arch/cpu.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> - -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - -/* - * GPIO LEDs - * 173 red - * 154 blue - * 61 blue2 - */ -#define ZOOM2_LED_RED 173 -#define ZOOM2_LED_BLUE 154 -#define ZOOM2_LED_BLUE2 61 - -void red_led_off(void) -{ - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 0); - } - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void blue_led_off(void) -{ - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 0); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 0); - } - saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; -} - -void red_led_on(void) -{ - blue_led_off(); - - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 1); - } - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void blue_led_on(void) -{ - red_led_off(); - - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 1); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 1); - } - - saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; -} - -void __led_init (led_id_t mask, int state) -{ - __led_set (mask, state); -} - -void __led_toggle (led_id_t mask) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) - blue_led_off(); - else - blue_led_on(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - } -} - -void __led_set (led_id_t mask, int state) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == state) - blue_led_on(); - else - blue_led_off(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - } -} diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c deleted file mode 100644 index e14de04695..0000000000 --- a/board/logicpd/zoom2/zoom2.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * Derived from Zoom1 code by - * Nishanth Menon <nm@ti.com> - * Sunil Kumar <sunilsaini05@gmail.com> - * Shashi Ranjan <shashiranjanmca05@gmail.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <netdev.h> -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#include <twl4030.h> -#include <asm/io.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/gpio.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include "zoom2.h" -#include "zoom2_serial.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This the the zoom2, board specific, gpmc configuration for the - * quad uart on the debug board. The more general gpmc configurations - * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c - * - * The details of the setting of the serial gpmc setup are not available. - * The values were provided by another party. - */ -static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { - 0x00011000, - 0x001F1F01, - 0x00080803, - 0x1D091D09, - 0x041D1F1F, - 0x1D0904C4, 0 -}; - -/* Used to track the revision of the board */ -static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN; - -/* - * Routine: zoom2_get_revision - * Description: Return the revision of the Zoom2 this code is running on. - */ -zoom2_revision zoom2_get_revision(void) -{ - return revision; -} - -/* - * Routine: zoom2_identify - * Description: Detect which version of Zoom2 we are running on. - */ -void zoom2_identify(void) -{ - /* - * To check for production board vs beta board, - * check if gpio 94 is clear. - * - * No way yet to check for alpha board identity. - * Alpha boards were produced in very limited quantities - * and they are not commonly used. They are mentioned here - * only for completeness. - */ - if (!gpio_request(94, "")) { - unsigned int val; - - gpio_direction_input(94); - val = gpio_get_value(94); - - if (val) - revision = ZOOM2_REVISION_BETA; - else - revision = ZOOM2_REVISION_PRODUCTION; - } - - printf("Board revision "); - switch (revision) { - case ZOOM2_REVISION_PRODUCTION: - printf("Production\n"); - break; - case ZOOM2_REVISION_BETA: - printf("Beta\n"); - break; - default: - printf("Unknown\n"); - break; - } -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init (void) -{ - u32 *gpmc_config; - - gpmc_init (); /* in SRAM or SDRAM, finish GPMC */ - - /* Configure console support on zoom2 */ - gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], - SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); - - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); -#endif - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure zoom board specific configurations - */ -int misc_init_r(void) -{ - zoom2_identify(); - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - dieid_num_r(); - - /* - * Board Reset - * The board is reset by holding the the large button - * on the top right side of the main board for - * eight seconds. - * - * There are reported problems of some beta boards - * continously resetting. For those boards, disable resetting. - */ - if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision()) - twl4030_power_reset_init(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs (void) -{ - /* platform specific muxes */ - MUX_ZOOM2 (); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h deleted file mode 100644 index 850c790a08..0000000000 --- a/board/logicpd/zoom2/zoom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * Derived from: board/omap3/zoom1/zoom1.h - * Nishanth Menon <nm@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _BOARD_ZOOM2_H_ -#define _BOARD_ZOOM2_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Zoom2 ", - "NAND", -}; - -typedef enum { - ZOOM2_REVISION_UNKNOWN = 0, - ZOOM2_REVISION_ALPHA, - ZOOM2_REVISION_BETA, - ZOOM2_REVISION_PRODUCTION -} zoom2_revision; - -zoom2_revision zoom2_get_revision(void); - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ZOOM2() \ - /* SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ -/* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ -/* IDCC modem Power On */\ - MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ - MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ -/* GPMC CS7 has LAN9211 device */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ -/* GPMC CS3 has Serial TL16CP754C device */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ -/* Toggle Reset pin of TL16CP754C device */\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ - udelay(10);\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ -/* LEDS */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */ - -#endif /* _BOARD_ZOOM2_H_ */ diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c deleted file mode 100644 index 2959276116..0000000000 --- a/board/logicpd/zoom2/zoom2_serial.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c - */ - -#include <common.h> -#include <serial.h> -#include <ns16550.h> -#include <asm/arch/cpu.h> -#include "zoom2_serial.h" - -int quad_init_dev (unsigned long base) -{ - /* - * The Quad UART is on the debug board. - * Check if the debug board is attached before using the UART - */ - if (zoom2_debug_board_connected ()) { - NS16550_t com_port = (NS16550_t) base; - int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - /* - * Zoom2 has a board specific initialization of its UART. - * This generic initialization has been copied from - * drivers/serial/ns16550.c. The macros have been expanded. - * - * Do the following instead of - * - * NS16550_init (com_port, clock_divisor); - */ - com_port->ier = 0x00; - - /* - * On Zoom2 board Set pre-scalar to 1 - * CLKSEL is GND => MCR[7] is 1 => preslr is 4 - * So change the prescl to 1 - */ - com_port->lcr = 0xBF; - com_port->fcr |= 0x10; - com_port->mcr &= 0x7F; - - /* This is generic ns16550.c setup */ - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCR_8N1; - com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; - com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | - UART_FCR_TXSR; - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCR_8N1; - } - /* - * We have to lie here, otherwise the board init code will hang - * on the check - */ - return 0; -} - -void quad_putc_dev (unsigned long base, const char c) -{ - if (zoom2_debug_board_connected ()) { - - if (c == '\n') - quad_putc_dev (base, '\r'); - - NS16550_putc ((NS16550_t) base, c); - } else { - usbtty_putc(c); - } -} - -void quad_puts_dev (unsigned long base, const char *s) -{ - if (zoom2_debug_board_connected ()) { - while ((s != NULL) && (*s != '\0')) - quad_putc_dev (base, *s++); - } else { - usbtty_puts(s); - } -} - -int quad_getc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_getc ((NS16550_t) base); - - return usbtty_getc(); -} - -int quad_tstc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_tstc ((NS16550_t) base); - - return usbtty_tstc(); -} - -void quad_setbrg_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) { - - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - NS16550_reinit ((NS16550_t) base, clock_divisor); - } -} - -QUAD_INIT (0) -QUAD_INIT (1) -QUAD_INIT (2) -QUAD_INIT (3) - -struct serial_device *default_serial_console(void) -{ - switch (ZOOM2_DEFAULT_SERIAL_DEVICE) { - case 0: return &zoom2_serial_device0; - case 1: return &zoom2_serial_device1; - case 2: return &zoom2_serial_device2; - case 3: return &zoom2_serial_device3; - } -} diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h deleted file mode 100644 index 82244521ac..0000000000 --- a/board/logicpd/zoom2/zoom2_serial.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ZOOM2_SERIAL_H -#define ZOOM2_SERIAL_H - -#include <linux/stringify.h> - -extern int zoom2_debug_board_connected (void); - -#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ - -#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE -#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) -#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) -#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) - -#define QUAD_INIT(n) \ -int quad_init_##n(void) \ -{ \ - return quad_init_dev(QUAD_BASE_##n); \ -} \ -void quad_setbrg_##n(void) \ -{ \ - quad_setbrg_dev(QUAD_BASE_##n); \ -} \ -void quad_putc_##n(const char c) \ -{ \ - quad_putc_dev(QUAD_BASE_##n, c); \ -} \ -void quad_puts_##n(const char *s) \ -{ \ - quad_puts_dev(QUAD_BASE_##n, s); \ -} \ -int quad_getc_##n(void) \ -{ \ - return quad_getc_dev(QUAD_BASE_##n); \ -} \ -int quad_tstc_##n(void) \ -{ \ - return quad_tstc_dev(QUAD_BASE_##n); \ -} \ -struct serial_device zoom2_serial_device##n = \ -{ \ - .name = __stringify(n), \ - .start = quad_init_##n, \ - .stop = NULL, \ - .setbrg = quad_setbrg_##n, \ - .getc = quad_getc_##n, \ - .tstc = quad_tstc_##n, \ - .putc = quad_putc_##n, \ - .puts = quad_puts_##n, \ -}; - -#endif /* ZOOM2_SERIAL_H */ diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile deleted file mode 100644 index 6dfd18e202..0000000000 --- a/board/mx1ads/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# board/mx1ads/Makefile -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu <minglen_wu@techware.com.tw> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := mx1ads.o syncflash.o -obj-y += lowlevel_init.o diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S deleted file mode 100644 index d1e472a933..0000000000 --- a/board/mx1ads/lowlevel_init.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * board/mx1ads/lowlevel_init.S - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#define SDCTL0 0x221000 -#define SDCTL1 0x221004 - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: -/* memory controller init */ - - ldr r1, =SDCTL0 - -/* Set Precharge Command */ - - ldr r3, =0x92120200 -/* ldr r3, =0x92120251 -*/ - str r3, [r1] - -/* Issue Precharge All Commad */ - ldr r3, =0x8200000 - ldr r2, [r3] - -/* Set AutoRefresh Command */ - ldr r3, =0xA2120200 - str r3, [r1] - -/* Issue AutoRefresh Command */ - ldr r3, =0x8000000 - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - -/* Set Mode Register */ - ldr r3, =0xB2120200 - str r3, [r1] - -/* Issue Mode Register Command */ - ldr r3, =0x08111800 /* Mode Register Value */ - ldr r2, [r3] - -/* Set Normal Mode */ - ldr r3, =0x82124200 - str r3, [r1] - -/* everything is fine now */ - mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c deleted file mode 100644 index 4266048981..0000000000 --- a/board/mx1ads/mx1ads.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * board/mx1ads/mx1ads.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -/*#include <mc9328.h>*/ -#include <asm/arch/imx-regs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -#if 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -#endif - -/* - * Miscellaneous platform dependent initialisations - */ - -void SetAsynchMode (void) -{ - __asm__ ("mrc p15,0,r0,c1,c0,0 \n" - "mov r2, #0xC0000000 \n" - "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); -} - -static u32 mc9328sid; - -int board_early_init_f(void) -{ - mc9328sid = SIDR; - - GPCR = 0x000003AB; /* I/O pad driving strength */ - - /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ -/* MX1_CS1L = 0x11110601; */ - - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ - -/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and - * BCLK divider to 2 (i.e. BCLK to 48 MHz) - */ - CSCR = 0xAF000403; - - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ - -/* setup cs4 for cs8900 ethernet */ - - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ - CS4L = 0x00001501; - - GIUS (0) &= 0xFF3FFFFF; - GPR (0) &= 0xFF3FFFFF; - - readl(0x1500000C); - readl(0x1500000C); - - SetAsynchMode (); - - icache_enable (); - dcache_enable (); - -/* set PERCLKs */ - PCDR = 0x00000055; /* set PERCLKS */ - -/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes - * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place - * all sources selected as normal interrupt - */ - -/* MX1_INTTYPEH = 0; - MX1_INTTYPEL = 0; -*/ - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - - return 0; -} - -int board_late_init (void) -{ - - setenv ("stdout", "serial"); - setenv ("stderr", "serial"); - - switch (mc9328sid) { - case 0x0005901d: - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x04d4c01d: - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x00d4c01d: - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - - default: - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", - mc9328sid); - break; - } - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c deleted file mode 100644 index 5d685338fb..0000000000 --- a/board/mx1ads/syncflash.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * board/mx1ads/syncflash.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -/*#include <mc9328.h>*/ -#include <asm/arch/imx-regs.h> - -typedef unsigned long * p_u32; - -/* 4Mx16x2 IAM=0 CSD1 */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) - -#define SYNCFLASH_A10 (0x00100000) - -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) - -#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ - -/* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ - -/* Get Status register */ -u32 SF_SR(void) { - u32 tmp; - - reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CONFIG_SYS_FLASH_BASE); - - reg_SFCTL = CMD_NORMAL; - - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); - - return tmp; -} - -/* check if SyncFlash is ready */ -u8 SF_Ready(void) { - u32 tmp; - - tmp = SF_SR(); - - if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if (tmp == 0x00800080) /* Test Bit 7 of SR */ - return 1; - else - return 0; -} - -/* Issue the precharge all command */ -void SF_PrechargeAll(void) { - - /* Set Precharge Command */ - reg_SFCTL = CMD_PREC; - /* Issue Precharge All Command */ - __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); -} - -/* set SyncFlash to normal mode */ -void SF_Normal(void) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_NORMAL; -} - -/* Erase SyncFlash */ -void SF_Erase(u32 RowAddress) { - - reg_SFCTL = CMD_NORMAL; - __REG(RowAddress); - - reg_SFCTL = CMD_PREC; - __REG(RowAddress); - - reg_SFCTL = CMD_LCR; /* Set LCR mode */ - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ - - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeErase(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeWrite(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ -} - -/****************************************************************************************/ - -ulong flash_init(void) { - int i, j; - -/* Turn on CSD1 for negating RESETSF of SyncFLash */ - - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ - udelay(200); - - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ - - SF_Normal(); - - i = 0; - - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; - } - - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t *info) { - - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_MT & FLASH_VENDMASK): - printf("Micron: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): - printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses: "); - - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - int iflag, cflag, prot, sect; - int rc = ERR_OK; - -/* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("protected!\n"); - return ERR_PROTECTED; - } -/* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - -/* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - -/* arm simple, non interrupt dependent timer */ - - get_timer(0); - - SF_NvmodeErase(); - SF_NvmodeWrite(); - - SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); - SF_Normal(); - - printf("ok.\n"); - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - int i; - - for(i = 0; i < cnt; i += 4) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ - __REG(addr + i) = __REG((u32)src + i); - - while(!SF_Ready()); - } - - SF_Normal(); - - return ERR_OK; -} diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile new file mode 100644 index 0000000000..f7c8e949f9 --- /dev/null +++ b/board/renesas/sh7753evb/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := sh7753evb.o spi-boot.o +obj-y += lowlevel_init.o diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S new file mode 100644 index 0000000000..21987a51e8 --- /dev/null +++ b/board/renesas/sh7753evb/lowlevel_init.S @@ -0,0 +1,416 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +.macro or32, addr, data + mov.l \addr, r1 + mov.l \data, r0 + mov.l @r1, r2 + or r2, r0 + mov.l r0, @r1 +.endm + +.macro wait_DBCMD + mov.l DBWAIT_A, r0 + mov.l @r0, r1 +.endm + + .global lowlevel_init + .section .spiboot1.text + .align 2 + +lowlevel_init: + mov #0, r14 + mova 2f, r0 + mov.l PC_MASK, r1 + tst r0, r1 + bf 2f + + bra exit_pmb + nop + + .align 2 + +/* If CPU runs on SDRAM (PC=0x5???????) or not. */ +PC_MASK: .long 0x20000000 + +2: + mov #1, r14 + + mov.l EXPEVT_A, r0 + mov.l @r0, r0 + mov.l EXPEVT_POWER_ON_RESET, r1 + cmp/eq r0, r1 + bt 1f + + /* + * If EXPEVT value is manual reset or tlb multipul-hit, + * initialization of DBSC3 is not necessary. + */ + bra exit_ddr + nop + +1: + /*------- Reset -------*/ + write32 MRSTCR0_A, MRSTCR0_D + write32 MRSTCR1_A, MRSTCR1_D + + /* For Core Reset */ + mov.l DBACEN_A, r0 + mov.l @r0, r0 + cmp/eq #0, r0 + bt 3f + + /* + * If DBACEN == 1(DBSC was already enabled), we have to avoid the + * initialization of DDR3-SDRAM. + */ + bra exit_ddr + nop + +3: + /*------- DBSC3 -------*/ + /* oscillation stabilization time */ + wait_timer WAIT_OSC_TIME + + /* step 3 */ + write32 DBKIND_A, DBKIND_D + + /* step 4 */ + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBTR4_A, DBTR4_D + write32 DBTR5_A, DBTR5_D + write32 DBTR6_A, DBTR6_D + write32 DBTR7_A, DBTR7_D + write32 DBTR8_A, DBTR8_D + write32 DBTR9_A, DBTR9_D + write32 DBTR10_A, DBTR10_D + write32 DBTR11_A, DBTR11_D + write32 DBTR12_A, DBTR12_D + write32 DBTR13_A, DBTR13_D + write32 DBTR14_A, DBTR14_D + write32 DBTR15_A, DBTR15_D + write32 DBTR16_A, DBTR16_D + write32 DBTR17_A, DBTR17_D + write32 DBTR18_A, DBTR18_D + write32 DBTR19_A, DBTR19_D + write32 DBRNK0_A, DBRNK0_D + write32 DBADJ0_A, DBADJ0_D + write32 DBADJ2_A, DBADJ2_D + + /* step 5 */ + write32 DBCMD_A, DBCMD_RSTL_VAL + wait_timer WAIT_30US + + /* step 6 */ + write32 DBCMD_A, DBCMD_PDEN_VAL + + /* step 7 */ + write32 DBPDCNT3_A, DBPDCNT3_D + + /* step 8 */ + write32 DBPDCNT1_A, DBPDCNT1_D + write32 DBPDCNT2_A, DBPDCNT2_D + write32 DBPDLCK_A, DBPDLCK_D + write32 DBPDRGA_A, DBPDRGA_D + write32 DBPDRGD_A, DBPDRGD_D + + /* step 9 */ + wait_timer WAIT_30US + + /* step 10 */ + write32 DBPDCNT0_A, DBPDCNT0_D + + /* step 11 */ + wait_timer WAIT_30US + wait_timer WAIT_30US + + /* step 12 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + wait_DBCMD + + /* step 13 */ + write32 DBCMD_A, DBCMD_RSTH_VAL + wait_DBCMD + + /* step 14 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + + /* step 15 */ + write32 DBCMD_A, DBCMD_PDXT_VAL + + /* step 16 */ + write32 DBCMD_A, DBCMD_MRS2_VAL + + /* step 17 */ + write32 DBCMD_A, DBCMD_MRS3_VAL + + /* step 18 */ + write32 DBCMD_A, DBCMD_MRS1_VAL + + /* step 19 */ + write32 DBCMD_A, DBCMD_MRS0_VAL + write32 DBPDNCNF_A, DBPDNCNF_D + + /* step 20 */ + write32 DBCMD_A, DBCMD_ZQCL_VAL + + write32 DBCMD_A, DBCMD_REF_VAL + write32 DBCMD_A, DBCMD_REF_VAL + wait_DBCMD + + /* step 21 */ + write32 DBCALTR_A, DBCALTR_D + + /* step 22 */ + write32 DBRFCNF0_A, DBRFCNF0_D + write32 DBRFCNF1_A, DBRFCNF1_D + write32 DBRFCNF2_A, DBRFCNF2_D + + /* step 23 */ + write32 DBCALCNF_A, DBCALCNF_D + + /* step 24 */ + write32 DBRFEN_A, DBRFEN_D + write32 DBCMD_A, DBCMD_SRXT_VAL + + /* step 25 */ + write32 DBACEN_A, DBACEN_D + + /* step 26 */ + wait_DBCMD + + bra exit_ddr + nop + + .align 2 + +EXPEVT_A: .long 0xff000024 +EXPEVT_POWER_ON_RESET: .long 0x00000000 + +/*------- Reset -------*/ +MRSTCR0_A: .long 0xffd50030 +MRSTCR0_D: .long 0xfe1ffe7f +MRSTCR1_A: .long 0xffd50034 +MRSTCR1_D: .long 0xfff3ffff + +/*------- DBSC3 -------*/ +DBCMD_A: .long 0xfe800018 +DBKIND_A: .long 0xfe800020 +DBCONF_A: .long 0xfe800024 +DBTR0_A: .long 0xfe800040 +DBTR1_A: .long 0xfe800044 +DBTR2_A: .long 0xfe800048 +DBTR3_A: .long 0xfe800050 +DBTR4_A: .long 0xfe800054 +DBTR5_A: .long 0xfe800058 +DBTR6_A: .long 0xfe80005c +DBTR7_A: .long 0xfe800060 +DBTR8_A: .long 0xfe800064 +DBTR9_A: .long 0xfe800068 +DBTR10_A: .long 0xfe80006c +DBTR11_A: .long 0xfe800070 +DBTR12_A: .long 0xfe800074 +DBTR13_A: .long 0xfe800078 +DBTR14_A: .long 0xfe80007c +DBTR15_A: .long 0xfe800080 +DBTR16_A: .long 0xfe800084 +DBTR17_A: .long 0xfe800088 +DBTR18_A: .long 0xfe80008c +DBTR19_A: .long 0xfe800090 +DBRNK0_A: .long 0xfe800100 +DBPDCNT0_A: .long 0xfe800200 +DBPDCNT1_A: .long 0xfe800204 +DBPDCNT2_A: .long 0xfe800208 +DBPDCNT3_A: .long 0xfe80020c +DBPDLCK_A: .long 0xfe800280 +DBPDRGA_A: .long 0xfe800290 +DBPDRGD_A: .long 0xfe8002a0 +DBADJ0_A: .long 0xfe8000c0 +DBADJ2_A: .long 0xfe8000c8 +DBRFCNF0_A: .long 0xfe8000e0 +DBRFCNF1_A: .long 0xfe8000e4 +DBRFCNF2_A: .long 0xfe8000e8 +DBCALCNF_A: .long 0xfe8000f4 +DBRFEN_A: .long 0xfe800014 +DBACEN_A: .long 0xfe800010 +DBWAIT_A: .long 0xfe80001c +DBCALTR_A: .long 0xfe8000f8 +DBPDNCNF_A: .long 0xfe800180 + +WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333 + +DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000004 +DBTR8_D: .long 0x00000014 +DBTR9_D: .long 0x00000004 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x000000a0 +DBTR14_D: .long 0x00060006 +DBTR15_D: .long 0x00000003 +DBTR16_D: .long 0x00160002 +DBTR17_D: .long 0x000c0000 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100 + +DBADJ0_D: .long 0x00010000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x00081040 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001 +DBCALTR_D: .long 0x08200820 +DBPDNCNF_D: .long 0x00000001 + + .align 2 +exit_ddr: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + */ + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif /* if defined(CONFIG_SH_32BIT) */ + +exit_pmb: + /* CPU is running on ILRAM? */ + mov r14, r0 + tst #1, r0 + bt 1f + + mov.l _stack_ilram, r15 + mov.l _spiboot_main, r0 +100: bsrf r0 + nop + + .align 2 +_spiboot_main: .long (spiboot_main - (100b + 4)) +_stack_ilram: .long 0xe5204000 + +1: + write32 CCR_A, CCR_D + + rts + nop + + .align 2 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) + +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000 + +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) + +PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c new file mode 100644 index 0000000000..42b920fb33 --- /dev/null +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmc.h> +#include <spi_flash.h> + +int checkboard(void) +{ + puts("BOARD: SH7753 EVB\n"); + + return 0; +} + +static void init_gpio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + struct sermux_regs *sermux = SERMUX_BASE; + + /* GPIO */ + writew(0x0000, &gpio->pacr); /* GETHER */ + writew(0x0001, &gpio->pbcr); /* INTC */ + writew(0x0000, &gpio->pccr); /* PWMU, INTC */ + writew(0x0000, &gpio->pdcr); /* SPI0 */ + writew(0xeaff, &gpio->pecr); /* GPIO */ + writew(0x0000, &gpio->pfcr); /* WDT */ + writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ + writew(0x0000, &gpio->phcr); /* SPI1 */ + writew(0x0000, &gpio->picr); /* SDHI */ + writew(0x0000, &gpio->pjcr); /* SCIF4 */ + writew(0x0003, &gpio->pkcr); /* SerMux */ + writew(0x0000, &gpio->plcr); /* SerMux */ + writew(0x0000, &gpio->pmcr); /* RIIC */ + writew(0x0000, &gpio->pncr); /* USB, SGPIO */ + writew(0x0000, &gpio->pocr); /* SGPIO */ + writew(0xd555, &gpio->pqcr); /* GPIO */ + writew(0x0000, &gpio->prcr); /* RIIC */ + writew(0x0000, &gpio->pscr); /* RIIC */ + writew(0x0000, &gpio->ptcr); /* STATUS */ + writeb(0x00, &gpio->pudr); + writew(0x5555, &gpio->pucr); /* Debug LED */ + writew(0x0000, &gpio->pvcr); /* RSPI */ + writew(0x0000, &gpio->pwcr); /* EVC */ + writew(0x0000, &gpio->pxcr); /* LBSC */ + writew(0x0000, &gpio->pycr); /* LBSC */ + writew(0x0000, &gpio->pzcr); /* eMMC */ + writew(0xfe00, &gpio->psel0); + writew(0x0000, &gpio->psel1); + writew(0x3000, &gpio->psel2); + writew(0xff00, &gpio->psel3); + writew(0x771f, &gpio->psel4); + writew(0x0ffc, &gpio->psel5); + writew(0x00ff, &gpio->psel6); + writew(0xfc00, &gpio->psel7); + + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ +} + +static void init_usb_phy(void) +{ + struct usb_common_regs *common0 = USB0_COMMON_BASE; + struct usb_common_regs *common1 = USB1_COMMON_BASE; + struct usb0_phy_regs *phy = USB0_PHY_BASE; + struct usb1_port_regs *port = USB1_PORT_BASE; + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; + + writew(0x0100, &phy->reset); /* set reset */ + /* port0 = USB0, port1 = USB1 */ + writew(0x0002, &phy->portsel); + writel(0x0001, &port->port1sel); /* port1 = Host */ + writew(0x0111, &phy->reset); /* clear reset */ + + writew(0x4000, &common0->suspmode); + writew(0x4000, &common1->suspmode); + +#if defined(__LITTLE_ENDIAN) + writel(0x00000000, &align->ehcidatac); + writel(0x00000000, &align->ohcidatac); +#endif +} + +static void init_gether_mdio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ +} + +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = GETHER0_MAC_BASE; + else + ether = GETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +/***************************************************************** + * This PMB must be set on this timing. The lowlevel_init is run on + * Area 0(phys 0x00000000), so we have to map it. + * + * The new PMB table is following: + * ent virt phys v sz c wt + * 0 0xa0000000 0x40000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 2 0xb0000000 0x50000000 1 128M 0 1 + * 3 0xb8000000 0x58000000 1 128M 0 1 + * 4 0x80000000 0x40000000 1 128M 1 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + * 6 0x90000000 0x50000000 1 128M 1 1 + * 7 0x98000000 0x58000000 1 128M 1 1 + */ +static void set_pmb_on_board_init(void) +{ + struct mmu_regs *mmu = MMU_BASE; + + /* clear ITLB */ + writel(0x00000004, &mmu->mmucr); + + /* delete PMB for SPIBOOT */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + /* ppn ub v s1 s0 c wt */ + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); +} + +int board_init(void) +{ + struct gether_control_regs *gether = GETHER_CONTROL_BASE; + + init_gpio(); + set_pmb_on_board_init(); + + /* Sets TXnDLY to B'010 */ + writel(0x00000202, &gether->gbecont); + + init_usb_phy(); + init_gether_mdio(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ + udelay(1); + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ + udelay(200); + + return mmcif_mmc_init(); +} + +static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{ + struct spi_flash *spi; + int ret; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (spi == NULL) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); + if (ret) { + printf("%s: spi_flash read failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{ + memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], + SH7753EVB_ETHERNET_MAC_SIZE); + mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ + + return 0; +} + +static void init_ethernet_mac(void) +{ + char mac_string[64]; + char env_string[64]; + int i; + unsigned char *buf; + + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return; + } + get_sh_eth_mac_raw(buf, 256); + + /* Gigabit Ethernet */ + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i == 0) + setenv("ethaddr", mac_string); + else { + sprintf(env_string, "eth%daddr", i); + setenv(env_string, mac_string); + } + set_mac_to_sh_giga_eth_register(i, mac_string); + } + + free(buf); +} + +int board_late_init(void) +{ + init_ethernet_mac(); + + return 0; +} + +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i, ret; + char mac_string[256]; + struct spi_flash *spi; + unsigned char *buf; + + if (argc != 3) { + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return 1; + } + + get_sh_eth_mac_raw(buf, 256); + + /* print current MAC address */ + for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + printf("GETHERC ch%d = %s\n", i, mac_string); + } + free(buf); + return 0; + } + + /* new setting */ + memset(mac_string, 0xff, sizeof(mac_string)); + sprintf(mac_string, "%s\t%s", + argv[1], argv[2]); + + /* write MAC data to SPI rom */ + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, + SH7753EVB_SPI_SECTOR_SIZE); + if (ret) { + printf("%s: spi_flash erase failed.\n", __func__); + return 1; + } + + ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, + sizeof(mac_string), mac_string); + if (ret) { + printf("%s: spi_flash write failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + puts("The writing of the MAC address to SPI ROM was completed.\n"); + + return 0; +} + +U_BOOT_CMD( + write_mac, 3, 1, do_write_mac, + "write MAC address for GETHERC", + "[GETHERC ch0] [GETHERC ch1]\n" +); diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c new file mode 100644 index 0000000000..21903d9c7b --- /dev/null +++ b/board/renesas/sh7753evb/spi-boot.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2013 Renesas Solutions Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#define CONFIG_SPI_ADDR 0x00000000 +#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000) +#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE) + +#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190 + +#define SPIDMINTSR_DMEND 0x00000004 + +#define TBR 0xFE002000 +#define RBR 0xFE002000 + +#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020 +#define CR7 0xFE002038 +#define CR8 0xFE002040 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SpiS0 0x02 +#define SPI_SSS 0x01 + +/* CR7 */ +#define CR7_IDX_OR12 0x12 +#define OR12_ADDR32 0x00000001 + +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr)) + +/* M25P80 */ +#define M25_READ 0x03 +#define M25_READ_4BYTE 0x13 + +extern void bss_start(void); + +#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{ + int timeout = 0x00100000; + + /* Make sure the last transaction is finalized */ + spi_write(0x00, CR3); + spi_write(0x02, CR1); + while (!(spi_read(CR4) & SPI_SpiS0)) { + if (timeout-- < 0) + break; + } + spi_write(0x00, CR1); + + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); + + spi_write(0, SPIDMCOR); +} + +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, + unsigned long len) +{ + spi_write(CR7_IDX_OR12, CR7); + if (spi_read(CR8) & OR12_ADDR32) { + /* 4-bytes address mode */ + spi_write(M25_READ_4BYTE, TBR); + spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ + } else { + /* 3-bytes address mode */ + spi_write(M25_READ, TBR); + } + spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ + spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ + spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ + + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); + spi_write((unsigned long)buf, SPIWDMADR); + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); + spi_write(1, SPIDMCOR); + + spi_write(0xff, CR3); + spi_write(spi_read(CR1) | SPI_SSDB, CR1); + spi_write(spi_read(CR1) | SPI_SSA, CR1); + + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) + ; + + /* Nagate SP0-SS0 */ + spi_write(0, CR1); +} + +void __uses_spiboot2 spiboot_main(void) +{ + /* + * This code rounds len up for SPIWDMCNTR. We should set it to 0 in + * lower 5-bits. + */ + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; + volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0; + + spi_reset(); + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len); + + _start(); +} diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds new file mode 100644 index 0000000000..053df642ea --- /dev/null +++ b/board/renesas/sh7753evb/u-boot.lds @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2012 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + KEEP(arch/sh/cpu/sh4/start.o (.text)) + *(.spiboot1.text) + *(.spiboot2.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (__bss_end = .); +} diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9ae88c57a4..1b60b8f672 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -202,12 +202,12 @@ int board_eth_init(bd_t *bis) /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - mac_addr[0] = mac_hi & 0xFF; + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = mac_lo & 0xFF; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 02d107c4b9..b6fdde4d1b 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -20,6 +20,7 @@ SECTIONS .text.0 : { arch/arm/cpu/pxa/start.o (.text*) + arch/arm/lib/built-in.o (.text*) board/vpac270/built-in.o (.text*) drivers/mtd/onenand/built-in.o (.text*) } diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts new file mode 100644 index 0000000000..6da71c116d --- /dev/null +++ b/board/xilinx/dts/zynq-microzed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx MicroZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq MicroZED Board"; + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts new file mode 100644 index 0000000000..667dc28256 --- /dev/null +++ b/board/xilinx/dts/zynq-zc702.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC702 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts new file mode 100644 index 0000000000..526fc8888b --- /dev/null +++ b/board/xilinx/dts/zynq-zc706.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC706 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC706 Board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts new file mode 100644 index 0000000000..8b542a109b --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm010.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM010 Board"; + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts new file mode 100644 index 0000000000..0379a07068 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm012.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM012 Board"; + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts new file mode 100644 index 0000000000..a4f9e05fc0 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm013.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM013 Board"; + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts new file mode 100644 index 0000000000..91a5deba4a --- /dev/null +++ b/board/xilinx/dts/zynq-zed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZED Board"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5119c09037..a5b9bdef46 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -12,6 +12,12 @@ DECLARE_GLOBAL_DATA_PTR; +/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0x0F +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + #ifdef CONFIG_FPGA Xilinx_desc fpga; @@ -59,6 +65,25 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) |
