diff options
Diffstat (limited to 'board')
200 files changed, 2838 insertions, 4334 deletions
diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index 4ba1964f7e..0c92d31f61 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -65,9 +65,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 5aaf6b309d..2bb876d689 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -86,9 +86,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 1327c62a75..4a780c3746 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -139,20 +139,13 @@ static void marvell_serial_setbrg(void) #endif /* CONFIG_MPSC */ -static void marvell_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device marvell_serial_drv = { .name = "marvell_serial", .start = marvell_serial_init, .stop = NULL, .setbrg = marvell_serial_setbrg, .putc = marvell_serial_putc, - .puts = marvell_serial_puts, + .puts = default_serial_puts, .getc = marvell_serial_getc, .tstc = marvell_serial_tstc, }; diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index 99c48f28d4..dc8c4e958f 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index 99c48f28d4..dc8c4e958f 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 4491edd944..b43a1e4281 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 838537375b..748e5113ef 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -71,9 +71,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 63fd356097..c41eed0e6f 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -54,11 +54,11 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } - __u_boot_cmd_end =.; . = ALIGN (4); .rel.dyn : { diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 9885d06b8e..84099840b5 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -54,11 +54,11 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } - __u_boot_cmd_end =.; . = ALIGN (4); .rel.dyn : { diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index 4a1c75aecc..a3bd02b0d2 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -54,11 +54,11 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } - __u_boot_cmd_end =.; . = ALIGN (4); .rel.dyn : { diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index a7627699e7..73e2f3f9cf 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -62,9 +62,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 52c986e8a9..656b2fbf89 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -48,6 +48,10 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } >.sram + . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index 88ced629ec..289386b35c 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -46,13 +46,11 @@ SECTIONS * the initialization code relocates the command table as * well -- admittedly, this is just pure laziness ;-) */ - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } /* INIT DATA sections - "Small" data (see the gcc -G option) * is always gp-relative. Here we make all init data sections diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index ab67de2f76..beba978f83 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -72,10 +72,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 3ad87095a1..2dd00d7f42 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -73,10 +73,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 76f89f188d..8ac5116296 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -73,10 +73,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index ab67de2f76..beba978f83 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -72,10 +72,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index 07ae8b1291..18266efd09 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -73,10 +73,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 423400ac66..6b02784926 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -64,10 +64,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index a1d8e0f6dc..bc40fd649d 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -22,51 +22,18 @@ */ OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + SECTIONS { /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/m68k/cpu/mcf532x/start.o (.text) - arch/m68k/lib/traps.o (.text) - arch/m68k/lib/interrupts.o (.text) - common/dlmalloc.o (.text) - lib/zlib.o (.text) + arch/m68k/cpu/mcf532x/start.o (.text*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text*) - *(.text) -/* *(.fixup)*/ - *(.got1) + *(.text*) } _etext = .; PROVIDE (etext = .); @@ -74,9 +41,6 @@ SECTIONS { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -86,33 +50,30 @@ SECTIONS .reloc : { __got_start = .; - *(.got) + KEEP(*(.got)) __got_end = .; _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; @@ -130,9 +91,8 @@ SECTIONS .bss : { _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.sbss*) + *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; diff --git a/board/bmw/README b/board/bmw/README deleted file mode 100644 index 1fbef79e64..0000000000 --- a/board/bmw/README +++ /dev/null @@ -1,331 +0,0 @@ -Broadcom 95xx BMW CPCI Platform - -Overview -========= -BMW is an MPC8245 system controller featuring: -* 3U CPCI Form Factor -* BCM5703 Gigabit Ethernet -* M48T59Y NVRAM -* 16MB DOC -* DIP Socket for Socketed DOC up to 1GB -* 64MB SDRAM -* LCD Display -* Configurable Jumper options for 66,85, and 100Mhz memory bus - - -BMW System Address Map -====================== -BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual -(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found -onboard the processor module are listed briefly below: - -0x00000000 - 0x40000000 - 64MB SDRAM SIMM - (Unregistered PC-100 SDRAM DIMM Module) - -0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000 - TSOP 16MB (MD2211-D16-V3) - -0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000 - DIP32 (Socketed 16MB - 1GB ) * - NOTE: this is not populated on all systems. - -0x7c000000 - 0x7c000000 - Reset Register - (Write 0 to reset) - -0x7c000001 - 0x7c000001 - System LED - (Clear Bit 7 to turn on, set to shut off) - -0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3 - (Clear bit 7 to reset, set to assert IRQ3) - -0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register - (Clear bit 7 to make R/W, set to make R/O) - -0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character - 5x7 Dot Matrix Alphanumeric Display - (Each byte sets the appropriate character) - -0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC - NVRAM Memory Region - -0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC - Realtime Clock Registers - -0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom - (AMD AM29F040, ST 29W040B) - -0xFFF00100 - System Reset Vector - - -IO/MMU (BAT) Configuration -====================== -The following Block-Address-Translation (BAT) configuration -is recommended to access all I/O devices. - -#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - - -Interrupt Mappings -====================== -BMW uses MPC8245 discrete mode interrupts. With the following -hardwired mappings: - -BCM5701 10/100/1000 Ethernet IRQ1 -CompactPCI Interrupt A IRQ2 -RTC/Watchdog Interrupt IRQ3 -Internal NS16552 UART IRQ4 - - -Jumper Settings -====================== - -BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus. -A jumper (X) is a 0 bit. - -Hence 66= 10110 - 85= 11000 - 100= 10000 - -Jumper Settings for various Speeds -======================= -J1 J2 J3 J4 J5 - X X 66Mhz -======================= -J1 J2 J3 J4 J5 - X X X 85Mhz -======================= -J1 J2 J3 J4 J5 - X X X X 100Mhz -======================= - -Obviously, 100Mhz memory bus is recommended for optimum performance. - - -U-Boot -=============== -Broadcom BMW board is supported under config_BWM option. -Supported features: - -- NVRAM setenv/getenv (used by Linux Kernel for configuration variables) -- BCM570x TFTP file transfer support -- LCD Display Support -- DOC Support - (underway) - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 -=>printenv -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -hostname=switch-2 -bootcmd=tftp 100000 vmlinux.img;bootm -gateway=10.16.64.1 -ethaddr=00:00:10:18:10:10 -nfsroot=172.16.40.111:/boot/root-fs -filesize=5ec8c -netmask=255.255.240.0 -ipaddr=172.16.40.114 -serverip=172.16.40.111 -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -Environment size: 315/8172 bytes -=>boot - - -DevTools -======== -ELDK - DENX Embedded Linux Development Kit - -ROM Emulator - Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time) - Grammar Engine PL32E 32Pin PLCC Emulation cables - Grammar Engine 3VA8CON (3Volt adapter with Short cables) - Grammar Engine FPNET PromICE Ethernet Adapters - -ICE - WRS/EST VisionICE-II (PPC8240) - - -=>reset - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 - -Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000 -BCM570x PCI Memory base address @0x80100000 -eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF -eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010 -eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found -eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON -ARP broadcast 1 -TFTP from server 172.16.40.111; our IP address is 172.16.40.114 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ################################################################# - ####################################T ############################# - ###################### -done -Bytes transferred = 777199 (bdbef hex) - -eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline. -## Booting image at 00100000 ... - Image Name: vmlinux.bin.gz - Created: 2002-08-06 6:30:13 UTC - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 777135 Bytes = 758 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb -Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002 -CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000 -U-Boot Environment: 0xc01b08f0 -IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10> -cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e -NOTICE: mounting root file system via NFS -IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111 -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111 -root_dev_setup:/dev/nfs or 00:ff -time_init: decrementer frequency = 16.501145 MHz -Calibrating delay loop... 175.71 BogoMIPS -Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem) -Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) -Inode cache hash table entries: 4096 (order: 3, 32768 bytes) -Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd -devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au) -devfs: devfs_debug: 0x0 -devfs: boot_options: 0x1 -Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -pty: 256 Unix98 ptys configured -Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -Testing ttyS0 (0xf7f51500, 0xf7f51500)... -Testing ttyS1 (0xfc004600, 0xfc004600)... -ttyS00 at 0xf7f51500 (irq = 24) is a ST16650 -ttyS01 at 0xfc004600 (irq = 25) is a 16550A -Real Time Clock Driver v1.10e -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -loop: loaded (max 8 devices) -TFFS 5.1.1 Flash disk driver for DiskOnChip -Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd. -DOC device(s) found: 1 -fl_init: registered device at major: 100 -fl_geninit: registered device at major: 100 -Partition check: - fla: p1 -partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB -partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB -partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02) -eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010 -eth0: Broadcom BCM5701 Integrated Copper transceiver found -eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON -bond0 registered without MII link monitoring, in bonding mode. -rtc: unable to get misc minor -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP, IGMP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex -IP-Config: Gateway not on directly connected network. -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com> -All bugs added by David S. Miller <davem@redhat.com> -Looking up port of RPC 100003/2 on 172.16.40.111 -Looking up port of RPC 100005/1 on 172.16.40.111 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 100k init -INIT: version 2.78 booting -Mounting local filesystems... -not mounted anything -Setting up symlinks in /dev...done. -Setting up extra devices in /dev...done. -Starting devfsd...Started device management daemon for /dev -INIT: Entering runlevel: 2 -Starting internet superserver: inetd. - - -Welcome to Linux/PPC -MPC8245/BMW - - -switch-2 login: root -Password: -PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Nov 25 11:51:14 1920 on console - - -Welcome to Linux/PPC -MPC8245/BMW - - -login[49]: ROOT LOGIN on `console' - -root@switch-2:~# cat /proc/cpuinfo -cpu : 82xx -revision : 16.20 (pvr 8081 1014) -bogomips : 175.71 -vendor : Broadcom -machine : BMW/MPC8245 -root@switch-2:~# diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c deleted file mode 100644 index 5ba6c09d1c..0000000000 --- a/board/bmw/bmw.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <net.h> -#include <timestamp.h> -#include <dtt.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <linux/mtd/doc2000.h> - -#include "bmw.h" -#include "m48t59y.h" -#include <pci.h> - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n"); - printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - -phys_size_t initdram(int board_type) -{ - return 64*1024*1024; -} - - -void -get_tod(void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get(&year, - &month, - &day, - &hour, - &minute, - &second); - - printf(" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ -#if 0 - m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */ - printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n", - TOD_NVRAM_SIZE); - get_tod(); -#endif - - sys_led_msg("BOOT"); - return 0; -} - - -/* - * Initialize PCI Devices, report devices found. - */ -struct pci_controller hose; - -void pci_init_board (void) -{ - pci_mpc824x_init(&hose); - /* pci_dev_init(0); */ -} - -/* - * Write characters to LCD display. - * Note that the bytes for the first character is the last address. - */ -void -sys_led_msg(char* msg) -{ - LED_REG(0) = msg[3]; - LED_REG(1) = msg[2]; - LED_REG(2) = msg[1]; - LED_REG(3) = msg[0]; -} - -#ifdef CONFIG_CMD_DOC -/* - * Map onboard TSOP-16MB DOC FLASH chip. - */ -void doc_init (void) -{ - doc_probe(DOC_BASE_ADDR); -} -#endif - -#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR) - -/* Read from NVRAM */ -void* -nvram_read(void *dest, const long src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - for( i = 0; i < count;i++) - d[i] = s[i]; - - return dest; -} - -/* Write to NVRAM */ -void -nvram_write(long dest, const void *src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - SYS_TOD_UNPROTECT(); - - for( i = 0; i < count;i++) - d[i] = s[i]; - - SYS_TOD_PROTECT(); -} diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h deleted file mode 100644 index dd97569303..0000000000 --- a/board/bmw/bmw.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BMW/MPC8245 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BMW_H -#define __BMW_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */ -#define EUMBSIZE 0x00100000 /* Size of EUMB region */ - -/* Extended ROM space devices */ -#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */ -#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */ -#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */ -#define PLD_REG_BASE XROM_BASE_ADDR -#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000) -#define TOD_BASE (XROM_BASE_ADDR | 0x4000) -#define LED_REG(x) (*(volatile unsigned char *) \ - (LED_REG_BASE + (x))) -#define XROM_DEV_SIZE 0x00006000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG(off) (*(volatile unsigned char *)\ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f /* Fix me */ -#define PLD_REVID_B2 0x01 /* Fix me */ - -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) -#define RTC(r) (TOD_BASE + r) - -/* Onboard BCM570x device */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - - -#ifndef __ASSEMBLY__ -/* C Function prototypes */ -void sys_led_msg(char* msg); - -#endif /* !__ASSEMBLY__ */ - -#endif /* __BMW_H */ diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S deleted file mode 100644 index 63c29d500f..0000000000 --- a/board/bmw/early_init.S +++ /dev/null @@ -1,1170 +0,0 @@ -#include <ppc_asm.tmpl> -#include <mpc824x.h> -#include <ppc_defs.h> -#include <asm/cache.h> -#include <asm/mmu.h> - -#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */ - - -/* - * Initialize the MMU using BAT entries and hardwired TLB - * This obviates the need for any code in cpu_init_f which - * configures the BAT registers. -*/ -#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */ - .global iommu_setup - /* Initialize IO/MMU mappings via BAT method Ch. 7, - * PPC Programming Reference - */ -iommu_setup: - -/* initialize the BAT registers (SPRs 528 - 543 */ -#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */ -#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */ -#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */ -#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */ -#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */ -#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */ -#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */ -#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */ -#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */ -#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */ -#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */ -#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */ -#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */ -#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */ -#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */ -#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */ - - -/* PowerPC processors do not necessarily initialize the BAT - registers on power-up or reset. So they are in an unknown - state. Before programming the BATs for the first time, all - BAT registers MUST have their Vs and Vp bits cleared in the - upper BAT half in order to avoid possibly having 2 BATs - valid and mapping the same memory region. - - The reason for this is that, even with address translation - disabled, multiple BAT hits for an address are treated as - programming errors and can cause unpredictable results. - - It is up to the software to make sure it never has 2 IBAT - mappings or 2 DBAT mappings that are valid for the same - addresses. It is not necessary to perform this code - sequence every time the BATs are programmed, only when - there is a possibility that there may be overlapping BAT - entries. - - When programming the BATs in non-reset scenarios, even if - you are sure that your new mapping will not temporarily - create overlapping regions, it is still a wise idea to - invalidate a BAT entry by setting its upper BAT register to - all 0's before programming it. This will avoid having a - BAT marked valid that is in an unknown or transient state -*/ - - addis r5,0,0x0000 - mtibat0u(r5) - mtibat0l(r5) - mtibat1u(r5) - mtibat1l(r5) - mtibat2u(r5) - mtibat2l(r5) - mtibat3u(r5) - mtibat3l(r5) - mtdbat0u(r5) - mtdbat0l(r5) - mtdbat1u(r5) - mtdbat1l(r5) - mtdbat2u(r5) - mtdbat2l(r5) - mtdbat3u(r5) - mtdbat3l(r5) - isync - -/* - * Set up I/D BAT0 - */ - lis r4, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - lis r3, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - - mtdbat0l(r4) - isync - mtdbat0u(r3) - isync - sync - - lis r4, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - lis r3, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - - isync - mtibat0l(r4) - isync - mtibat0u(r3) - isync - -/* - * Set up I/D BAT1 - */ - lis r4, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - lis r3, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - - isync - mtibat1l(r4) - isync - mtibat1u(r3) - isync - mtdbat1l(r4) - isync - mtdbat1u(r3) - isync - sync - -/* - * Set up I/D BAT2 - */ - lis r4, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - lis r3, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - - isync - mtibat2l(r4) - isync - mtibat2u(r3) - isync - mtdbat2l(r4) - isync - mtdbat2u(r3) - isync - sync - -/* - * Setup I/D BAT3 - */ - lis r4, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - lis r3, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - - isync - mtibat3l(r4) - isync - mtibat3u(r3) - isync - mtdbat3l(r4) - isync - mtdbat3u(r3) - isync - sync - - -/* - * Invalidate all 64 TLB's - */ - lis r3, 0 - mtctr r3 - lis r5, 4 - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmplw r3, r5 - blt tlblp - - sync - -/* - * Enable Data Translation - */ - lis r4, MEMORY_MGMT_MSR_BITS@h - ori r4, r4, MEMORY_MGMT_MSR_BITS@l - mfmsr r3 - or r3, r4, r3 - mtmsr r3 - isync - sync - - blr - - -#ifdef USE_V2_INIT -/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */ -/* Macro for hiadjust and lo */ -#define HIADJ(arg) arg@ha -#define HI(arg) arg@h -#define LO(arg) arg@l - -#undef LOADPTR -#define LOADPTR(reg,const32) \ - addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32) - -.globl early_init_f - -early_init_f: -/* MPC8245/BMW CPCI System Init - * Jimmy Blair, Broadcom Corp, 2002. - */ - mflr r11 - /* Zero-out registers */ - - addis r0,r0,0 - mtspr SPRG0,r0 - mtspr SPRG1,r0 - mtspr SPRG2,r0 - mtspr SPRG3,r0 - - /* Set MPU/MSR to a known state. Turn on FP */ - - LOADPTR (r3, MSR_FP) - sync - mtmsr r3 - isync - - /* Init the floating point control/status register */ - - mtfsfi 7,0x0 - mtfsfi 6,0x0 - mtfsfi 5,0x0 - mtfsfi 4,0x0 - mtfsfi 3,0x0 - mtfsfi 2,0x0 - mtfsfi 1,0x0 - mtfsfi 0,0x0 - isync - - /* Set MPU/MSR to a known state. Turn off FP */ - -#if 1 /* Turn off floating point (remove to keep FP on) */ - andi. r3, r3, 0 - sync - mtmsr r3 - isync -#endif - - /* Init the Segment registers */ - - andi. r3, r3, 0 - isync - mtsr 0,r3 - isync - mtsr 1,r3 - isync - mtsr 2,r3 - isync - mtsr 3,r3 - isync - mtsr 4,r3 - isync - mtsr 5,r3 - isync - mtsr 6,r3 - isync - mtsr 7,r3 - isync - mtsr 8,r3 - isync - mtsr 9,r3 - isync - mtsr 10,r3 - isync - mtsr 11,r3 - isync - mtsr 12,r3 - isync - mtsr 13,r3 - isync - mtsr 14,r3 - isync - mtsr 15,r3 - isync - - /* Turn off data and instruction cache control bits */ - - mfspr r3, HID0 - isync - rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - isync - - /* Get cpu type */ - - mfspr r28, PVR - rlwinm r28, r28, 16, 16, 31 - - /* invalidate the MPU's data/instruction caches */ - - lis r3, 0x0 - cmpli 0, 0, r28, CPU_TYPE_603 - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603E - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603P - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_604R - bne cpuNot604R - -cpuIs604R: - lis r3, 0x0 - mtspr HID0, r3 /* disable the caches */ - isync - ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */ - -cpuNot604R: - ori r3, r3, (HID0_ICFI |HID0_DCI) - -cpuIs603: - ori r3, r3, (HID0_ICE | HID0_DCE) - or r4, r4, r3 /* set bits */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - andc r4, r4, r3 /* clear bits */ - isync - cmpli 0, 0, r28, CPU_TYPE_604 - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604E - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604R - beq cpuIs604 - mtspr HID0, r4 - isync - -#ifdef USER_I_CACHE_ENABLE - b instCacheOn603 -#else - b cacheEnableDone -#endif - -cpuIs604: - LOADPTR (r5, 0x1000) /* loop count, 0x1000 */ - mtspr CTR, r5 -loopDelay: - nop - bdnz loopDelay - isync - mtspr HID0, r4 - isync - - /* turn the Instruction cache ON for faster FLASH ROM boots */ - -#ifdef USER_I_CACHE_ENABLE - - ori r4, r4, (HID0_ICE | HID0_ICFI) - isync /* Synchronize for ICE enable */ - b writeReg4 -instCacheOn603: - ori r4, r4, (HID0_ICE | HID0_ICFI) - rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ - - /* - * The setting of the instruction cache enable (ICE) bit must be - * preceded by an isync instruction to prevent the cache from being - * enabled or disabled while an instruction access is in progress. - */ - isync -writeReg4: - mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ - cmpli 0, 0, r28, CPU_TYPE_604 - beq cacheEnableDone - cmpli 0, 0, r28, CPU_TYPE_604E - beq cacheEnableDone - - mtspr HID0, r3 /* using 2 consec instructions */ - /* PPC603 recommendation */ -#endif -cacheEnableDone: - - /* Detect map A or B */ - - addis r5,r0, HI(CHRP_REG_ADDR) - addis r6,r0, HI(CHRP_REG_DATA) - LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */ - LOADPTR (r8, BMC_BASE) - - stwbrx r8,0,(r5) - lwbrx r3,0,(r6) /* Store read value to r3 */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* It's not an 8240, is it an 8245? */ - - LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* Save the PCI controller type in r7 */ - mr r7, r3 - - LOADPTR (r5, PREP_REG_ADDR) - LOADPTR (r6, PREP_REG_DATA) - -X4_KAHLUA_START: - /* MPC8245 changes begin here */ - LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */ - stwbrx r3,0,r5 - li r4, 6 /* Command register value */ - sthbrx r4, 0, r6 - - LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */ - stwbrx r3,0,r5 - li r4, -1 /* Write-to-clear all bits */ - li r3, 2 /* PCI_STATUS is at +2 offset */ - sthbrx r4, r3, r6 - - /*-------PROC_INT1_ADR */ - - LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xff141b98) - stwbrx r4,0,r6 - - /*-------PROC_INT2_ADR */ - - LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */ - stwbrx r3,0,r5 - lis r4, 0x2000 /* Flush PCI config writes */ - stwbrx r4,0,r6 - - LOADPTR (r9, KAHLUA2_ID) - cmpl 0, 0, r7, r9 - bne L1not8245 - - /* MIOCR1 -- turn on bit for DLL delay */ - - LOADPTR (r3, MIOCR1_ADR_X) - stwbrx r3,0,r5 - li r4, 0x04 - stb r4, MIOCR1_SHIFT(r6) - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - - LOADPTR (r3, MIOCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x10 - stb r4, MIOCR2_SHIFT(r6) - - /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */ - - LOADPTR (r3, PMCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x20 - stb r4, PMCR2_SHIFT(r6) - - /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */ - - LOADPTR (r3, EUMBBAR) - stwbrx r3,0,r5 - LOADPTR (r4, CONFIG_SYS_EUMB_ADDR) - stwbrx r4,0,r6 - -L1not8245: - - /* Toggle the DLL reset bit in AMBOR */ - - LOADPTR (r3, AMBOR) - stwbrx r3,0,r5 - lbz r4, 0(r6) - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - sync - - ori r4, r4, 0x20 /* Set DLL_RESET */ - stb r4, 0(r6) - sync - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - - - /* Enable RCS2, use supplied timings */ - LOADPTR (r3, ERCR1) - stwbrx r3,0,r5 - LOADPTR (r4, 0x80408000) - stwbrx r4,0,r6 - - /* Disable RCS3 parameters */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - /* RCS3 at 0x70000000, 64KBytes */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000004) - stwbrx r4,0,r6 - - /*-------MCCR1 */ - -#ifdef INCLUDE_ECC -#define MC_ECC 1 -#else /* INCLUDE_ECC */ -#define MC_ECC 0 -#endif /* INCLUDE_ECC */ - -#define MC1_ROMNAL 8 /* 0-15 */ -#define MC1_ROMFAL 11 /* 0-31 */ -#define MC1_DBUS_SIZE 0 /* 0-3, read only */ -#define MC1_BURST 0 /* 0-1 */ -#define MC1_MEMGO 0 /* 0-1 */ -#define MC1_SREN 1 /* 0-1 */ -#define MC1_RAM_TYPE 0 /* 0-1 */ -#define MC1_PCKEN MC_ECC /* 0-1 */ -#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */ - - LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \ - MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \ - MC1_MEMGO << 19 | MC1_SREN << 18 | \ - MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 ) - li r3, MC1_BANKBITS - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne BankBitsAdd - cmpli 0, 0, r3, 0x5555 - beq K2BankBitsHack /* On 8245, 5555 ==> 0 */ -BankBitsAdd: - ori r4, r3, 0 -K2BankBitsHack: - stwbrx r4, 0, r6 - - /*------- MCCR2 */ - -#define MC2_TS_WAIT_TIMER 0 /* 0-7 */ -#define MC2_ASRISE 8 /* 0-15 */ -#define MC2_ASFALL 4 /* 0-15 */ -#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */ -#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */ -#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */ -#define MC2_ECC_EN 0 /* 0-1 */ -#define MC2_EDO 0 /* 0-1 */ -/* -* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM. -* May need to be decreased for 100 MHz -*/ -#define MC2_REFINT 0x3a5 /* 0-0x3fff */ -#define MC2_RSV_PG 0 /* 0-1 */ -#define MC2_RMW_PAR MC_ECC /* 0-1 */ - - LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \ - MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \ - MC2_WRITE_PARITY_CHK_EN << 19 | \ - MC2_INLRD_PARECC_CHK_EN << 18 | \ - MC2_ECC_EN << 17 | MC2_EDO << 16 | \ - MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2 - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xfffcffff) - and r4, r4, r3 -notK2: - stwbrx r4,0,r6 - - /*------- MCCR3 */ - -#define MC_BSTOPRE 0x079 /* 0-0x7ff */ - -#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf) -#define MC3_REFREC 8 /* 0-15 */ -#define MC3_RDLAT (4+MC_ECC) /* 0-15 */ -#define MC3_CPX 0 /* 0-1 */ -#define MC3_RAS6P 0 /* 0-15 */ -#define MC3_CAS5 0 /* 0-7 */ -#define MC3_CP4 0 /* 0-7 */ -#define MC3_CAS3 0 /* 0-7 */ -#define MC3_RCD2 0 /* 0-7 */ -#define MC3_RP1 0 /* 0-7 */ - - LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \ - MC3_RDLAT << 20 | MC3_CPX << 19 | \ - MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \ - MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2b - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xff000000) - and r4, r4, r3 -notK2b: - stwbrx r4,0,r6 - - /*------- MCCR4 */ - -#define MC4_PRETOACT 3 /* 0-15 */ -#define MC4_ACTOPRE 5 /* 0-15 */ -#define MC4_WMODE 0 /* 0-1 */ -#define MC4_INLINE MC_ECC /* 0-1 */ -#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */ -#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3) -#define MC4_REGDIMM 0 /* 0-1 */ -#define MC4_SDMODE_CAS 2 /* 0-7 */ -#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */ -#define MC4_SDMODE_WRAP 0 /* 0-1 */ -#define MC4_SDMODE_BURST 2 /* 0-7 */ -#define MC4_ACTORW 3 /* 0-15 */ -#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf) - - LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \ - MC4_WMODE << 23 | MC4_INLINE << 22 | \ - MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \ - MC4_DBUS_RCS1 << 17 | \ - MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \ - MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \ - MC4_ACTORW << 4 | MC4_BSTOPRE_L) - cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */ - bne notK2c - /* Turn on Kahlua2 extended ROM space */ - LOADPTR (r3, 0x00200000) - or r4, r4, r3 -notK2c: - stwbrx r4,0,r6 - -#ifdef INCLUDE_ECC - /*------- MEM_ERREN1 */ - - LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 - ori r4,r4,4 /* Set MEM_PERR_EN */ - stwbrx r4,0,r6 -#endif /* INCLUDE_ECC */ - - /*------- MSAR/MEAR */ - - LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - /*-------ODCR */ - - LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */ - stwbrx r3,0,r5 - - li r4, 0x7f - stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */ - - /*-------MBEN */ - - LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */ - stwbrx r3,0,r5 - li r4, 0x01 /* Enable bank 0 */ - stb r4, 0(r6) /* MBEN is at +0 offset */ - -#if 0 /* Jimmy: I think page made is broken */ - /*-------PGMAX */ - - LOADPTR (r3, MPM_ADR_X) - stwbrx r3,0,r5 - li r4, 0x32 - stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */ -#endif - - /* Wait before initializing other registers */ - - lis r4,0x0001 - mtctr r4 - -KahluaX4wait200us: - bdnz KahluaX4wait200us - - /* Set MEMGO bit */ - - LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 /* old MCCR1 */ - oris r4,r4,0x0008 /* MEMGO=1 */ - stwbrx r4, 0, r6 - - /* Wait again */ - - addis r4,r0,0x0002 - ori r4,r4,0xffff - - mtctr r4 - -KahluaX4wait8ref: - bdnz KahluaX4wait8ref - - sync - eieio - mtlr r11 - blr - -#else /* USE_V2_INIT */ - - -/* U-Boot works, but memory will not run reliably for all address ranges. - * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not - * initialized correctly. Could work if debugged. - */ -/* PCI Support routines */ - - .globl __pci_config_read_32 -__pci_config_read_32: - lis r4, 0xfec0 - stwbrx r3, r0, r4 - sync - lis r4, 0xfee0 - lwbrx r3, 0, r4 - blr - .globl __pci_config_read_16 -__pci_config_read_16: - lis r4, 0xfec0 - andi. r5, r3, 2 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lhbrx r3, r0, r4 - blr - .globl __pci_config_read_8 -__pci_config_read_8: - lis r4, 0xfec0 - andi. r5, r3, 3 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lbz r3, 0(4) - blr - .globl __pci_config_write_32 -__pci_config_write_32: - lis r5, 0xfec0 - stwbrx r3, r0, r5 - sync - lis r5, 0xfee0 - stwbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_16 -__pci_config_write_16: - lis r5, 0xfec0 - andi. r6, r3, 2 - stwbrx r3, r0, 5 - sync - oris r5, r6, 0xfee0 - sthbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_8 -__pci_config_write_8: - lis r5, 0xfec0 - andi. r6, r3, 3 - stwbrx r3, r0, r5 - sync - oris r5, r6, 0xfee0 - stb r4, 0(r5) - sync - blr - .globl in_8 -in_8: - oris r3, r3, 0xfe00 - lbz r3,0(r3) - blr - .globl in_16 -in_16: - oris r3, r3, 0xfe00 - lhbrx r3, 0, r3 - blr - .globl in_16_ne -in_16_ne: - oris r3, r3, 0xfe00 - lhzx r3, 0, r3 - blr - .globl in_32 -in_32: - oris r3, r3, 0xfe00 - lwbrx r3, 0, r3 - blr - .globl out_8 -out_8: - oris r3, r3, 0xfe00 - stb r4, 0(r3) - eieio - blr - .globl out_16 -out_16: - oris r3, r3, 0xfe00 - sthbrx r4, 0, r3 - eieio - blr - .globl out_16_ne -out_16_ne: - oris r3, r3, 0xfe00 - sth r4, 0(r3) - eieio - blr - .globl out_32 -out_32: - oris r3, r3, 0xfe00 - stwbrx r4, 0, r3 - eieio - blr - .globl read_8 -read_8: - lbz r3,0(r3) - blr - .globl read_16 -read_16: - lhbrx r3, 0, r3 - blr - .globl read_32 -read_32: - lwbrx r3, 0, r3 - blr - .globl read_32_ne -read_32_ne: - lwz r3, 0(r3) - blr - .globl write_8 -write_8: - stb r4, 0(r3) - eieio - blr - .globl write_16 -write_16: - sthbrx r4, 0, r3 - eieio - blr - .globl write_32 -write_32: - stwbrx r4, 0, r3 - eieio - blr - .globl write_32_ne -write_32_ne: - stw r4, 0(r3) - eieio - blr - - -.globl early_init_f - -early_init_f: - mflr r11 - lis r10, 0x8000 - - /* PCI Latency Timer */ - li r4, 0x0d - ori r3, r10, PLTR@l - bl __pci_config_write_8 - - /* Cache Line Size */ - li r4, 0x08 - ori r3, r10, PCLSR@l - bl __pci_config_write_8 - - /* PCI Cmd */ - li r4, 6 - ori r3, r10, PCICR@l - bl __pci_config_write_16 - -#if 1 - /* PCI Stat */ - ori r3, r10, PCISR@l - bl __pci_config_read_16 - ori r4, r4, 0xffff - ori r3, r10, PCISR@l - bl __pci_config_write_16 -#endif - - /* PICR1 */ - lis r4, 0xff14 - ori r4, r4, 0x1b98 - ori r3, r10, PICR1@l - bl __pci_config_write_32 - - - /* PICR2 */ - lis r4, 0x0404 - ori r4, r4, 0x0004 - ori r3, r10, PICR2@l - bl __pci_config_write_32 - - /* MIOCR1 */ - li r4, 0x04 - ori r3, r10, MIOCR1@l - bl __pci_config_write_8 - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - li r4, 0x10 - ori r3, r10, MIOCR2@l - bl __pci_config_write_8 - - /* EUMBBAR */ - lis r4, 0xfc00 - ori r3, r10, EUMBBAR@l - bl __pci_config_write_32 - - /* AMBOR */ - - /* Even if Address Map B is not being used (though it should), - * the memory DLL needs to be cleared/set/cleared before using memory. - */ - - ori r3, r10, AMBOR@l - bl __pci_config_read_8 /* get Current bits */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - ori r4, r4, 0x0020 - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Set DLL_RESET */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - /* ERCR1 */ - lis r4, 0x8040 /* Enable RCS2, use supplied timings */ - ori r4, r4, 0x8000 - ori r3, r10, ERCR1@l - bl __pci_config_write_32 - - /* ERCR2 */ - lis r4, 0x0000 /* Disable RCS3 parms */ - ori r4, r4, 0x0000 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* ERCR3 */ - lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */ - ori r4, r4, 0x0004 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* Preserve memgo bit */ - /* MCCR1 */ - -/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */ - lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */ -/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */ -/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */ -/* oris r4, r4, 0x0004 / Self-refresh enable */ - -/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */ -/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */ -/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */ - ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */ - - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* MCCR2 */ - - lis r4,0x0000 -/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */ - oris r4,r4,0x1000 /* ASRISE = 8 clocks */ - oris r4,r4,0x0080 /* ASFALL = 8 clocks */ -/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */ -/* oris r4,r4,0x0008 / Write parity check */ -/* oris r4,r4,0x0004 / SDRAM inline reads */ - - -/* Select a refresh rate; it needs to match the bus speed; if too */ -/* slow, data may be lost; if too fast, performance is lost. We */ -/* use the fastest value so we run at all speeds. */ -/* Refresh = (15600ns/busclk) - (213 (see UM)). */ - -/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */ -/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */ -/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */ -/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */ - ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */ -/* ori r4,r4,0x0002 / Reserve a page */ -/* ori r4,r4,0x0001 / RWM parity */ - - ori r3, r10, MCCR2@l - bl __pci_config_write_32 - - - /* MCCR3 */ - lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */ - oris r4,r4,0x0500 /* REFREC = 8 clocks */ - ori r3, r10, MCCR3@l - bl __pci_config_write_32 - - /* MCCR4 */ /* Turn on registered buffer mode */ - lis r4, 0x2000 /* PRETOACT = 3 clocks */ - oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */ -/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */ -/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */ - oris r4,r4,0x0020 /* EXTROM enabled */ - oris r4,r4,0x0010 /* Registered buffers */ -/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */ - oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */ - -/* ori r4,r4,0x8000 / Registered DIMMs */ - ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */ -/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */ -/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */ - ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */ - ori r4,r4,0x0030 /* ACTORW = 3 clocks */ - ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */ - - ori r3, r10, MCCR4@l - bl __pci_config_write_32 - - /* MSAR1 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR1@l - bl __pci_config_write_32 - - /* MSAR2 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR2@l - bl __pci_config_write_32 - - /* MESAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMSAR1@l - bl __pci_config_write_32 - - /* MESAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMSAR2@l - bl __pci_config_write_32 - - /* MEAR1 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR1@l - bl __pci_config_write_32 - - /* MEAR2 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR2@l - bl __pci_config_write_32 - - /* MEEAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMEAR1@l - bl __pci_config_write_32 - - /* MEEAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMEAR2@l - bl __pci_config_write_32 - - /* ODCR */ - li r4, 0x7f - ori r3, r10, ODCR@l - bl __pci_config_write_8 - - /* MBER */ - li r4, 0x01 - ori r3, r10, MBER@l - bl __pci_config_write_8 - - /* Page CTR aka PGMAX */ - li r4, 0x32 - ori r3, r10, 0x70 - bl __pci_config_write_8 - -#if 0 - /* CLK Drive */ - ori r4, r10, 0xfc01 /* Top bit will be ignored */ - ori r3, r10, 0x74 - bl __pci_config_write_16 -#endif - - /* delay */ - lis r7, 1 - mtctr r7 -label1: bdnz label1 - - /* Set memgo bit */ - /* MCCR1 */ - ori r3, r10, MCCR1@l - bl __pci_config_read_32 - lis r7, 0x0008 - or r4, r3, r7 - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* delay again */ - lis r7, 1 - mtctr r7 -label2: bdnz label2 -#if 0 -/* DEBUG: Infinite loop, write then read */ -loop: - lis r7, 0xffff - mtctr r7 - li r3, 0x5004 - lis r4, 0xa0a0 - ori r4, r4, 0x5050 - bl write_32_ne - li r3, 0x5004 - bl read_32_ne - bdnz loop -#endif - mtlr r11 - blr -#endif diff --git a/board/bmw/flash.c b/board/bmw/flash.c deleted file mode 100644 index 57ffe0890f..0000000000 --- a/board/bmw/flash.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/pci_io.h> - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t * info, ulong dest, ulong data); - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd (unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int byte_parity_odd (unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE *addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__ ("sync"); - -#if 0 - pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE - *) (pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - printf ("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio (); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf ("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id, - info->sector_count, info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start - [sect] - - - info-> - start - [0]) << - sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c deleted file mode 100644 index 4e83b9076e..0000000000 --- a/board/bmw/m48t59y.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include <common.h> -#include <rtc.h> -#include "bmw.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -int -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c deleted file mode 100644 index be455bbefe..0000000000 --- a/board/bmw/ns16550.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/powerpc/boot/ns16550.c) - * modified to use CONFIG_SYS_ISA_MEM and new defines - */ - -#include <config.h> -#include "ns16550.h" - -typedef struct NS16550 *NS16550_t; - -const NS16550_t COM_PORTS[] = - { (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500), -(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) }; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -unsigned char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h deleted file mode 100644 index 2087a4aabd..0000000000 --- a/board/bmw/ns16550.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/powerpc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CONFIG_SYS_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * further modified to support the 8245 duart - * modifications (c) Paul Jimenez, Musenki, Inc. 2001. - */ - - -struct NS16550 { - unsigned char rbrthrdlb; /* 0 */ - unsigned char ierdmb; /* 1 */ - unsigned char iirfcrafr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ - unsigned char reserved[2]; /* 8 & 9 */ - unsigned char dsr; /* 10 */ - unsigned char dcr; /* 11 */ -}; - - -#define rbr rbrthrdlb -#define thr rbrthrdlb -#define dll rbrthrdlb -#define ier ierdmb -#define dlm ierdmb -#define iir iirfcrafr -#define fcr iirfcrafr -#define afr iirfcrafr - -#define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*receiver soft reset */ -#define FCR_TXSR 0x04 /*transmitter soft reset */ -#define FCR_DMS 0x08 /* DMA Mode Select */ - -#define MCR_RTS 0x02 /* Readyu to Send */ -#define MCR_LOOP 0x10 /* Local loopback mode enable */ -/* #define MCR_DTR 0x01 noton 8245 duart */ -/* #define MCR_DMA_EN 0x04 noton 8245 duart */ -/* #define MCR_TX_DFR 0x08 noton 8245 duart */ - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc (volatile struct NS16550 *com_port); -int NS16550_tstc (volatile struct NS16550 *com_port); -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/bmw/serial.c b/board/bmw/serial.c deleted file mode 100644 index 08f449c864..0000000000 --- a/board/bmw/serial.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <serial.h> -#include <linux/compiler.h> - -#include "ns16550.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_CONS_INDEX == 1 -static struct NS16550 *console = - (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); -#elif CONFIG_CONS_INDEX == 2 -static struct NS16550 *console = - (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); -#else -#error no valid console defined -#endif - -extern ulong get_bus_freq (ulong); - -static int bmw_serial_init(void) -{ - int clock_divisor = gd->bus_clk / 16 / gd->baudrate; - - NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); - - return (0); -} - -static void bmw_serial_putc(const char c) -{ - if (c == '\n') { - serial_putc ('\r'); - } - NS16550_putc (console, c); -} - -static void bmw_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - - -static int bmw_serial_getc(void) -{ - return NS16550_getc (console); -} - -static int bmw_serial_tstc(void) -{ - return NS16550_tstc (console); -} - -static void bmw_serial_setbrg(void) -{ - int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; - - NS16550_reinit (console, clock_divisor); -} - -static struct serial_device bmw_serial_drv = { - .name = "bmw_serial", - .start = bmw_serial_init, - .stop = NULL, - .setbrg = bmw_serial_setbrg, - .putc = bmw_serial_putc, - .puts = bmw_serial_puts, - .getc = bmw_serial_getc, - .tstc = bmw_serial_tstc, -}; - -void bmw_serial_initialize(void) -{ - serial_register(&bmw_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &bmw_serial_drv; -} diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index b9b8e3c727..b854c180c4 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -74,9 +74,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index c7711028ad..92796e6744 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index c4039edf43..d054f20bce 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/cogent/serial.c b/board/cogent/serial.c index cd4a976f89..20631d162d 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -68,12 +68,6 @@ static void cogent_serial_putc(const char c) cma_mb_reg_write (&mbsp->ser_thr, c); } -static void cogent_serial_puts(const char *s) -{ - while (*s != '\0') - serial_putc (*s++); -} - static int cogent_serial_getc(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; @@ -96,7 +90,7 @@ static struct serial_device cogent_serial_drv = { .stop = NULL, .setbrg = cogent_serial_setbrg, .putc = cogent_serial_putc, - .puts = cogent_serial_puts, + .puts = default_serial_puts, .getc = cogent_serial_getc, .tstc = cogent_serial_tstc, }; diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 2393d8d8af..2a6027f814 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -70,9 +70,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index 99c48f28d4..dc8c4e958f 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile index 5c6b78f704..ac1d17440f 100644 --- a/board/cpc45/Makefile +++ b/board/cpc45/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o plx9030.o pd67290.o +COBJS = $(BOARD).o flash.o plx9030.o pd67290.o ide.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c index 1178822db3..22008066e6 100644 --- a/board/cpc45/cpc45.c +++ b/board/cpc45/cpc45.c @@ -260,21 +260,6 @@ int pcmcia_init(void) #endif -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - u_char val; - /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ - val = readb(BCSR_BASE + 0x04); - if (status) { /* led on */ - val |= B_CTRL_LED0; - } else { - val &= ~B_CTRL_LED0; - } - writeb(val, BCSR_BASE + 0x04); -} -# endif - int board_eth_init(bd_t *bis) { return pci_eth_init(bis); diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c new file mode 100644 index 0000000000..03be59f974 --- /dev/null +++ b/board/cpc45/ide.c @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2000-2011 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <ata.h> +#include <asm/io.h> + +#define EIEIO __asm__ volatile ("eieio") +#define SYNC __asm__ volatile ("sync") + +void ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + uchar i; + volatile uchar *pbuf_even = + (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + volatile uchar *pbuf_odd = + (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + ushort *dbuf = (ushort *) sect_buf; + + while (words--) { + for (i = 0; i < 2; i++) { + *(((uchar *) (dbuf)) + 1) = *pbuf_even; + *(uchar *) dbuf = *pbuf_odd; + dbuf += 1; + } + } +} + +void ide_input_data(int dev, ulong *sect_buf, int words) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (words--) { + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + } +} + +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (shorts--) { + EIEIO; + *dbuf++ = *pbuf_even; + EIEIO; + *dbuf++ = *pbuf_odd; + } +} + +void ide_output_data(int dev, const ulong *sect_buf, int words) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (words--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +} + +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (shorts--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +} + +void ide_led(uchar led, uchar status) +{ + u_char val; + /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ + val = readb(BCSR_BASE + 0x04); + if (status) /* led on */ + val |= B_CTRL_LED0; + else + val &= ~B_CTRL_LED0; + + writeb(val, BCSR_BASE + 0x04); +} + diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index fcf8ebbf8e..d7a2e56008 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 3b10114354..8a306d6076 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -74,9 +74,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 6f6e065a9f..c5fd93c0f7 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -47,6 +47,12 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } >.sram + . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index b3a41afc42..86dc172ee2 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -58,6 +58,11 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } + + . = ALIGN(4); __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 4a59cea80f..8a871cff49 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -54,10 +54,9 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } uboot_end_data = .; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 01ec39008d..1bd1700aa2 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -54,11 +54,11 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } - __u_boot_cmd_end =.; . = ALIGN (4); .rel.dyn : { diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index fd4e8a50d5..c8d38942c9 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index c7711028ad..92796e6744 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index fb06648663..22626d392a 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -67,9 +67,11 @@ SECTIONS . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 332b35a57d..1dcc22a191 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -62,9 +62,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index aa001df0b8..4ef10e7d72 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -30,7 +30,6 @@ #include <ide.h> #include <pci.h> -extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; int cpci_hd_type; int ata_device(int dev) diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index 25f8950e9a..160e0e0ae0 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -75,21 +75,13 @@ static void cpci750_serial_setbrg(void) galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } - -static void cpci750_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device cpci750_serial_drv = { .name = "cpci750_serial", .start = cpci750_serial_init, .stop = NULL, .setbrg = cpci750_serial_setbrg, .putc = cpci750_serial_putc, - .puts = cpci750_serial_puts, + .puts = default_serial_puts, .getc = cpci750_serial_getc, .tstc = cpci750_serial_tstc, }; diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index b15948d34c..7eca18390b 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -73,9 +73,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index 71f0fd2c3e..ca7df4592e 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -102,10 +102,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index f697ccd515..0d6a0f3a3b 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -65,9 +65,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 163b83d819..69f15000db 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index 8465937d10..56c3470bde 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 9fd429864a..b9ca1d760c 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -139,20 +139,13 @@ static void evb64260_serial_setbrg(void) #endif /* CONFIG_MPSC */ -static void evb64260_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device evb64260_serial_drv = { .name = "evb64260_serial", .start = evb64260_serial_init, .stop = NULL, .setbrg = evb64260_serial_setbrg, .putc = evb64260_serial_putc, - .puts = evb64260_serial_puts, + .puts = default_serial_puts, .getc = evb64260_serial_getc, .tstc = evb64260_serial_tstc, }; diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 2d031efc4e..eac9c070e3 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -70,9 +70,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 9ea0674b88..6022dbce72 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index fd4e8a50d5..c8d38942c9 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index c7711028ad..92796e6744 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 54cb098a91..36f7c4f30f 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 6cd7e5108a..c92902a92e 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -32,22 +32,22 @@ void qixis_write(unsigned int reg, u8 value) void qixis_reset(void) { - QIXIS_WRITE(rst_ctl, 0x83); + QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } void qixis_bank_reset(void) { - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } -/* Set the boot bank to the power-on default bank0 */ +/* Set the boot bank to the power-on default bank */ void clear_altbank(void) { u8 reg; reg = QIXIS_READ(brdcfg[0]); - reg = reg & ~QIXIS_LBMAP_MASK; + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK; QIXIS_WRITE(brdcfg[0], reg); } @@ -85,11 +85,11 @@ static void qixis_dump_regs(void) printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); printf("present = %02x\n", QIXIS_READ(present)); + printf("present2 = %02x\n", QIXIS_READ(present2)); printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); - printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); } #endif @@ -115,7 +115,8 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (i = 0; i < ARRAY_SIZE(period); i++) { if (strcmp(argv[2], period[i]) == 0) { /* disable watchdog */ - QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(rcfg_ctl, + rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); QIXIS_WRITE(watch, ((i<<2) - 1)); QIXIS_WRITE(rcfg_ctl, rcfg); return 0; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 7a0268a02c..b98b180655 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -26,7 +26,7 @@ struct qixis { u8 stat_sys; u8 stat_alrm; u8 present; - u8 ctl_sys2; + u8 present2; /* Presence Status Register 2,0x0c */ u8 rcw_ctl; u8 ctl_led; u8 i2cblk; @@ -86,12 +86,6 @@ struct qixis { u8 res15[16]; }; -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 7 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_ALTBANK 0x04 - u8 qixis_read(unsigned int reg); void qixis_write(unsigned int reg, u8 value); diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c new file mode 100644 index 0000000000..786856597f --- /dev/null +++ b/board/freescale/common/vsc3316_3308.c @@ -0,0 +1,184 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "vsc3316_3308.h" + +#define REVISION_ID_REG 0x7E +#define INTERFACE_MODE_REG 0x79 +#define CURRENT_PAGE_REGISTER 0x7F +#define CONNECTION_CONFIG_PAGE 0x00 +#define INPUT_STATE_REG 0x13 +#define GLOBAL_INPUT_ISE1 0x51 +#define GLOBAL_INPUT_ISE2 0x52 +#define GLOBAL_INPUT_LOS 0x55 +#define GLOBAL_CORE_CNTRL 0x5D +#define OUTPUT_MODE_PAGE 0x23 +#define CORE_CONTROL_PAGE 0x25 +#define CORE_CONFIG_REG 0x75 + +int vsc_if_enable(unsigned int vsc_addr) +{ + u8 data; + + debug("VSC:Configuring VSC at I2C address 0x%2x" + " for 2-wire interface\n", vsc_addr); + + /* enable 2-wire Serial InterFace (I2C) */ + data = 0x02; + return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); +} + +int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3316 at I2C address 0x%2x" + " for Tx\n", vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Configuring the required input of the switch */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 0x80); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} + +int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3308 at I2C address 0x%x" + " for Tx\n", vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /*Configure Global Input ISE and gain */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12); + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning ON the required input of the switch */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 0); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} + +void vsc_wp_config(unsigned int vsc_addr) +{ + debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr); + + /* For new crosspoint configuration to occur, WP bit of + * CORE_CONFIG_REG should be set 1 and then reset to 0 */ + i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); + i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); +} diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h new file mode 100644 index 0000000000..effd66dce4 --- /dev/null +++ b/board/freescale/common/vsc3316_3308.h @@ -0,0 +1,34 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VSC_CROSSBAR_H_ +#define __VSC_CROSSBAR_H 1_ + +#include <common.h> +#include <i2c.h> +#include <errno.h> + +int vsc_if_enable(unsigned int vsc_addr); +int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +void vsc_wp_config(unsigned int vsc_addr); + +#endif /* __VSC_CROSSBAR_H_ */ diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index 6e39be169a..2c151f20f5 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index 3e9f4c3460..dbd6f6ab20 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index d39e7348b3..00932ae68d 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index c4039edf43..d054f20bce 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index cbd28312a0..f8116f601e 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index c4039edf43..d054f20bce 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index 4717036d50..133ec01036 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index c4039edf43..d054f20bce 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index 6c2dfe8ec4..fc68de1ba1 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 4ba1964f7e..ad49874c5a 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -29,6 +29,9 @@ SECTIONS { arch/m68k/cpu/mcf52x2/start.o (.text*) + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text*) + *(.text*) } _etext = .; @@ -65,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 80935f28bf..d25a36f651 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -71,9 +71,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index 40af8bc23c..6616594e7b 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index 19342ac214..bc40fd649d 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/bmw/Makefile b/board/freescale/m54418twr/Makefile index 4f88efafd4..1e53f48f5d 100644 --- a/board/bmw/Makefile +++ b/board/freescale/m54418twr/Makefile @@ -1,10 +1,5 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright 2010-2012 Freescale Semiconductor, Inc. +# TsiChung Liew (Tsi-Chung.Liew@freescale.com) # # See file CREDITS for list of people who contributed to this # project. @@ -29,16 +24,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o - -SOBJS = early_init.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/bmw/config.mk b/board/freescale/m54418twr/config.mk index a1a44e5811..a592335861 100644 --- a/board/bmw/config.mk +++ b/board/freescale/m54418twr/config.mk @@ -1,6 +1,5 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright 2010-2012 Freescale Semiconductor, Inc. +# TsiChung Liew (Tsi-Chung.Liew@freescale.com) # # See file CREDITS for list of people who contributed to this # project. @@ -21,10 +20,6 @@ # MA 02111-1307 USA # -# -# BMW board -# +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp -# NOTE: The flags below affect how the BCM570x driver is compiled -PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\ - -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c new file mode 100644 index 0000000000..6e57bef896 --- /dev/null +++ b/board/freescale/m54418twr/m54418twr.c @@ -0,0 +1,129 @@ +/* + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/immap.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + /* + * need to to: + * Check serial flash size. if 2mb evb, else 8mb demo + */ + puts("Board: "); + puts("Freescale MCF54418 Tower System\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + u32 dramsize; + +#if defined(CONFIG_SERIAL_BOOT) + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; +#else + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + ccm_t *ccm = (ccm_t *)MMAP_CCM; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pm_t *pm = (pm_t *) MMAP_PM; + u32 i; + + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + + out_8(&pm->pmcr0, 0x2E); + out_8(&gpio->mscr_sdram, 1); + + clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); + setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); + + out_be32(&sdram->rcrcr, 0x40000000); + out_be32(&sdram->padcr, 0x01030203); + + out_be32(&sdram->cr00, 0x01010101); + out_be32(&sdram->cr01, 0x00000101); + out_be32(&sdram->cr02, 0x01010100); + out_be32(&sdram->cr03, 0x01010000); + out_be32(&sdram->cr04, 0x00010101); + out_be32(&sdram->cr06, 0x00010100); + out_be32(&sdram->cr07, 0x00000001); + out_be32(&sdram->cr08, 0x01000001); + out_be32(&sdram->cr09, 0x00000100); + out_be32(&sdram->cr10, 0x00010001); + out_be32(&sdram->cr11, 0x00000200); + out_be32(&sdram->cr12, 0x01000002); + out_be32(&sdram->cr13, 0x00000000); + out_be32(&sdram->cr14, 0x00000100); + out_be32(&sdram->cr15, 0x02000100); + out_be32(&sdram->cr16, 0x02000407); + out_be32(&sdram->cr17, 0x02030007); + out_be32(&sdram->cr18, 0x02000100); + out_be32(&sdram->cr19, 0x0A030203); + out_be32(&sdram->cr20, 0x00020708); + out_be32(&sdram->cr21, 0x00050008); + out_be32(&sdram->cr22, 0x04030002); + out_be32(&sdram->cr23, 0x00000004); + out_be32(&sdram->cr24, 0x020A0000); + out_be32(&sdram->cr25, 0x0C00000E); + out_be32(&sdram->cr26, 0x00002004); + out_be32(&sdram->cr28, 0x00100010); + out_be32(&sdram->cr29, 0x00100010); + out_be32(&sdram->cr31, 0x07990000); + out_be32(&sdram->cr40, 0x00000000); + out_be32(&sdram->cr41, 0x00C80064); + out_be32(&sdram->cr42, 0x44520002); + out_be32(&sdram->cr43, 0x00C80023); + out_be32(&sdram->cr45, 0x0000C350); + out_be32(&sdram->cr56, 0x04000000); + out_be32(&sdram->cr57, 0x03000304); + out_be32(&sdram->cr58, 0x40040000); + out_be32(&sdram->cr59, 0xC0004004); + out_be32(&sdram->cr60, 0x0642C000); + out_be32(&sdram->cr61, 0x00000642); + asm("tpf"); + + out_be32(&sdram->cr09, 0x01000100); + + udelay(100); +#endif + return dramsize; +}; + +int testdram(void) +{ + return 0; +} diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds new file mode 100644 index 0000000000..f341449346 --- /dev/null +++ b/board/freescale/m54418twr/u-boot.lds @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text : + { + arch/m68k/cpu/mcf5445x/start.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end__ = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 45924b7514..91328a4af6 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index f341449346..36a4c264b9 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index 5472689b5b..de4d0eb907 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index cf3f38c0f3..fbbe0c5dc5 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 79eb7aca38..29ad0e6e79 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -57,9 +57,11 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = ALIGN(4); diff --git a/board/sbc8560/Makefile b/board/freescale/t4qds/Makefile index ce0156040a..ff09ffa51e 100644 --- a/board/sbc8560/Makefile +++ b/board/freescale/t4qds/Makefile @@ -1,9 +1,5 @@ # -# (C) Copyright 2004-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. -# Added support for Wind River SBC8560 board +# Copyright 2012 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. @@ -15,7 +11,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -29,9 +25,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-$(CONFIG_T4240QDS)+= eth.o +COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) @@ -40,6 +38,12 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + ######################################################################### # defines $(obj).depend target diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c new file mode 100644 index 0000000000..692616aed4 --- /dev/null +++ b/board/freescale/t4qds/ddr.c @@ -0,0 +1,186 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, + {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c new file mode 100644 index 0000000000..a49c7d4f15 --- /dev/null +++ b/board/freescale/t4qds/eth.c @@ -0,0 +1,495 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> +#include <asm/fsl_serdes.h> +#include "../common/qixis.h" +#include "../common/fman.h" + +#include "t4240qds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII 0 +#define EMI1_SLOT1 1 +#define EMI1_SLOT2 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT7 7 +#define EMI2 8 /* tmp, FIXME */ +/* Slot6 and Slot8 do not have EMI connections */ + +static int mdio_mux[NUM_FM_PORTS]; + +static const char *mdio_names[] = { + "T4240QDS_MDIO0", + "T4240QDS_MDIO1", + "T4240QDS_MDIO2", + "T4240QDS_MDIO3", + "T4240QDS_MDIO4", + "T4240QDS_MDIO5", + "NULL", + "T4240QDS_MDIO7", + "T4240QDS_10GC", +}; + +static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; +static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; + +static const char *t4240qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t4240qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t4240qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t4240qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if ((muxval < 6) || (muxval == 7)) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t4240qds_mdio *priv = bus->priv; + + t4240qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t4240qds_mdio *priv = bus->priv; + + t4240qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t4240qds_mdio_reset(struct mii_dev *bus) +{ + struct t4240qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t4240qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t4240qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate T4240QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate T4240QDS private data\n"); + free(bus); + return -1; + } + + bus->read = t4240qds_mdio_read; + bus->write = t4240qds_mdio_write; + bus->reset = t4240qds_mdio_reset; + sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + if (mdio_mux[port] == EMI1_RGMII) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); + + /* TODO: will do with dts */ +} + +void fdt_fixup_board_enet(void *fdt) +{ + /* TODO: will do with dts */ +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + + switch (srds_prtcl_s1) { + case 1: + case 2: + case 4: + /* XAUI/HiGig in Slot1 and Slot2 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + break; + case 28: + case 36: + /* SGMII in Slot1 and Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, + SGMII_CARD_PORT3_PHY_ADDR); + } + break; + case 38: + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC9, + QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, + QSGMII_CARD_PHY_ADDR); + } + break; + case 40: + case 46: + case 48: + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC10, + SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT4_PHY_ADDR); + } + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + default: + puts("Invalid SerDes1 protocol for T4240QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + /* FM1 DTSEC5 routes to RGMII with EC2 */ + debug("FM1@DTSEC%u is RGMII at address %u\n", + idx + 1, 2); + if (i == FM1_DTSEC5) + fm_info_set_phy_address(i, 2); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + +#if (CONFIG_SYS_NUM_FMAN == 2) + switch (srds_prtcl_s2) { + case 1: + case 2: + case 4: + /* XAUI/HiGig in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); + break; + case 7: + case 13: + case 14: + case 16: + case 22: + case 23: + case 25: + case 26: + /* XAUI/HiGig in Slot3, SGMII in Slot4 */ + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 28: + case 36: + /* SGMII in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; + case 38: + /* QSGMII in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR); + break; + case 40: + case 46: + case 48: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + /* QSGMII in Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + case 50: + case 52: + case 54: + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + case 56: + case 57: + /* XFI in Slot3, SGMII in Slot4 */ + fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + puts("Invalid SerDes2 protocol for T4240QDS\n"); + break; + } + + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_2, + SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * If DTSEC5 is RGMII, then it's routed via via EC1 to + * the first on-board RGMII port. If DTSEC6 is RGMII, + * then it's routed via via EC2 to the second on-board + * RGMII port. + */ + debug("FM2@DTSEC%u is RGMII at address %u\n", + idx + 1, i == FM2_DTSEC5 ? 1 : 2); + fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c new file mode 100644 index 0000000000..5debcf612a --- /dev/null +++ b/board/freescale/t4qds/law.c @@ -0,0 +1,47 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/bmw/m48t59y.h b/board/freescale/t4qds/pci.c index 717300d957..fc00b4ad6d 100644 --- a/board/bmw/m48t59y.h +++ b/board/freescale/t4qds/pci.c @@ -1,12 +1,5 @@ /* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,31 +20,20 @@ * MA 02111-1307 USA */ -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h new file mode 100644 index 0000000000..efb718d2c3 --- /dev/null +++ b/board/freescale/t4qds/t4240qds_qixis.h @@ -0,0 +1,56 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __T4020QDS_QIXIS_H__ +#define __T4020QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T4020QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_RESET 0x00 + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c new file mode 100644 index 0000000000..88b8cedf48 --- /dev/null +++ b/board/freescale/t4qds/t4qds.c @@ -0,0 +1,395 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "t4qds.h" +#include "t4240qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + static const char *freq[] = { + "100", "125", "156.25", "161.1328125"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("SERDES%u=%sMHz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +/* Configure Crossbar switches for Front-Side SerDes Ports */ +int config_frontside_crossbar_vsc3316(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + int ret; + + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + if (ret) + return ret; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + if (srds_prtcl_s1) { + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); + if (ret) + return ret; + } + + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + if (srds_prtcl_s2) { + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); + if (ret) + return ret; + } + + return 0; +} + +int config_backside_crossbar_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s3, srds_prtcl_s4; + u8 brdcfg; + + srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS3_PRTCL; + srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; + switch (srds_prtcl_s3) { + case 0: + /* SerDes3 is not enabled */ + break; + case 2: + case 9: + case 10: + /* SD3(0:7) => SLOT5(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT5; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 4: + case 6: + case 8: + case 12: + case 14: + case 16: + case 17: + case 19: + case 20: + /* SD3(4:7) => SLOT6(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT6; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes3 Protocol %d\n", + srds_prtcl_s3); + return -1; + } + + srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + switch (srds_prtcl_s4) { + case 0: + /* SerDes4 is not enabled */ + break; + case 2: + /* 10b, SD4(0:7) => SLOT7(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT7; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 4: + case 6: + case 8: + /* x1b, SD4(4:7) => SLOT8(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT8; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 10: + case 12: + case 14: + case 16: + case 18: + /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_AURO_SATA; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes4 Protocol %d\n", + srds_prtcl_s4); + return -1; + } + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connectoin */ + QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET); + + /* Configure board SERDES ports crossbar */ + config_frontside_crossbar_vsc3316(); + config_backside_crossbar_mux(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328125"; + default: + return "???"; + } +} + +int misc_init_r(void) +{ + u8 sw; + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[MAX_SERDES]; + unsigned int i; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; + break; + } + } + + for (i = 0; i < MAX_SERDES; i++) { + u32 pllcr0 = srds_regs->bank[i].pllcr0; + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES%u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h new file mode 100644 index 0000000000..c6a3492cb6 --- /dev/null +++ b/board/freescale/t4qds/t4qds.h @@ -0,0 +1,37 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, + {8, 8}, {9, 9}, {14, 14}, {15, 15} }; + +static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, + {10, 10}, {11, 11}, {12, 12}, {13, 13} }; + +static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, + {10, 11}, {11, 10}, {12, 2}, {13, 3} }; + +static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, + {8, 9}, {9, 8}, {14, 1}, {15, 0} }; +#endif diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c new file mode 100644 index 0000000000..078a6e415c --- /dev/null +++ b/board/freescale/t4qds/tlb.c @@ -0,0 +1,136 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index 87cb8e32ba..774c494f03 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -85,10 +85,11 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } .data : { diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 2fb44aa832..f6d13014f3 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -85,10 +85,11 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } .data : { diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 8719e97ee4..7df6e83392 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -85,10 +85,11 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } .data : { diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index 33890b504d..b241cbc1d0 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -84,10 +84,11 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } .data : { diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index cf6e5020ba..63c15b9117 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -84,10 +84,11 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } + . = ALIGN(4); - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } .data : { diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 5bb6c62d71..1cbe7e32ba 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -71,9 +71,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index be99b51208..dd89c70f56 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -71,9 +71,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 1d66a9b2bd..124b183516 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -80,9 +80,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index cfa4ef3f87..e1cf249650 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index ca9711575d..f02eb1c2aa 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -72,9 +72,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 8a197deef7..e84cc7991e 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 1309f209de..7afae0a625 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -110,9 +110,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index 99c48f28d4..dc8c4e958f 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 93c79a64b4..6778eb13ad 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 91d3e67e82..3e075a85bd 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index f697ccd515..0d6a0f3a3b 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -65,9 +65,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 4a59cea80f..8a871cff49 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -54,10 +54,9 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } uboot_end_data = .; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index 2f61b11d81..e47aff0fa7 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c index 71d64d434f..ab294794bd 100644 --- a/board/ivm/ivm.c +++ b/board/ivm/ivm.c @@ -333,13 +333,59 @@ void show_boot_progress (int status) void ide_set_reset (int on) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + int i; /* * Configure PC for IDE Reset Pin */ if (on) { /* assert RESET */ immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); + +#ifdef CONFIG_SYS_PB_12V_ENABLE + /* 12V Enable output OFF */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE); + + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE); + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE); + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE; + + /* wait 500 ms for the voltage to stabilize */ + for (i = 0; i < 500; ++i) + udelay(1000); +#endif /* CONFIG_SYS_PB_12V_ENABLE */ } else { /* release RESET */ +#ifdef CONFIG_SYS_PB_12V_ENABLE + /* 12V Enable output ON */ + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE; +#endif /* CONFIG_SYS_PB_12V_ENABLE */ + +#ifdef CONFIG_SYS_PB_IDE_MOTOR + /* configure IDE Motor voltage monitor pin as input */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR); + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR); + immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR); + +/* wait up to 1 s for the motor voltage to stabilize */ + for (i = 0; i < 1000; ++i) { + if ((immr->im_cpm.cp_pbdat + & CONFIG_SYS_PB_IDE_MOTOR) != 0) + break; + udelay(1000); + } + + if (i == 1000) { /* Timeout */ + printf("\nWarning: 5V for IDE Motor missing\n"); +#ifdef CONFIG_STATUS_LED +#ifdef STATUS_LED_YELLOW + status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON); +#endif +#ifdef STATUS_LED_GREEN + status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF); +#endif +#endif /* CONFIG_STATUS_LED */ + } +#endif /* CONFIG_SYS_PB_IDE_MOTOR */ + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; } diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 1e843eb24e..4cca652748 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 732a46f272..53a19b2947 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index e01a633aae..83a8753e5a 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ -#else +#elif !defined(CONFIG_MPC8309) /* Local Bus */ {0, 16, 1, 0, 3}, /* LA00 */ {0, 17, 1, 0, 3}, /* LA01 */ diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 525c97aea6..54f25e097c 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 << 24) #define SMSTPCR1_I2C0 (1 << 16) #define SMSTPCR3_USB (1 << 22) +#define SMSTPCR3_I2C1 (1 << 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -287,8 +288,8 @@ int board_early_init_f(void) clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); - clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); + clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, &cpg->vclkcr1); /* Setup SCIF4 / workaround */ @@ -343,6 +344,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index 6a017e305c..033cff42d9 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -108,10 +108,10 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 4491edd944..b43a1e4281 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 4491edd944..b43a1e4281 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index de0b355a62..94118024bd 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 856a99b6f9..e788f5c170 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index f3e3fce824..541c958fca 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -37,7 +37,6 @@ #define IT8212_PCI_IdeBusSkewCONTROL 0x4c #define IT8212_PCI_IdeDrivingCURRENT 0x42 -extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; extern struct pci_controller hose; int ide_preinit (void) diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index 3527b381df..ef2cc24aae 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -29,6 +29,7 @@ #include <netdev.h> #include <asm/arch/pxa.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/regs-mmc.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,14 @@ int board_init (void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int board_late_init(void) { setenv("stdout", "serial"); diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 8bf7324f37..bc71b0d2c1 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 241223481b..0a3e6466a9 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index 731cec9af7..e32ae37ea4 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 57c37deb89..5a3a9eabbf 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -74,9 +74,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index a95c47feac..4155b604fb 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds index 3a05ef9049..2ce8d0e158 100644 --- a/board/micronas/vct/u-boot.lds +++ b/board/micronas/vct/u-boot.lds @@ -53,10 +53,8 @@ SECTIONS .sdata : { *(.sdata*) } . = ALIGN(4); - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + .u_boot_list : { + #include <u-boot.lst> } . = ALIGN(4); diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index dae2cfc7da..43f91f1a3c 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -60,9 +60,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index b3364be48c..5255651347 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -85,9 +85,6 @@ SECTIONS } > ram */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; __start___ex_table = .; __ex_table : { *(__ex_table) } > ram diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index b4b9e02e52..29a34fb9c5 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -102,9 +102,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index fcf8ebbf8e..d7a2e56008 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index 11624d21f5..c378564f6d 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -70,9 +70,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index a949e4f592..cdc1fdac2c 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index a001f3fd87..900da64859 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index a949e4f592..cdc1fdac2c 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index a001f3fd87..900da64859 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index a949e4f592..cdc1fdac2c 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index a001f3fd87..900da64859 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index a949e4f592..cdc1fdac2c 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 6c7d698c95..6cbf4dc66e 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index fd4e8a50d5..c8d38942c9 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index c7711028ad..92796e6744 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds index 1aed197bb9..4cffacbd46 100644 --- a/board/openrisc/openrisc-generic/u-boot.lds +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -26,9 +26,11 @@ SECTIONS _endtext = .; } > ram - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } > ram - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } .rodata : { *(.rodata); diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index b23eec805e..590ca414aa 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -24,6 +24,7 @@ #include <serial.h> #include <asm/io.h> #include <asm/arch/pxa.h> +#include <asm/arch/regs-mmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,6 +52,14 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index bd0dee1efb..07ddd364a0 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -54,10 +54,9 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } uboot_end_data = .; diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c index 5f89d9b125..de61ca0e56 100644 --- a/board/pcippc2/fpga_serial.c +++ b/board/pcippc2/fpga_serial.c @@ -73,13 +73,6 @@ void fpga_serial_putc (char c) } } -void fpga_serial_puts (const char *s) -{ - while (*s) { - fpga_serial_print (*s++); - } -} - int fpga_serial_getc (void) { while ((in8 (UART (LSR)) & 0x01) == 0); diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h index 52750143c4..106fbf7a50 100644 --- a/board/pcippc2/fpga_serial.h +++ b/board/pcippc2/fpga_serial.h @@ -26,7 +26,6 @@ extern void fpga_serial_init (int); extern void fpga_serial_putc (char); -extern void fpga_serial_puts (const char *); extern int fpga_serial_getc (void); extern int fpga_serial_tstc (void); extern void fpga_serial_setbrg (void); diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 4a91458e8e..5e6fc58cf7 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -29,6 +29,7 @@ #include <watchdog.h> #include <pci.h> #include <netdev.h> +#include <serial.h> #include "hardware.h" #include "pcippc2.h" @@ -129,7 +130,7 @@ int misc_init_r (void) fpga_serial_init (sconsole_get_baudrate ()); sconsole_putc = fpga_serial_putc; - sconsole_puts = fpga_serial_puts; + sconsole_puts = default_serial_puts; sconsole_getc = fpga_serial_getc; sconsole_tstc = fpga_serial_tstc; sconsole_setbrg = fpga_serial_setbrg; diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 746a54c5e3..f8345ddb46 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -32,6 +32,7 @@ #include <sha1.h> #include <asm/io.h> #include <net.h> +#include <ata.h> DECLARE_GLOBAL_DATA_PTR; @@ -672,7 +673,6 @@ U_BOOT_CMD( * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) * These values are shifted */ -extern ulong *ide_bus_offset; void inline ide_outb(int dev, int port, unsigned char val) { debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", @@ -714,3 +714,58 @@ void ide_set_reset (int idereset) udelay (10000); } #endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + + +/* this is motly the same as it should, causing a little code duplication */ +#if defined(CONFIG_CMD_IDE) +#define EIEIO __asm__ volatile ("eieio") + +void ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + volatile ushort *pbuf = + (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + ushort *dbuf = (ushort *) sect_buf; + + debug("in input swap data base for read is %lx\n", + (unsigned long) pbuf); + + while (words--) { + *dbuf++ = *pbuf; + *dbuf++ = *pbuf; + } +} + +void ide_output_data(int dev, const ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + dbuf = (ushort *) sect_buf; + while (words--) { + EIEIO; + *pbuf = ld_le16(dbuf++); + EIEIO; + *pbuf = ld_le16(dbuf++); + } +} + +void ide_input_data(int dev, ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + dbuf = (ushort *) sect_buf; + + debug("in input data base for read is %lx\n", (unsigned long) pbuf); + + while (words--) { + EIEIO; + *dbuf++ = ld_le16(pbuf); + EIEIO; + *dbuf++ = ld_le16(pbuf); + } +} + +#endif diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c index 2f4d294b9d..3536933c00 100644 --- a/board/prodrive/p3mx/serial.c +++ b/board/prodrive/p3mx/serial.c @@ -75,21 +75,13 @@ static void p3mx_serial_setbrg(void) galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } - -static void p3mx_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device p3mx_serial_drv = { .name = "p3mx_serial", .start = p3mx_serial_init, .stop = NULL, .setbrg = p3mx_serial_setbrg, .putc = p3mx_serial_putc, - .puts = p3mx_serial_puts, + .puts = default_serial_puts, .getc = p3mx_serial_getc, .tstc = p3mx_serial_tstc, }; diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 877e8d9b2a..9931efdc08 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -35,6 +35,7 @@ #include <command.h> #include <asm/io.h> #include <asm/arch/pxa.h> +#include <asm/arch/regs-mmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -77,6 +78,14 @@ int board_init (void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int board_late_init(void) { setenv("stdout", "serial"); diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk deleted file mode 100644 index 27cd34ac36..0000000000 --- a/board/qemu-mips/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Qemu -M mips system emulator -# See http://fabrice.bellard.free.fr/qemu -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80001000 diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 9460b2010c..cb2356f731 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,11 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ +#if defined(CONFIG_64BIT) +OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips") +#else OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS @@ -55,15 +59,17 @@ SECTIONS . = ALIGN(4); .sdata : { *(.sdata*) } - . = .; - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } uboot_end_data = .; +#if defined(CONFIG_64BIT) + num_got_entries = (__got_end - __got_start) >> 3; +#else num_got_entries = (__got_end - __got_start) >> 2; +#endif . = ALIGN(4); .sbss : { *(.sbss*) } diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds index 7317652569..b3cb869748 100644 --- a/board/qi/qi_lb60/u-boot.lds +++ b/board/qi/qi_lb60/u-boot.lds @@ -47,9 +47,11 @@ SECTIONS .sdata : { *(.sdata*) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 2fa085a3d9..3ef0d9e0b7 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index d943fb6de7..a86b568f6e 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -77,9 +77,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; __start___ex_table = .; diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index 38ebe88507..cf406ce966 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -77,13 +77,10 @@ SECTIONS } PROVIDE (_egot = .); - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); + + .u_boot_list : { + #include <u-boot.lst> } - PROVIDE (__u_boot_cmd_end = .); PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index a729c52626..ff950294f3 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -97,9 +97,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index d78dd77efd..951d8cec1d 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -48,6 +48,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } >.sram + . = ALIGN(4); + /* Align .machine_param on 256 byte boundary for easier searching */ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram . = ALIGN(4); diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index f1628152d3..fbb442a02b 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -47,11 +47,13 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - . = ALIGN(4); + . = align(4); + .u_boot_list : { + #include <u-boot.lst> + } + + . = align(4); .mmudata : { *(.mmudata) } . = ALIGN(4); diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 31746e3adc..7a0757f146 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -115,9 +115,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 4922bd241e..07bd6fe19f 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -115,9 +115,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index e382fd1a1e..ae3afa1130 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -68,9 +68,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/sbc8560/README b/board/sbc8560/README deleted file mode 100644 index c4b642236e..0000000000 --- a/board/sbc8560/README +++ /dev/null @@ -1,57 +0,0 @@ -The port was tested on Wind River System Sbc8560 board -<www.windriver.com>. U-Boot was installed on the flash memory of the -CPU card (no the SODIMM). - -NOTE: Please configure uboot compile to the proper PCI frequency and -setup the appropriate DIP switch settings. - -SBC8560 board: - -Make sure boards switches are set to their appropriate conditions. -Refer to the Engineering Reference Guide ERG-00300-002. Of particular -importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which -select the on-board FLASH device (Intel 28F128Jx); 2) The settings -for the Clock SW9 (33 MHz or 66 MHz). - - Note: SW9 Settings: 66 MHz - 4:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on - Note: SW9 Settings: 33 MHz - 8:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on - - -Flashing the FLASH device with the "Wind River ICE": - -1) Properly connect and configure the Wind River ICE to the target - JTAG port. This includes running the SBC8560 register script. Make - sure target memory can be read and written. - -2) Build the u-boot image: - make distclean - make SBC8560_66_config or SBC8560_33_config - make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all - - Note: reference is made to the ELDK3.0 compiler. Further, it seems - the ppc_8xx compiler is required for the 85xx (no 85xx - designated compiler in ELDK3.0) - -3) Convert the uboot (.elf) file to a uboot.bin file (using - visionClick converter). The bin file should be converted from - fffc0000 to ffffffff - -4) Setup the Flash Utility (tools menu) for: - - Do a "dc clr" [visionClick] to load the default register settings - Determine the clock speed of the PCI bus and set SW9 accordingly - Note: the speed of the PCI bus defaults to the slowest PCI card - PlayBack the "default" register file for the SBC8560 - Select the uboot.bin file with zero bias - Select the initialize Target prior to programming - Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm - Select the erase base address from FFFC0000 to FFFFFFFF - Select the start address from 0 with size of 4000 - -5) Erase and Program diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c deleted file mode 100644 index e9babc6477..0000000000 --- a/board/sbc8560/ddr.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c deleted file mode 100644 index 4e6baed2f4..0000000000 --- a/board/sbc8560/law.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(512M) -or- larger - * c000_0000-cfff_ffff: PCI(256M) - * d000_0000-dfff_ffff: RapidIO(256M) - * e000_0000-ffff_ffff: localbus(512M) - * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 - * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 - * e800_0000-efff_ffff: LBC 128M, nothing here - * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 - * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 - * f800_0000-fdff_ffff: LBC 64M, nothing here - * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 - * fd00_0000-fdff_ffff: LBC 16M, nothing here - * fe00_0000-feff_ffff: LBC 16M, nothing here - * ff00_0000-ff6f_ffff: LBC 7M, nothing here - * ff70_0000-ff7f_ffff: CCSRBAR 1M - * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c deleted file mode 100644 index 98bc7df4c8..0000000000 --- a/board/sbc8560/sbc8560.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int board_early_init_f (void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr[0] &= ~0x20; - udelay(2); - bcsr[0] |= 0x20; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr[0] &= ~0x10; - udelay(2); - bcsr[0] |= 0x10; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -} - -int checkboard (void) -{ - sys_info_t sysinfo; - char buf[32]; - - get_sys_info (&sysinfo); - -#ifdef CONFIG_SBC8560 - printf ("Board: Wind River SBC8560 Board\n"); -#else - printf ("Board: Wind River SBC8540 Board\n"); -#endif - printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0])); - printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); - printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2)); - if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ - || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %s MHz\n", - strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f))); - } else { - printf("\tLBC: unknown\n"); - } - printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); - return (0); -} - - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 - - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - -#if (CONFIG_SYS_SDRAM_SIZE == 512) - ddr->cs0_bnds = 0x0000000f; -#else - ddr->cs0_bnds = 0x00000007; -#endif - ddr->cs1_bnds = 0x0010001f; - ddr->cs2_bnds = 0x00000000; - ddr->cs3_bnds = 0x00000000; - ddr->cs0_config = 0x80000102; - ddr->cs1_config = 0x80000102; - ddr->cs2_config = 0x00000000; - ddr->cs3_config = 0x00000000; - ddr->timing_cfg_1 = 0x37334321; - ddr->timing_cfg_2 = 0x00000800; - ddr->sdram_cfg = 0x42000000; - ddr->sdram_mode = 0x00000022; - ddr->sdram_interval = 0x05200100; - ddr->err_sbe = 0x00ff0000; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - int node; -#ifdef CONFIG_PCI - const char *path; -#endif - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c deleted file mode 100644 index fe0ac763af..0000000000 --- a/board/sbc8560/tlb.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { -/* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -/* TLB for Local Bus stuff, just map the whole 512M */ -/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - - SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_256M, 1), -#endif - - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_16K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 0e78e4fd47..c0f107319e 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index 02d198001f..6cf7a01738 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 9ab248a4e9..f57f8a0258 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -69,9 +69,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index d0b60cf7c1..18f962cfa5 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index a84e7fd35b..f69e39d583 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index a95c47feac..4155b604fb 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index a949e4f592..cdc1fdac2c 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index a001f3fd87..900da64859 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index c65f0228c3..163587512b 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -83,9 +83,11 @@ SECTIONS . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c index a3983e376b..188e4acc09 100644 --- a/board/ti/omap2420h4/omap2420h4.c +++ b/board/ti/omap2420h4/omap2420h4.c @@ -153,7 +153,7 @@ void wait_for_command_complete(unsigned int wd_base) ******************************************************************/ void ether_init (void) { -#ifdef CONFIG_DRIVER_LAN91C96 +#ifdef CONFIG_LAN91C96 int cnt = 20; __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index e905c26c6f..7cc41cd521 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -81,9 +81,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 871e052b04..c3dee8459e 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -34,6 +34,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> #include <asm/arch/pxa.h> +#include <asm/arch/regs-mmc.h> #include <netdev.h> #include <asm/io.h> @@ -152,3 +153,11 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index e62d53db54..fd2d72e8ae 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 1958c2fb90..20161a46a6 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -57,6 +57,10 @@ SECTIONS *(.data) } + .u_boot_list : { + #include <u-boot.lst> + } + . = ALIGN(4); .rel.dyn : { diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 1c67b301fb..2ce5a9a71c 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -106,9 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 3470b437e8..9b69d3d1e6 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -75,9 +75,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } . = .; diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 91d3e67e82..3e075a85bd 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -107,9 +107,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index e2e66aec99..c4e5706543 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -111,9 +111,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> + } __start___ex_table = .; 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