diff options
Diffstat (limited to 'board')
97 files changed, 4331 insertions, 7921 deletions
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 15225b0724..39afbba7db 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -12,6 +12,10 @@ #ifndef _BUR_COMMON_H_ #define _BUR_COMMON_H_ +#include <../../../drivers/video/am335x-fb.h> + +int load_lcdtiming(struct am335x_lcdpanel *panel); +void br_summaryscreen(void); void blink(u32 blinks, u32 intervall, u32 pin); void pmicsetup(u32 mpupll); void enable_uart0_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 25cbe62b1f..5ff8a7e0ae 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -9,7 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ * */ - +#include <version.h> #include <common.h> #include <errno.h> #include <spl.h> @@ -26,10 +26,421 @@ #include <miiphy.h> #include <cpsw.h> #include <power/tps65217.h> +#include <lcd.h> +#include <fs.h> +#ifdef CONFIG_USE_FDT + #include <fdt_support.h> +#endif #include "bur_common.h" +#include "../../../drivers/video/am335x-fb.h" static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USE_FDT + #define FDTPROP(a, b, c) fdt_getprop_u32_default((void *)a, b, c, ~0UL) + #define PATHTIM "/panel/display-timings/default" + #define PATHINF "/panel/panel-info" +#endif /* --------------------------------------------------------------------------*/ +#if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \ + !defined(CONFIG_SPL_BUILD) +int load_lcdtiming(struct am335x_lcdpanel *panel) +{ + struct am335x_lcdpanel pnltmp; +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + u32 dtbprop; + + if (dtbaddr == ~0UL) { + puts("load_lcdtiming: failed to get 'dtbaddr' from env!\n"); + return -1; + } + memcpy(&pnltmp, (void *)panel, sizeof(struct am335x_lcdpanel)); + + pnltmp.hactive = FDTPROP(dtbaddr, PATHTIM, "hactive"); + pnltmp.vactive = FDTPROP(dtbaddr, PATHTIM, "vactive"); + pnltmp.bpp = FDTPROP(dtbaddr, PATHINF, "bpp"); + pnltmp.hfp = FDTPROP(dtbaddr, PATHTIM, "hfront-porch"); + pnltmp.hbp = FDTPROP(dtbaddr, PATHTIM, "hback-porch"); + pnltmp.hsw = FDTPROP(dtbaddr, PATHTIM, "hsync-len"); + pnltmp.vfp = FDTPROP(dtbaddr, PATHTIM, "vfront-porch"); + pnltmp.vbp = FDTPROP(dtbaddr, PATHTIM, "vback-porch"); + pnltmp.vsw = FDTPROP(dtbaddr, PATHTIM, "vsync-len"); + pnltmp.pup_delay = FDTPROP(dtbaddr, PATHTIM, "pupdelay"); + pnltmp.pon_delay = FDTPROP(dtbaddr, PATHTIM, "pondelay"); + + /* calc. proper clk-divisor */ + dtbprop = FDTPROP(dtbaddr, PATHTIM, "clock-frequency"); + if (dtbprop != ~0UL) + pnltmp.pxl_clk_div = 192000000 / dtbprop; + else + pnltmp.pxl_clk_div = ~0UL; + + /* check polarity of control-signals */ + dtbprop = FDTPROP(dtbaddr, PATHTIM, "hsync-active"); + if (dtbprop == 0) + pnltmp.pol |= HSYNC_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "vsync-active"); + if (dtbprop == 0) + pnltmp.pol |= VSYNC_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-ctrl"); + if (dtbprop == 1) + pnltmp.pol |= HSVS_CONTROL; + dtbprop = FDTPROP(dtbaddr, PATHINF, "sync-edge"); + if (dtbprop == 1) + pnltmp.pol |= HSVS_RISEFALL; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "pixelclk-active"); + if (dtbprop == 0) + pnltmp.pol |= PXCLK_INVERT; + dtbprop = FDTPROP(dtbaddr, PATHTIM, "de-active"); + if (dtbprop == 0) + pnltmp.pol |= DE_INVERT; +#else + pnltmp.hactive = getenv_ulong("ds1_hactive", 10, ~0UL); + pnltmp.vactive = getenv_ulong("ds1_vactive", 10, ~0UL); + pnltmp.bpp = getenv_ulong("ds1_bpp", 10, ~0UL); + pnltmp.hfp = getenv_ulong("ds1_hfp", 10, ~0UL); + pnltmp.hbp = getenv_ulong("ds1_hbp", 10, ~0UL); + pnltmp.hsw = getenv_ulong("ds1_hsw", 10, ~0UL); + pnltmp.vfp = getenv_ulong("ds1_vfp", 10, ~0UL); + pnltmp.vbp = getenv_ulong("ds1_vbp", 10, ~0UL); + pnltmp.vsw = getenv_ulong("ds1_vsw", 10, ~0UL); + pnltmp.pxl_clk_div = getenv_ulong("ds1_pxlclkdiv", 10, ~0UL); + pnltmp.pol = getenv_ulong("ds1_pol", 16, ~0UL); + pnltmp.pup_delay = getenv_ulong("ds1_pupdelay", 10, ~0UL); + pnltmp.pon_delay = getenv_ulong("ds1_tondelay", 10, ~0UL); +#endif + if ( + ~0UL == (pnltmp.hactive) || + ~0UL == (pnltmp.vactive) || + ~0UL == (pnltmp.bpp) || + ~0UL == (pnltmp.hfp) || + ~0UL == (pnltmp.hbp) || + ~0UL == (pnltmp.hsw) || + ~0UL == (pnltmp.vfp) || + ~0UL == (pnltmp.vbp) || + ~0UL == (pnltmp.vsw) || + ~0UL == (pnltmp.pxl_clk_div) || + ~0UL == (pnltmp.pol) || + ~0UL == (pnltmp.pup_delay) || + ~0UL == (pnltmp.pon_delay) + ) { + puts("lcd-settings in env/dtb incomplete!\n"); + printf("display-timings:\n" + "================\n" + "hactive: %d\n" + "vactive: %d\n" + "bpp : %d\n" + "hfp : %d\n" + "hbp : %d\n" + "hsw : %d\n" + "vfp : %d\n" + "vbp : %d\n" + "vsw : %d\n" + "pxlclk : %d\n" + "pol : 0x%08x\n" + "pondly : %d\n", + pnltmp.hactive, pnltmp.vactive, pnltmp.bpp, + pnltmp.hfp, pnltmp.hbp, pnltmp.hsw, + pnltmp.vfp, pnltmp.vbp, pnltmp.vsw, + pnltmp.pxl_clk_div, pnltmp.pol, pnltmp.pon_delay); + + return -1; + } + debug("lcd-settings in env complete, taking over.\n"); + memcpy((void *)panel, + (void *)&pnltmp, + sizeof(struct am335x_lcdpanel)); + + return 0; +} + +#ifdef CONFIG_USE_FDT +static int load_devicetree(void) +{ + char *dtbname = getenv("dtb"); + char *dtbdev = getenv("dtbdev"); + char *dtppart = getenv("dtbpart"); + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + loff_t dtbsize; + + if (!dtbdev || !dtbdev) { + puts("load_devicetree: <dtbdev>/<dtbpart> missing.\n"); + return -1; + } + + if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) { + puts("load_devicetree: set_blk_dev failed.\n"); + return -1; + } + if (dtbname && dtbaddr != ~0UL) { + if (fs_read(dtbname, dtbaddr, 0, 0, &dtbsize) == 0) { + gd->fdt_blob = (void *)dtbaddr; + gd->fdt_size = dtbsize; + debug("loaded %d bytes of dtb onto 0x%08x\n", + (u32)dtbsize, dtbaddr); + return dtbsize; + } + puts("load_devicetree: load dtb failed,file does not exist!\n"); + } + + puts("load_devicetree: <dtb>/<dtbaddr> missing!\n"); + return -1; +} + +static const char *dtbmacaddr(u32 ifno) +{ + int node, len; + char enet[16]; + const char *mac; + const char *path; + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("dtbmacaddr: failed to get 'dtbaddr' from env!\n"); + return NULL; + } + + node = fdt_path_offset((void *)dtbaddr, "/aliases"); + if (node < 0) + return NULL; + + sprintf(enet, "ethernet%d", ifno); + path = fdt_getprop((void *)dtbaddr, node, enet, NULL); + if (!path) { + printf("no alias for %s\n", enet); + return NULL; + } + + node = fdt_path_offset((void *)dtbaddr, path); + mac = fdt_getprop((void *)dtbaddr, node, "mac-address", &len); + if (mac && is_valid_ether_addr((u8 *)mac)) + return mac; + + return NULL; +} + +static void br_summaryscreen_printdtb(char *prefix, + char *name, + char *suffix) +{ + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + char buf[32] = { 0 }; + const char *nodep = buf; + char *mac = 0; + int nodeoffset; + int len; + + if (dtbaddr == ~0UL) { + puts("br_summaryscreen: failed to get 'dtbaddr' from env!\n"); + return; + } + + if (strcmp(name, "brmac1") == 0) { + mac = (char *)dtbmacaddr(0); + if (mac) + sprintf(buf, "%pM", mac); + } else if (strcmp(name, "brmac2") == 0) { + mac = (char *)dtbmacaddr(1); + if (mac) + sprintf(buf, "%pM", mac); + } else { + nodeoffset = fdt_path_offset((void *)dtbaddr, + "/factory-settings"); + if (nodeoffset < 0) { + puts("no 'factory-settings' in dtb!\n"); + return; + } + nodep = fdt_getprop((void *)dtbaddr, nodeoffset, name, &len); + } + if (nodep && strlen(nodep) > 1) + lcd_printf("%s %s %s", prefix, nodep, suffix); + else + lcd_printf("\n"); +} +int ft_board_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(blob, "/factory-settings"); + if (nodeoffset < 0) { + puts("set bootloader version 'factory-settings' not in dtb!\n"); + return -1; + } + if (fdt_setprop(blob, nodeoffset, "bl-version", + PLAIN_VERSION, strlen(PLAIN_VERSION)) != 0) { + puts("set bootloader version 'bl-version' prop. not in dtb!\n"); + return -1; + } + return 0; +} +#else + +static void br_summaryscreen_printenv(char *prefix, + char *name, char *altname, + char *suffix) +{ + char *envval = getenv(name); + if (0 != envval) { + lcd_printf("%s %s %s", prefix, envval, suffix); + } else if (0 != altname) { + envval = getenv(altname); + if (0 != envval) + lcd_printf("%s %s %s", prefix, envval, suffix); + } else { + lcd_printf("\n"); + } +} +#endif +void br_summaryscreen(void) +{ +#ifdef CONFIG_USE_FDT + br_summaryscreen_printdtb(" - B&R -", "order-no", "-\n"); + br_summaryscreen_printdtb(" Serial/Rev :", "serial-no", " /"); + br_summaryscreen_printdtb(" ", "hw-revision", "\n"); + br_summaryscreen_printdtb(" MAC (IF1) :", "brmac1", "\n"); + br_summaryscreen_printdtb(" MAC (IF2) :", "brmac2", "\n"); + lcd_puts(" Bootloader : " PLAIN_VERSION "\n"); + lcd_puts("\n"); +#else + br_summaryscreen_printenv(" - B&R -", "br_orderno", 0, "-\n"); + br_summaryscreen_printenv(" Serial/Rev :", "br_serial", 0, "\n"); + br_summaryscreen_printenv(" MAC (IF1) :", "br_mac1", "ethaddr", "\n"); + br_summaryscreen_printenv(" MAC (IF2) :", "br_mac2", 0, "\n"); + lcd_puts(" Bootloader : " PLAIN_VERSION "\n"); + lcd_puts("\n"); +#endif +} + +void lcdpower(int on) +{ + u32 pin, swval, i; +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("lcdpower: failed to get 'dtbaddr' from env!\n"); + return; + } + pin = FDTPROP(dtbaddr, PATHINF, "pwrpin"); +#else + pin = getenv_ulong("ds1_pwr", 16, ~0UL); +#endif + if (pin == ~0UL) { + puts("no pwrpin in dtb/env, cannot powerup display!\n"); + return; + } + + for (i = 0; i < 3; i++) { + if (pin != 0) { + swval = pin & 0x80 ? 0 : 1; + if (on) + gpio_direction_output(pin & 0x7F, swval); + else + gpio_direction_output(pin & 0x7F, !swval); + + debug("switched pin %d to %d\n", pin & 0x7F, swval); + } + pin >>= 8; + } +} + +vidinfo_t panel_info = { + .vl_col = 1366, /* + * give full resolution for allocating enough + * memory + */ + .vl_row = 768, + .vl_bpix = 5, + .priv = 0 +}; + +void lcd_ctrl_init(void *lcdbase) +{ + struct am335x_lcdpanel lcd_panel; +#ifdef CONFIG_USE_FDT + /* TODO: is there a better place to load the dtb ? */ + load_devicetree(); +#endif + memset(&lcd_panel, 0, sizeof(struct am335x_lcdpanel)); + if (load_lcdtiming(&lcd_panel) != 0) + return; + + lcd_panel.panel_power_ctrl = &lcdpower; + + if (0 != am335xfb_init(&lcd_panel)) + printf("ERROR: failed to initialize video!"); + /* + * modifiy panel info to 'real' resolution, to operate correct with + * lcd-framework. + */ + panel_info.vl_col = lcd_panel.hactive; + panel_info.vl_row = lcd_panel.vactive; + + lcd_set_flush_dcache(1); +} + +void lcd_enable(void) +{ +#ifdef CONFIG_USE_FDT + u32 dtbaddr = getenv_ulong("dtbaddr", 16, ~0UL); + + if (dtbaddr == ~0UL) { + puts("lcdpower: failed to get 'dtbaddr' from env!\n"); + return; + } + unsigned int driver = FDTPROP(dtbaddr, PATHINF, "brightdrv"); + unsigned int bright = FDTPROP(dtbaddr, PATHINF, "brightdef"); + unsigned int pwmfrq = FDTPROP(dtbaddr, PATHINF, "brightfdim"); +#else + unsigned int driver = getenv_ulong("ds1_bright_drv", 16, 0UL); + unsigned int bright = getenv_ulong("ds1_bright_def", 10, 50); + unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL); +#endif + unsigned int tmp; + struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE; + + bright = bright != ~0UL ? bright : 50; + + switch (driver) { + case 0: /* PMIC LED-Driver */ + /* brightness level */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, bright, 0xFF); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x0A, 0xFF); + break; + case 1: /* PWM using timer6 */ + if (pwmfrq != ~0UL) { + timerhw->tiocp_cfg = TCFG_RESET; + udelay(10); + while (timerhw->tiocp_cfg & TCFG_RESET) + ; + tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */ + timerhw->tldr = tmp; + timerhw->tcrr = tmp; + tmp = tmp + ((V_OSCK/pwmfrq)/100) * bright; + timerhw->tmar = tmp; + timerhw->tclr = (TCLR_PT | (2 << TCLR_TRG_SHIFT) | + TCLR_CE | TCLR_AR | TCLR_ST); + } else { + puts("invalid pwmfrq in env/dtb! skip PWM-setup.\n"); + } + break; + default: + puts("no suitable backlightdriver in env/dtb!\n"); + break; + } + br_summaryscreen(); +} +#elif CONFIG_SPL_BUILD +#else +#error "LCD-support with a suitable FB-Driver is mandatory !" +#endif /* CONFIG_LCD */ + void blink(u32 blinks, u32 intervall, u32 pin) { gpio_direction_output(pin, 0); @@ -43,6 +454,7 @@ void blink(u32 blinks, u32 intervall, u32 pin) gpio_set_value(pin, 0); } + #ifdef CONFIG_SPL_BUILD void pmicsetup(u32 mpupll) { @@ -115,6 +527,9 @@ void pmicsetup(u32 mpupll) /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + /* Set PWR_EN bit in Status Register */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_STATUS, TPS65217_PWR_OFF, TPS65217_PWR_OFF); } void set_uart_mux_conf(void) @@ -176,9 +591,9 @@ static struct cpsw_platform_data cpsw_data = { int board_eth_init(bd_t *bis) { int rv = 0; - uint8_t mac_addr[6]; + char mac_addr[6]; + const char *mac = 0; uint32_t mac_hi, mac_lo; - /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); @@ -192,14 +607,19 @@ int board_eth_init(bd_t *bis) #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { - printf("<ethaddr> not set. Validating first E-fuse MAC ... "); - - if (is_valid_ether_addr(mac_addr)) { - printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", - mac_addr[0], mac_addr[1], mac_addr[2], - mac_addr[3], mac_addr[4], mac_addr[5] - ); - eth_setenv_enetaddr("ethaddr", mac_addr); + #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT) + printf("<ethaddr> not set. trying DTB ... "); + mac = dtbmacaddr(0); + #endif + if (!mac) { + printf("<ethaddr> not set. validating E-fuse MAC ... "); + if (is_valid_ether_addr((const u8 *)mac_addr)) + mac = (const char *)mac_addr; + } + + if (mac) { + printf("using: %pM on ", mac); + eth_setenv_enetaddr("ethaddr", (const u8 *)mac); } } writel(MII_MODE_ENABLE, &cdev->miisel); @@ -221,3 +641,7 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(1, 0, 0, -1, -1); } #endif +int overwrite_console(void) +{ + return 1; +} diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 804765a8de..892311e6ee 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -26,14 +26,13 @@ #include <i2c.h> #include <power/tps65217.h> #include "../common/bur_common.h" +#include <lcd.h> /* -------------------------------------------------------------------------*/ /* -- defines for used GPIO Hardware -- */ -#define KEY (0+4) -#define LCD_PWR (0+5) -#define PUSH_KEY (0+31) -#define USB2SD_NRST (32+29) -#define USB2SD_PWR (96+13) +#define ESC_KEY (0+19) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) /* -------------------------------------------------------------------------*/ /* -- PSOC Resetcontroller Register defines -- */ @@ -46,6 +45,13 @@ /* -- defines for RSTCTRL_CTRLREG -- */ #define RSTCTRL_FORCE_PWR_NEN 0x0404 +#define RSTCTRL_CAN_STB 0x4040 + +#define VXWORKS_BOOTLINE 0x80001100 +#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks" +#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget" + +DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_BUILD) /* TODO: check ram-timing ! */ @@ -107,10 +113,13 @@ void am33xx_spl_board_init(void) &cmper->epwmss0clkctrl, &cmper->epwmss1clkctrl, &cmper->epwmss2clkctrl, + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, 0 }; do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); - + /* setup LCD-Pixel Clock */ + writel(0x2, CM_DPLL + 0x34); /* power-OFF LCD-Display */ gpio_direction_output(LCD_PWR, 0); @@ -121,7 +130,7 @@ void am33xx_spl_board_init(void) /* power-ON 3V3 via Resetcontroller */ oldspeed = i2c_get_bus_speed(); if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { - buf = RSTCTRL_FORCE_PWR_NEN; + buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, (uint8_t *)&buf, sizeof(buf)); i2c_set_bus_speed(oldspeed); @@ -129,15 +138,6 @@ void am33xx_spl_board_init(void) puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); } -#if defined(CONFIG_AM335X_USB0) - /* power on USB2SD Controller */ - gpio_direction_output(USB2SD_PWR, 1); - mdelay(1); - /* give a reset Pulse to USB2SD Controller */ - gpio_direction_output(USB2SD_NRST, 0); - mdelay(1); - gpio_set_value(USB2SD_NRST, 1); -#endif pmicsetup(0); } @@ -166,59 +166,111 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - const unsigned int ton = 250; const unsigned int toff = 1000; unsigned int cnt = 3; unsigned short buf = 0xAAAA; + unsigned char scratchreg = 0; unsigned int oldspeed; - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + /* try to read out some boot-instruction from resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + &scratchreg, sizeof(scratchreg)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } - if (gpio_get_value(KEY)) { + if (gpio_get_value(ESC_KEY)) { do { - /* turn on light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x09, 0xFF); - mdelay(ton); - /* turn off light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x01, 0xFF); + lcd_position_cursor(1, 8); + switch (cnt) { + case 3: + lcd_puts( + "release ESC-KEY to enter SERVICE-mode."); + break; + case 2: + lcd_puts( + "release ESC-KEY to enter DIAGNOSE-mode."); + break; + case 1: + lcd_puts( + "release ESC-KEY to enter BOOT-mode. "); + break; + } mdelay(toff); cnt--; - if (!gpio_get_value(KEY) && + if (!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && 2 == cnt) { + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); + cnt = 4; + break; + } else if (!gpio_get_value(ESC_KEY) && gpio_get_value(PUSH_KEY) && 1 == cnt) { - puts("updating from USB ...\n"); + lcd_position_cursor(1, 8); + lcd_puts( + "updating U-BOOT from USB ... "); setenv("bootcmd", "run usbupdate"); + cnt = 4; + break; + } else if ((!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0) || + (gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0)) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; break; - } else if (!gpio_get_value(KEY)) { + } else if (!gpio_get_value(ESC_KEY)) { break; } } while (cnt); + } else if (scratchreg == 0xCC) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting vxworks from network ... "); + setenv("bootcmd", "run netboot"); + cnt = 4; + } else if (scratchreg == 0xCD) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; + } else if (scratchreg == 0xCE) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting AR from eMMC ... "); + setenv("bootcmd", "run mmcboot"); + cnt = 4; } + lcd_position_cursor(1, 8); switch (cnt) { case 0: - puts("3 blinks ... entering BOOT mode.\n"); + lcd_puts("entering BOOT-mode. "); + setenv("bootcmd", "run defaultAR"); buf = 0x0000; break; case 1: - puts("2 blinks ... entering DIAGNOSE mode.\n"); + lcd_puts("entering DIAGNOSE-mode. "); buf = 0x0F0F; break; case 2: - puts("1 blinks ... entering SERVICE mode.\n"); + lcd_puts("entering SERVICE mode. "); buf = 0xB4B4; break; case 3: - puts("0 blinks ... entering RUN mode.\n"); + lcd_puts("loading OS... "); buf = 0x0404; break; } - mdelay(ton); - /* turn on light */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_WLEDCTRL1, 0x09, 0xFF); /* write bootinfo into scratchregister of resetcontroller */ oldspeed = i2c_get_bus_speed(); if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { @@ -228,6 +280,30 @@ int board_late_init(void) } else { puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); } + /* setup vxworks bootline */ + char *vxworksbootline = (char *)VXWORKS_BOOTLINE; + + /* setup default IP, in case if there is nothing in environment */ + if (!getenv("ipaddr")) { + setenv("ipaddr", "192.168.60.1"); + setenv("netmask", "255.255.255.0"); + setenv("serverip", "192.168.60.254"); + setenv("gatewayip", "192.168.60.254"); + puts("net: had no IP! made default setup.\n"); + } + + sprintf(vxworksbootline, + "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x", + DEFAULT_BOOTLINE, + getenv("serverip"), + getenv("ipaddr"), getenv("netmask"), + getenv("gatewayip"), + VXWORKS_USER, + (unsigned int) gd->fb_base-0x20, + (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), + (u32)getenv_ulong("vx_romfsbase", 16, 0), + (u32)getenv_ulong("vx_romfssize", 16, 0)); + /* * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does * expect that vectors are there, original u-boot moves them to _start diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index ecb2e7a427..9f89b5e53d 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -16,23 +16,17 @@ #include <asm/io.h> #include <i2c.h> -static struct module_pin_mux usb0_pin_mux[] = { - {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, - /* USB0 DrvBus Receiver disable (from romcode 0x20) */ - {OFFSET(usb0_drvvbus), (MODE(0))}, - /* USB1 DrvBus as GPIO due to HW-Workaround */ - {OFFSET(usb1_drvvbus), (MODE(7))}, - {-1}, -}; -static struct module_pin_mux spi1_pin_mux[] = { +static struct module_pin_mux spi0_pin_mux[] = { /* SPI1_SCLK */ - {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_D0 */ - {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_D1 */ - {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE}, /* SPI1_CS0 */ - {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, + /* SPI1_CS1 */ + {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, {-1}, }; @@ -53,30 +47,34 @@ static struct module_pin_mux dcan1_pin_mux[] = { }; static struct module_pin_mux gpios[] = { - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, - /* GPIO0_4 (SPI D1) - TA602 */ - {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ - {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* GPIO0_7 (PWW0 OUT) - CAN TERM */ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ - {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, - /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_19 (DMA_INTR0) - TA602 */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, /* GPIO0_30 (GPMC_WAIT0) - TA601 */ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO1_29 (gpmc_csn0) - MMC nRST */ + {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)}, /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO2_4 (GPMC_nWE) - TST_BAST */ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, + /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ @@ -126,6 +124,10 @@ static struct module_pin_mux mii1_pin_mux[] = { }; static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ @@ -187,8 +189,7 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(usb0_pin_mux); - configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); configure_module_pin_mux(dcan0_pin_mux); configure_module_pin_mux(dcan1_pin_mux); configure_module_pin_mux(mmc1_pin_mux); diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index c0178e75cf..9402aa4205 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -27,15 +27,15 @@ #include <i2c.h> #include <power/tps65217.h> #include "../common/bur_common.h" +#include <lcd.h> +#include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; /* --------------------------------------------------------------------------*/ /* -- defines for GPIO -- */ -#define ETHLED_ORANGE (96+16) /* GPIO3_16 */ #define REPSWITCH (0+20) /* GPIO0_20 */ - #if defined(CONFIG_SPL_BUILD) /* TODO: check ram-timing ! */ static const struct ddr_data ddr3_data = { @@ -82,7 +82,6 @@ static const struct ctrl_ioregs ddr3_ioregs = { int spl_start_uboot(void) { if (0 == gpio_get_value(REPSWITCH)) { - blink(5, 125, ETHLED_ORANGE); mdelay(1000); printf("SPL: entering u-boot instead kernel image.\n"); return 1; @@ -96,7 +95,35 @@ static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { - pmicsetup(1000); + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ + struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; + + /* + * in TRM they write a reset value of 1 (=CLK_M_OSC) for the + * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set + * the source of timer6 clk to CLK_M_OSC + */ + writel(0x01, &cmdpll->clktimer6clk); + + /* enable additional clocks of modules which are accessed later */ + u32 *const clk_domains[] = { + &cmper->lcdcclkstctrl, + 0 + }; + + u32 *const clk_modules_tsspecific[] = { + &cmper->lcdclkctrl, + &cmper->timer5clkctrl, + &cmper->timer6clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); + + /* setup LCD-Pixel Clock */ + writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ + + pmicsetup(0); } const struct dpll_params *get_dpll_ddr_params(void) @@ -116,6 +143,9 @@ void sdram_init(void) /* Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND gpmc_init(); @@ -126,24 +156,12 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - gpio_direction_output(ETHLED_ORANGE, 0); - if (0 == gpio_get_value(REPSWITCH)) { - printf("\n\n\n" - "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" - "!!!!!!! recovery switch activated !!!!!!!\n" - "!!!!!!! running usbupdate !!!!!!!\n" - "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n"); - setenv("bootcmd", "sleep 2; run netupdate;"); + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); } - - printf("turning on display power+backlight ... "); - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1, - 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */ - tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2, - 0x62, TPS65217_MASK_ALL_BITS); /* 100% */ - printf("ok.\n"); - return 0; } #endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 0ba25ee318..2c87a63b85 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -25,6 +25,13 @@ static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, {-1}, }; +static struct module_pin_mux uart1_pin_mux[] = { + /* UART0_RXD */ + {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; #ifdef CONFIG_MMC static struct module_pin_mux mmc1_pin_mux[] = { {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ @@ -131,9 +138,9 @@ static struct module_pin_mux gpIOs[] = { {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, - /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ - {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */ + /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ + {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, + /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, @@ -168,7 +175,14 @@ static struct module_pin_mux gpIOs[] = { {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, - +#ifndef CONFIG_NAND + /* GPIO2_3 - NAND_OE */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_4 - NAND_WEN */ + {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, + /* GPIO2_5 - NAND_BE_CLE */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, +#endif {-1}, }; @@ -229,5 +243,6 @@ void enable_board_pin_mux(void) #endif configure_module_pin_mux(spi0_pin_mux); configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(uart1_pin_mux); configure_module_pin_mux(gpIOs); } diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk deleted file mode 100644 index dfa84f032e..0000000000 --- a/board/LaCie/edminiv2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TEXT_BASE must equal the intended FLASH location of u-boot. -CONFIG_SYS_TEXT_BASE = 0xfff90000 diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 80ec7faa04..edf6281797 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -12,59 +12,11 @@ #include <miiphy.h> #include <asm/arch/orion5x.h> #include "../common/common.h" +#include <spl.h> +#include <ns16550.h> DECLARE_GLOBAL_DATA_PTR; -/* - * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH - * which CFI does not properly detect, hence the LEGACY config. - */ -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include <flash.h> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; - int sect; - - if (base != CONFIG_SYS_FLASH_BASE) - return 0; - - info->size = 0; - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - /* set each sector's start address and size based */ - for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { - info->start[sect] = base+info->size; - info->size += sectsz[sect]; - } - /* This flash must be accessed in 8-bits mode, no buffer. */ - info->flash_id = 0x01000000; - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->buffer_size = 0; - /* timings are derived from the Macronix datasheet. */ - info->erase_blk_tout = 1000; - info->write_tout = 10; - info->buffer_write_tout = 300; - /* Commands and addresses are for AMD mode 8-bit access. */ - info->vendor = CFI_CMDSET_AMD_LEGACY; - info->cmd_reset = 0xF0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->ext_addr = 0; - info->addr_unlock1 = 0x00000aaa; - info->addr_unlock2 = 0x00000555; - /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */ - info->manufacturer_id = 0x22; - info->device_id = 0xBA; - info->device_id2 = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->name = "MX29LV400CB"; - - return 1; -} -#endif /* CONFIG_SYS_FLASH_CFI */ - int board_init(void) { /* arch number of board */ @@ -83,3 +35,21 @@ void reset_phy(void) mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ + +/* + * SPL serial setup and NOR boot device selection + */ + +#ifdef CONFIG_SPL_BUILD + +void spl_board_init(void) +{ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig index fc42185a83..cbed8d6931 100644 --- a/board/altera/socfpga/Kconfig +++ b/board/altera/socfpga/Kconfig @@ -13,3 +13,19 @@ config SYS_CONFIG_NAME default "socfpga_cyclone5" endif + +if TARGET_SOCFPGA_ARRIA5 + +config SYS_BOARD + default "socfpga" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga" + +config SYS_CONFIG_NAME + default "socfpga_arria5" + +endif diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile index 44baa0068c..c867f73ff7 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/socfpga/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := socfpga_cyclone5.o +obj-y := socfpga.o obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c index b4b5ff8972..c79aa6d566 100644 --- a/board/altera/socfpga/iocsr_config.c +++ b/board/altera/socfpga/iocsr_config.c @@ -8,6 +8,7 @@ #include <iocsr_config.h> +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 const unsigned long iocsr_scan_chain0_table[(( CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, @@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[(( 0x0000001F, 0x00004100, }; +#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000060, + 0x00018060, + 0x06018060, + 0x00004000, + 0x0C0300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x00000000, + 0x00002000, + 0x00000000, + 0x00000000, + 0x06000000, + 0x00006018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x04000000, + 0x03000000, + 0x0000300C, + 0x00000000, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x0000300C, + 0x00C03000, + 0x00C00000, + 0x00000003, + 0x00000C03, + 0x00000200, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x0000300C, + 0x01000000, + 0x00000000, + 0x00000004, + 0x00000C03, + 0x00000200, + 0x00001806, + 0x00800000, + 0x00000000, + 0x00000002, + 0x00000800, + 0x00000100, + 0x00001000, + 0x00400000, + 0xC0300000, + 0x00000000, + 0x00000400, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x18060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000000, + 0x00010000, + 0x00002000, + 0x10038060, + 0x00000000, + 0x00000000, + 0x00000020, + 0x01806018, + 0x00001000, + 0x00010000, + 0x04000000, + 0x03000000, + 0x0000801C, + 0x00004000, + 0x00000800, + 0x01806018, + 0x02000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, + 0x00601806, + 0x80601800, + 0x80600001, + 0x80000601, + 0x00180601, + 0x00000100, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00481800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0xFFD602AF, + 0x86FFFFFF, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; +#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h index 490f109e4b..d1c9b0d36a 100644 --- a/board/altera/socfpga/iocsr_config.h +++ b/board/altera/socfpga/iocsr_config.h @@ -9,9 +9,18 @@ #ifndef _PRELOADER_IOCSR_CONFIG_H_ #define _PRELOADER_IOCSR_CONFIG_H_ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif #endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index 8b09005b60..61cdc73fa3 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -2,102 +2,103 @@ #include "pinmux_config.h" +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 /* pin mux configuration data */ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { - 0, /* EMACIO0 - Unused */ - 2, /* EMACIO1 - USB */ - 2, /* EMACIO2 - USB */ - 2, /* EMACIO3 - USB */ - 2, /* EMACIO4 - USB */ - 2, /* EMACIO5 - USB */ - 2, /* EMACIO6 - USB */ - 2, /* EMACIO7 - USB */ - 2, /* EMACIO8 - USB */ - 0, /* EMACIO9 - Unused */ - 2, /* EMACIO10 - USB */ - 2, /* EMACIO11 - USB */ - 2, /* EMACIO12 - USB */ - 2, /* EMACIO13 - USB */ - 0, /* EMACIO14 - N/A */ - 0, /* EMACIO15 - N/A */ - 0, /* EMACIO16 - N/A */ - 0, /* EMACIO17 - N/A */ - 0, /* EMACIO18 - N/A */ - 0, /* EMACIO19 - N/A */ - 3, /* FLASHIO0 - SDMMC */ - 3, /* FLASHIO1 - SDMMC */ - 3, /* FLASHIO2 - SDMMC */ - 3, /* FLASHIO3 - SDMMC */ - 0, /* FLASHIO4 - SDMMC */ - 0, /* FLASHIO5 - SDMMC */ - 0, /* FLASHIO6 - SDMMC */ - 0, /* FLASHIO7 - SDMMC */ - 0, /* FLASHIO8 - SDMMC */ - 3, /* FLASHIO9 - SDMMC */ - 3, /* FLASHIO10 - SDMMC */ - 3, /* FLASHIO11 - SDMMC */ - 3, /* GENERALIO0 - TRACE */ - 3, /* GENERALIO1 - TRACE */ - 3, /* GENERALIO2 - TRACE */ - 3, /* GENERALIO3 - TRACE */ - 3, /* GENERALIO4 - TRACE */ - 3, /* GENERALIO5 - TRACE */ - 3, /* GENERALIO6 - TRACE */ - 3, /* GENERALIO7 - TRACE */ - 3, /* GENERALIO8 - TRACE */ - 3, /* GENERALIO9 - SPIM0 */ - 3, /* GENERALIO10 - SPIM0 */ - 3, /* GENERALIO11 - SPIM0 */ - 3, /* GENERALIO12 - SPIM0 */ - 2, /* GENERALIO13 - CAN0 */ - 2, /* GENERALIO14 - CAN0 */ - 3, /* GENERALIO15 - I2C0 */ - 3, /* GENERALIO16 - I2C0 */ - 2, /* GENERALIO17 - UART0 */ - 2, /* GENERALIO18 - UART0 */ - 0, /* GENERALIO19 - N/A */ - 0, /* GENERALIO20 - N/A */ - 0, /* GENERALIO21 - N/A */ - 0, /* GENERALIO22 - N/A */ - 0, /* GENERALIO23 - N/A */ - 0, /* GENERALIO24 - N/A */ - 0, /* GENERALIO25 - N/A */ - 0, /* GENERALIO26 - N/A */ - 0, /* GENERALIO27 - N/A */ - 0, /* GENERALIO28 - N/A */ - 0, /* GENERALIO29 - N/A */ - 0, /* GENERALIO30 - N/A */ - 0, /* GENERALIO31 - N/A */ - 2, /* MIXED1IO0 - EMAC */ - 2, /* MIXED1IO1 - EMAC */ - 2, /* MIXED1IO2 - EMAC */ - 2, /* MIXED1IO3 - EMAC */ - 2, /* MIXED1IO4 - EMAC */ - 2, /* MIXED1IO5 - EMAC */ - 2, /* MIXED1IO6 - EMAC */ - 2, /* MIXED1IO7 - EMAC */ - 2, /* MIXED1IO8 - EMAC */ - 2, /* MIXED1IO9 - EMAC */ - 2, /* MIXED1IO10 - EMAC */ - 2, /* MIXED1IO11 - EMAC */ - 2, /* MIXED1IO12 - EMAC */ - 2, /* MIXED1IO13 - EMAC */ - 0, /* MIXED1IO14 - Unused */ - 3, /* MIXED1IO15 - QSPI */ - 3, /* MIXED1IO16 - QSPI */ - 3, /* MIXED1IO17 - QSPI */ - 3, /* MIXED1IO18 - QSPI */ - 3, /* MIXED1IO19 - QSPI */ - 3, /* MIXED1IO20 - QSPI */ - 0, /* MIXED1IO21 - GPIO */ - 0, /* MIXED2IO0 - N/A */ - 0, /* MIXED2IO1 - N/A */ - 0, /* MIXED2IO2 - N/A */ - 0, /* MIXED2IO3 - N/A */ - 0, /* MIXED2IO4 - N/A */ - 0, /* MIXED2IO5 - N/A */ - 0, /* MIXED2IO6 - N/A */ - 0, /* MIXED2IO7 - N/A */ + 3, /* EMACIO0 */ + 3, /* EMACIO1 */ + 3, /* EMACIO2 */ + 3, /* EMACIO3 */ + 3, /* EMACIO4 */ + 3, /* EMACIO5 */ + 3, /* EMACIO6 */ + 3, /* EMACIO7 */ + 3, /* EMACIO8 */ + 3, /* EMACIO9 */ + 3, /* EMACIO10 */ + 3, /* EMACIO11 */ + 3, /* EMACIO12 */ + 3, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 3, /* FLASHIO4 */ + 3, /* FLASHIO5 */ + 3, /* FLASHIO6 */ + 3, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 1, /* MIXED1IO1 */ + 1, /* MIXED1IO2 */ + 1, /* MIXED1IO3 */ + 1, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 1, /* MIXED1IO8 */ + 1, /* MIXED1IO9 */ + 1, /* MIXED1IO10 */ + 1, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 1, /* MIXED1IO15 */ + 1, /* MIXED1IO16 */ + 1, /* MIXED1IO17 */ + 1, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ 0, /* GPLINMUX48 */ 0, /* GPLINMUX49 */ 0, /* GPLINMUX50 */ @@ -212,3 +213,217 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ }; +#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 3, /* EMACIO14 */ + 3, /* EMACIO15 */ + 3, /* EMACIO16 */ + 3, /* EMACIO17 */ + 3, /* EMACIO18 */ + 3, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 3, /* GENERALIO23 */ + 3, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 0, /* MIXED1IO1 */ + 0, /* MIXED1IO2 */ + 0, /* MIXED1IO3 */ + 0, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 0, /* MIXED1IO8 */ + 0, /* MIXED1IO9 */ + 0, /* MIXED1IO10 */ + 0, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 3, /* MIXED2IO0 */ + 3, /* MIXED2IO1 */ + 3, /* MIXED2IO2 */ + 3, /* MIXED2IO3 */ + 3, /* MIXED2IO4 */ + 3, /* MIXED2IO5 */ + 3, /* MIXED2IO6 */ + 3, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h index f278f2b280..21fabb0b2b 100644 --- a/board/altera/socfpga/pinmux_config.h +++ b/board/altera/socfpga/pinmux_config.h @@ -7,21 +7,21 @@ * State of enabling for which IP connected out through the muxing. * Value 1 mean the IP connection is muxed out */ -#define CONFIG_HPS_EMAC0 (0) -#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_EMAC0 (1) +#define CONFIG_HPS_EMAC1 (0) #define CONFIG_HPS_USB0 (0) #define CONFIG_HPS_USB1 (1) #define CONFIG_HPS_NAND (0) #define CONFIG_HPS_SDMMC (1) -#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_QSPI (0) #define CONFIG_HPS_UART0 (1) #define CONFIG_HPS_UART1 (0) -#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_TRACE (0) #define CONFIG_HPS_I2C0 (1) #define CONFIG_HPS_I2C1 (0) #define CONFIG_HPS_I2C2 (0) #define CONFIG_HPS_I2C3 (0) -#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM0 (0) #define CONFIG_HPS_SPIM1 (0) #define CONFIG_HPS_SPIS0 (0) #define CONFIG_HPS_SPIS1 (0) @@ -29,10 +29,10 @@ #define CONFIG_HPS_CAN1 (0) /* IP attribute value (which affected by pin muxing configuration) */ -#define CONFIG_HPS_SDMMC_BUSWIDTH (4) +#define CONFIG_HPS_SDMMC_BUSWIDTH (8) /* 1 if the pins are connected out */ -#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS0 (0) #define CONFIG_HPS_QSPI_CS1 (0) #define CONFIG_HPS_QSPI_CS2 (0) #define CONFIG_HPS_QSPI_CS3 (0) diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index f0f59a9519..8130fa4744 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -16,9 +16,9 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) @@ -36,7 +36,7 @@ /* Peripheral PLL */ #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) /* * To tell where is the VCOs source: * 0 = EOSC1 @@ -45,13 +45,13 @@ */ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4) #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) @@ -66,15 +66,8 @@ #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) /* SDRAM PLL */ -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz - * This if..else... is not required if generated by tools */ #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) -#else -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) -#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) /* * To tell where is the VCOs source: @@ -94,17 +87,12 @@ /* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) -#else -#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) -#endif +#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) #define CONFIG_HPS_CLK_USBCLK_HZ (200000000) diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga.c index 459d82f351..20d221641b 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga.c @@ -19,23 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; /* - * Print Board information - */ -int checkboard(void) -{ - puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); - return 0; -} - -/* - * Initialization function which happen at early stage of c code - */ -int board_early_init_f(void) -{ - return 0; -} - -/* * Miscellaneous platform dependent initialisations */ int board_init(void) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 58973185ec..de6286435d 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -22,12 +22,6 @@ int board_init(void) int dram_init(void) { - /* - * Clear spin table so that secondary processors - * observe the correct value after waken up from wfe. - */ - *(unsigned long *)CPU_RELEASE_ADDR = 0; - gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } @@ -143,5 +137,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif return rc; } diff --git a/board/bc3450/Kconfig b/board/bc3450/Kconfig deleted file mode 100644 index a0fc19f63c..0000000000 --- a/board/bc3450/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_BC3450 - -config SYS_BOARD - default "bc3450" - -config SYS_CONFIG_NAME - default "BC3450" - -endif diff --git a/board/bc3450/MAINTAINERS b/board/bc3450/MAINTAINERS deleted file mode 100644 index 81a7076093..0000000000 --- a/board/bc3450/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BC3450 BOARD -#M: - -S: Maintained -F: board/bc3450/ -F: include/configs/BC3450.h -F: configs/BC3450_defconfig diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile deleted file mode 100644 index b8d22bafed..0000000000 --- a/board/bc3450/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := bc3450.o cmd_bc3450.o diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c deleted file mode 100644 index a5c6d750cb..0000000000 --- a/board/bc3450/bc3450.c +++ /dev/null @@ -1,586 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2006 - * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <netdev.h> - -#ifdef CONFIG_VIDEO_SM501 -#include <sm501.h> -#endif - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifdef CONFIG_RTC_MPC5200 -#include <rtc.h> -#endif - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ - - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -int checkboard (void) -{ -#if defined (CONFIG_TQM5200) - puts ("Board: TQM5200 (TQ-Components GmbH)\n"); -#endif - -#if defined (CONFIG_BC3450) - puts ("Dev: GERSYS BC3450\n"); -#endif - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#ifdef CONFIG_POST -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ - struct mpc5xxx_gpio *gpio; - - gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; - - /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. - */ - gpio->port_config &= ~(0x07000000); - gpio->port_config |= 0x03000000; - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - gpio->simple_gpioe |= 0x20000000; - - /* Configure GPIO_IRDA_1 as input */ - gpio->simple_ddr &= ~(0x20000000); - - return ((gpio->simple_ival & 0x20000000) ? 0 : 1); -} -#endif - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_RTC_MPC5200 - struct rtc_time t; - - /* set to Wed Dec 31 19:00:00 1969 */ - t.tm_sec = t.tm_min = 0; - t.tm_hour = 19; - t.tm_mday = 31; - t.tm_mon = 12; - t.tm_year = 1969; - t.tm_wday = 3; - - rtc_set(&t); -#endif /* CONFIG_RTC_MPC5200 */ - -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - - -int last_stage_init (void) -{ - /* - * auto scan for really existing devices and re-set chip select - * configuration. - */ - u16 save, tmp; - int restore; - - /* - * Check for SRAM and SRAM size - */ - - /* save original SRAM content */ - save = *(volatile u16 *)CONFIG_SYS_CS2_START; - restore = 1; - - /* write test pattern to SRAM */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in SRAM detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { - /* no SRAM at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); - *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { - /* make sure that we access a mirrored address */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; - __asm__ volatile ("sync"); - if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { - /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, - 0x80000); - __asm__ volatile ("sync"); - puts ("SRAM: 512 kB\n"); - } - else - puts ("!! possible error in SRAM detection\n"); - } else { - puts ("SRAM: 1 MB\n"); - } - /* restore origianl SRAM content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS2_START = save; - __asm__ volatile ("sync"); - } - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); - *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else { - puts ("VGA: SMI501 (Voyager) with 8 MB\n"); - } - /* restore origianl FB content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - - return 0; -} - -#ifdef CONFIG_VIDEO_SM501 - -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#error CONFIG_VIDEO_SM501_16BPP not supported. -#endif /* CONFIG_VIDEO_SM501_16BPP */ - -#ifdef CONFIG_VIDEO_SM501_32BPP -static const SMI_REGS init_regs [] = -{ -#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT) - /* FP only */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x01013106}, - {0x80004, 0xc428bb17}, - {0x80000, 0x03013106}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a028b}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00010200}, - {0x80000, 0x0f013106}, -#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP) - /* CRT only */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x10090a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x10090a01}, - {0x00054, 0x0}, - {0x80200, 0x00010000}, - {0x80204, 0x0}, - {0x80208, 0x0A000A00}, - {0x8020C, 0x02fa027f}, - {0x80210, 0x004a028b}, - {0x80214, 0x020c01df}, - {0x80218, 0x000201e9}, - {0x80200, 0x00013306}, -#else /* panel + CRT */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a028b}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00010000}, -#endif - {0, 0} -}; -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { -#if defined (CONFIG_TQM5200) - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#else -#error No supported board selected -#endif /* CONFIG_TQM5200 */ - -#if defined (CONFIG_BC3450) - } else if (line_number == 2) { - strcpy (info, " Dev: GERSYS BC3450"); -#endif /* CONFIG_BC3450 */ - } - else { - info [0] = '\0'; - } -} -#endif - -/* - * Returns SM501 register base address. First thing called in the - * driver. Checks if SM501 is physically present. - */ -unsigned int board_video_init (void) -{ - u16 save, tmp; - int restore, ret; - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller found */ - restore = 0; - ret = 0; - } else { - ret = SM501_MMIO_BASE; - } - - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - return ret; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - return SM501_FB_BASE; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SM501 */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c deleted file mode 100644 index 3c6e798ac3..0000000000 --- a/board/bc3450/cmd_bc3450.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de - * - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> - -/* - * BC3450 specific commands - */ -#if defined(CONFIG_CMD_BSP) - -/* - * Definitions for DS1620 chip - */ -#define THERM_START_CONVERT 0xee -#define THERM_RESET 0xaf -#define THERM_READ_CONFIG 0xac -#define THERM_READ_TEMP 0xaa -#define THERM_READ_TL 0xa2 -#define THERM_READ_TH 0xa1 -#define THERM_WRITE_CONFIG 0x0c -#define THERM_WRITE_TL 0x02 -#define THERM_WRITE_TH 0x01 - -#define CONFIG_SYS_1SHOT 1 -#define CONFIG_SYS_STANDALONE 0 - -struct therm { - int hi; - int lo; -}; - -/* - * SM501 Register - */ -#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */ -#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */ -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_LOW 0x00010000UL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL -#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL - -/* SM501 CRT Display Control Bits */ -#define SM501_CDC_SEL (1 << 9) -#define SM501_CDC_TE (1 << 8) -#define SM501_CDC_E (1 << 2) - -/* SM501 Panel Display Control Bits */ -#define SM501_PDC_FPEN (1 << 27) -#define SM501_PDC_BIAS (1 << 26) -#define SM501_PDC_DATA (1 << 25) -#define SM501_PDC_VDDEN (1 << 24) - -/* SM501 GPIO Data LOW Bits */ -#define SM501_GPIO24 0x01000000 -#define SM501_GPIO25 0x02000000 -#define SM501_GPIO26 0x04000000 -#define SM501_GPIO27 0x08000000 -#define SM501_GPIO28 0x10000000 -#define SM501_GPIO29 0x20000000 -#define SM501_GPIO30 0x40000000 -#define SM501_GPIO31 0x80000000 - -/* SM501 GPIO Data HIGH Bits */ -#define SM501_GPIO46 0x00004000 -#define SM501_GPIO47 0x00008000 -#define SM501_GPIO48 0x00010000 -#define SM501_GPIO49 0x00020000 -#define SM501_GPIO50 0x00040000 -#define SM501_GPIO51 0x00080000 - -/* BC3450 GPIOs @ SM501 Data LOW */ -#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27) -#define DS1620_DQ SM501_GPIO29 /* I/O */ -#define DS1620_CLK SM501_GPIO30 /* High active O/P */ -#define DS1620_RES SM501_GPIO31 /* Low active O/P */ -/* BC3450 GPIOs @ SM501 Data HIGH */ -#define BUZZER SM501_GPIO47 /* Low active O/P */ -#define DS1620_TLOW SM501_GPIO48 /* High active I/P */ -#define PWR_OFF SM501_GPIO49 /* Low active O/P */ -#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */ - - -/* - * Initialise GPIO on SM501 - * - * This function may be called from several other functions. - * Yet, the initialisation sequence is executed only the first - * time the function is called. - */ -int sm501_gpio_init (void) -{ - static int init_done = 0; - - if (init_done) { - debug("sm501_gpio_init: nothing to be done.\n"); - return 1; - } - - /* enable SM501 GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - - /* set up default O/Ps */ - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= - ~(DS1620_RES | DS1620_CLK); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ; - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= - ~(FP_DATA_TRI); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= - (BUZZER | PWR_OFF); - - /* configure directions for SM501 GPIO pins */ - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= - ~(0x3F << 14); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= - ~(DIP | DS1620_DQ); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= - (DS1620_RES | DS1620_CLK); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= - ~DS1620_TLOW; - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= - (PWR_OFF | BUZZER | FP_DATA_TRI); - - init_done = 1; - debug("sm501_gpio_init: done.\n"); - - return 0; -} - - -/* - * dip - read Config Inputs - * - * read and prints the dip switch - * and/or external config inputs (4bits) 0...0x0F - */ -int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - vu_long rc = 0; - - sm501_gpio_init (); - - /* read dip switch */ - rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); - rc = ~rc; - rc &= DIP; - rc = (int) (rc >> 24); - - /* plausibility check */ - if (rc > 0x0F) - return -1; - - printf ("0x%lx\n", rc); - return 0; -} - -U_BOOT_CMD (dip, 1, 1, cmd_dip, - "read dip switch and config inputs", - "\n" - " - prints the state of the dip switch and/or\n" - " external configuration inputs as hex value.\n" - " - \"Config 1\" is the LSB"); - - -/* - * buz - turns Buzzer on/off - */ -#ifdef CONFIG_BC3450_BUZZER -static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 2) { - printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); - return 1; - } - - sm501_gpio_init (); - - if (strncmp (argv[1], "on", 2) == 0) { - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= - ~(BUZZER); - return 0; - } else if (strncmp (argv[1], "off", 3) == 0) { - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= - BUZZER; - return 0; - } - printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n"); - return 1; -} - -U_BOOT_CMD (buz, 2, 1, cmd_buz, - "turns buzzer on/off", - "\n" "buz <on/off>\n" " - turns the buzzer on or off"); -#endif /* CONFIG_BC3450_BUZZER */ - - -/* - * fp - front panel commands - */ -static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - sm501_gpio_init (); - - if (strncmp (argv[1], "on", 2) == 0) { - /* turn on VDD first */ - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN; - udelay (1000); - /* then put data on */ - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA; - /* wait some time and enable backlight */ - udelay (1000); - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS; - udelay (1000); - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN; - return 0; - } else if (strncmp (argv[1], "off", 3) == 0) { - /* turn off the backlight first */ - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN; - udelay (1000); - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS; - udelay (200000); - /* wait some time, then remove data */ - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA; - udelay (1000); - /* and remove VDD last */ - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= - ~SM501_PDC_VDDEN; - return 0; - } else if (strncmp (argv[1], "bl", 2) == 0) { - /* turn on/off backlight only */ - if (strncmp (argv[2], "on", 2) == 0) { - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= - SM501_PDC_BIAS; - udelay (1000); - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) |= - SM501_PDC_FPEN; - return 0; - } else if (strncmp (argv[2], "off", 3) == 0) { - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= - ~SM501_PDC_FPEN; - udelay (1000); - *(vu_long *) (SM501_MMIO_BASE + - SM501_PANEL_DISPLAY_CONTROL) &= - ~SM501_PDC_BIAS; - return 0; - } - } -#ifdef CONFIG_BC3450_CRT - else if (strncmp (argv[1], "crt", 3) == 0) { - /* enables/disables the crt output (debug only) */ - if (strncmp (argv[2], "on", 2) == 0) { - *(vu_long *) (SM501_MMIO_BASE + - SM501_CRT_DISPLAY_CONTROL) |= - (SM501_CDC_TE | SM501_CDC_E); - *(vu_long *) (SM501_MMIO_BASE + - SM501_CRT_DISPLAY_CONTROL) &= - ~SM501_CDC_SEL; - return 0; - } else if (strncmp (argv[2], "off", 3) == 0) { - *(vu_long *) (SM501_MMIO_BASE + - SM501_CRT_DISPLAY_CONTROL) &= - ~(SM501_CDC_TE | SM501_CDC_E); - *(vu_long *) (SM501_MMIO_BASE + - SM501_CRT_DISPLAY_CONTROL) |= - SM501_CDC_SEL; - return 0; - } - } -#endif /* CONFIG_BC3450_CRT */ - printf ("Usage:%s\n", cmdtp->help); - return 1; -} - -U_BOOT_CMD (fp, 3, 1, cmd_fp, - "front panes access functions", - "\n" - "fp bl <on/off>\n" - " - turns the CCFL backlight of the display on/off\n" - "fp <on/off>\n" " - turns the whole display on/off" -#ifdef CONFIG_BC3450_CRT - "\n" - "fp crt <on/off>\n" - " - enables/disables the crt output (debug only)" -#endif /* CONFIG_BC3450_CRT */ - ); - -/* - * temp - DS1620 thermometer - */ -/* GERSYS BC3450 specific functions */ -static inline void bc_ds1620_set_clk (int clk) -{ - if (clk) - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= - DS1620_CLK; - else - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= - ~DS1620_CLK; -} - -static inline void bc_ds1620_set_data (int dat) -{ - if (dat) - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= - DS1620_DQ; - else - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= - ~DS1620_DQ; -} - -static inline int bc_ds1620_get_data (void) -{ - vu_long rc; - - rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW); - rc &= DS1620_DQ; - if (rc != 0) - rc = 1; - return (int) rc; -} - -static inline void bc_ds1620_set_data_dir (int dir) -{ - if (dir) /* in */ - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ; - else /* out */ - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ; -} - -static inline void bc_ds1620_set_reset (int res) -{ - if (res) - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES; - else - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES; -} - -/* hardware independent functions */ -static void ds1620_send_bits (int nr, int value) -{ - int i; - - for (i = 0; i < nr; i++) { - bc_ds1620_set_data (value & 1); - bc_ds1620_set_clk (0); - udelay (1); - bc_ds1620_set_clk (1); - udelay (1); - - value >>= 1; - } -} - -static unsigned int ds1620_recv_bits (int nr) -{ - unsigned int value = 0, mask = 1; - int i; - - bc_ds1620_set_data (0); - - for (i = 0; i < nr; i++) { - bc_ds1620_set_clk (0); - udelay (1); - - if (bc_ds1620_get_data ()) - value |= mask; - - mask <<= 1; - - bc_ds1620_set_clk (1); - udelay (1); - } - - return value; -} - -static void ds1620_out (int cmd, int bits, int value) -{ - bc_ds1620_set_clk (1); - bc_ds1620_set_data_dir (0); - - bc_ds1620_set_reset (0); - udelay (1); - bc_ds1620_set_reset (1); - - udelay (1); - - ds1620_send_bits (8, cmd); - if (bits) - ds1620_send_bits (bits, value); - - udelay (1); - - /* go stand alone */ - bc_ds1620_set_data_dir (1); - bc_ds1620_set_reset (0); - bc_ds1620_set_clk (0); - - udelay (10000); -} - -static unsigned int ds1620_in (int cmd, int bits) -{ - unsigned int value; - - bc_ds1620_set_clk (1); - bc_ds1620_set_data_dir (0); - - bc_ds1620_set_reset (0); - udelay (1); - bc_ds1620_set_reset (1); - - udelay (1); - - ds1620_send_bits (8, cmd); - - bc_ds1620_set_data_dir (1); - value = ds1620_recv_bits (bits); - - /* go stand alone */ - bc_ds1620_set_data_dir (1); - bc_ds1620_set_reset (0); - bc_ds1620_set_clk (0); - - return value; -} - -static int cvt_9_to_int (unsigned int val) -{ - if (val & 0x100) - val |= 0xfffffe00; - - return val; -} - -/* set thermostate thresholds */ -static void ds1620_write_state (struct therm *therm) -{ - ds1620_out (THERM_WRITE_TL, 9, therm->lo); - ds1620_out (THERM_WRITE_TH, 9, therm->hi); - ds1620_out (THERM_START_CONVERT, 0, 0); -} - -static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - struct therm therm; - - sm501_gpio_init (); - - /* print temperature */ - if (argc == 1) { - i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9)); - printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0); - return 0; - } - - /* set to default operation */ - if (strncmp (argv[1], "set", 3) == 0) { - if (strncmp (argv[2], "default", 3) == 0) { - therm.hi = +88; - therm.lo = -20; - therm.hi <<= 1; - therm.lo <<= 1; - ds1620_write_state (&therm); - ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE); - return 0; - } - } - - printf ("Usage:%s\n", cmdtp->help); - return 1; -} - -U_BOOT_CMD (temp, 3, 1, cmd_temp, - "print current temperature", - "\n" "temp\n" " - print current temperature"); - -#ifdef CONFIG_BC3450_CAN -/* - * Initialise CAN interface - * - * return 1 on CAN initialization failure - * return 0 if no failure - */ -int can_init (void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980); - - /* GPIO configuration of the CAN pins is done in BC3450.h */ - - if (!init_done) { - /* init CAN 1 */ - can1->canctl1 |= 0x80; /* CAN enable */ - udelay (100); - - i = 0; - can1->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can1->canctl1 & 0x02)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can1->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can1->canctl1 & 0x01)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can1->canctl1 = 0x80; - can1->canctl1 |= 0x40; - can1->canbtr0 = 0x0F; - can1->canbtr1 = 0x7F; - can1->canidac &= ~(0x30); - can1->canidar1 = 0x00; - can1->canidar3 = 0x00; - can1->canidar5 = 0x00; - can1->canidar7 = 0x00; - can1->canidmr0 = 0xFF; - can1->canidmr1 = 0xFF; - can1->canidmr2 = 0xFF; - can1->canidmr3 = 0xFF; - can1->canidmr4 = 0xFF; - can1->canidmr5 = 0xFF; - can1->canidmr6 = 0xFF; - can1->canidmr7 = 0xFF; - - i = 0; - can1->canctl0 &= ~(0x01); /* leave init mode */ - can1->canctl0 &= ~(0x02); - /* wait until init and sleep mode left */ - while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - - /* init CAN 2 */ - can2->canctl1 |= 0x80; /* CAN enable */ - udelay (100); - - i = 0; - can2->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can2->canctl1 & 0x02)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can2->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can2->canctl1 & 0x01)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can2->canctl1 = 0x80; - can2->canctl1 |= 0x40; - can2->canbtr0 = 0x0F; - can2->canbtr1 = 0x7F; - can2->canidac &= ~(0x30); - can2->canidar1 = 0x00; - can2->canidar3 = 0x00; - can2->canidar5 = 0x00; - can2->canidar7 = 0x00; - can2->canidmr0 = 0xFF; - can2->canidmr1 = 0xFF; - can2->canidmr2 = 0xFF; - can2->canidmr3 = 0xFF; - can2->canidmr4 = 0xFF; - can2->canidmr5 = 0xFF; - can2->canidmr6 = 0xFF; - can2->canidmr7 = 0xFF; - can2->canctl0 &= ~(0x01); /* leave init mode */ - can2->canctl0 &= ~(0x02); - - i = 0; - /* wait until init mode left */ - while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { - udelay (10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - init_done = 1; - } - return 0; -} - -/* - * Do CAN test - * by sending message between CAN1 and CAN2 - * - * return 1 on CAN failure - * return 0 if no failure - */ -int do_can (char * const argv[]) -{ - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980); - - /* send a message on CAN1 */ - can1->cantbsel = 0x01; - can1->cantxfg.idr[0] = 0x55; - can1->cantxfg.idr[1] = 0x00; - can1->cantxfg.idr[1] &= ~0x8; - can1->cantxfg.idr[1] &= ~0x10; - can1->cantxfg.dsr[0] = 0xCC; - can1->cantxfg.dlr = 1; - can1->cantxfg.tbpr = 0; - can1->cantflg = 0x01; - - i = 0; - while ((can1->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN1 send timeout, " - "can not send message!\n", __FUNCTION__); - return 1; - } - udelay (1000); - } - udelay (1000); - - i = 0; - while (!(can2->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN2 receive timeout, " - "no message received!\n", __FUNCTION__); - return 1; - } - udelay (1000); - } - - if (can2->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN2 receive error, " - "data mismatch!\n", __FUNCTION__); - return 1; - } - - /* send a message on CAN2 */ - can2->cantbsel = 0x01; - can2->cantxfg.idr[0] = 0x55; - can2->cantxfg.idr[1] = 0x00; - can2->cantxfg.idr[1] &= ~0x8; - can2->cantxfg.idr[1] &= ~0x10; - can2->cantxfg.dsr[0] = 0xCC; - can2->cantxfg.dlr = 1; - can2->cantxfg.tbpr = 0; - can2->cantflg = 0x01; - - i = 0; - while ((can2->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN2 send error, " - "can not send message!\n", __FUNCTION__); - return 1; - } - udelay (1000); - } - udelay (1000); - - i = 0; - while (!(can1->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN1 receive timeout, " - "no message received!\n", __FUNCTION__); - return 1; - } - udelay (1000); - } - - if (can1->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN1 receive error 0x%02x\n", - __FUNCTION__, (can1->canrxfg.dsr[0])); - return 1; - } - - return 0; -} -#endif /* CONFIG_BC3450_CAN */ - -/* - * test - BC3450 HW test routines - */ -int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ -#ifdef CONFIG_BC3450_CAN - int rcode; - - can_init (); -#endif /* CONFIG_BC3450_CAN */ - - sm501_gpio_init (); - - if (argc != 2) { - printf ("Usage:%s\n", cmdtp->help); - return 1; - } - - if (strncmp (argv[1], "unit-off", 8) == 0) { - printf ("waiting 2 seconds...\n"); - udelay (2000000); - *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= - ~PWR_OFF; - return 0; - } -#ifdef CONFIG_BC3450_CAN - else if (strncmp (argv[1], "can", 2) == 0) { - rcode = do_can (argv); - if (simple_strtoul (argv[2], NULL, 10) == 2) { - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - } - return rcode; - } -#endif /* CONFIG_BC3450_CAN */ - - printf ("Usage:%s\n", cmdtp->help); - return 1; -} - -U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n" -#ifdef CONFIG_BC3450_CAN - "test can\n" - " - connect CAN1 (X8) with CAN2 (X9) for this test\n" -#endif /* CONFIG_BC3450_CAN */ - "test unit-off\n" - " - turns off the BC3450 unit\n" - " WARNING: Unsaved environment variables will be lost!" -); -#endif diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h deleted file mode 100644 index 3d9979664f..0000000000 --- a/board/bc3450/mt48lc16m16a2-75.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig new file mode 100644 index 0000000000..3380ed39b2 --- /dev/null +++ b/board/birdland/bav335x/Kconfig @@ -0,0 +1,33 @@ +if TARGET_BAV335X + +config SYS_BOARD + default "bav335x" + +config SYS_VENDOR + default "birdland" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "bav335x" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0 as for example the IDK + uses UART3 so enter 4 here. + +config BAV_VERSION + int "BAV335x Version (1=A, 2=B)" + range 1 2 + help + The BAV335x has various version of the board. Rev.A (mostly obsolete) + used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY. + Overwrite this if you have an older Rev.A and want ethernet support. + +endif diff --git a/board/birdland/bav335x/MAINTAINERS b/board/birdland/bav335x/MAINTAINERS new file mode 100644 index 0000000000..45dcfcb1e6 --- /dev/null +++ b/board/birdland/bav335x/MAINTAINERS @@ -0,0 +1,13 @@ +BAV335x BOARD +M: Gilles Gameiro <gilles@gigadevices.com> +S: Maintained +F: include/configs/bav335x.h +F: board/birdland/bav335x/Kconfig +F: board/birdland/bav335x/Makefile +F: board/birdland/bav335x/README +F: board/birdland/bav335x/board.c +F: board/birdland/bav335x/board.h +F: board/birdland/bav335x/mux.c +F: board/birdland/bav335x/u-boot.lds +F: configs/birdland_bav335a_defconfig +F: configs/birdland_bav335b_defconfig diff --git a/board/birdland/bav335x/Makefile b/board/birdland/bav335x/Makefile new file mode 100644 index 0000000000..2fc56143c3 --- /dev/null +++ b/board/birdland/bav335x/Makefile @@ -0,0 +1,11 @@ +# +# Makefile +# +# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/birdland/bav335x/README b/board/birdland/bav335x/README new file mode 100644 index 0000000000..08c73eee0c --- /dev/null +++ b/board/birdland/bav335x/README @@ -0,0 +1,31 @@ +Summary +======= + +This document covers various features of the 'BAV335x' board build. +For more information about this board, visit http://birdland.com/oem + + +Hardware +======== + +The binary produced supports the bav335x Rev.A with 10/100 MB PHY +and Rev.B (default) with GB ethernet PHY. +If the BAV335x EEPROM is populated and programmed, the board will +automatically detect the version and extract proper serial# and +mac address from the EE. + + +Customization +============= + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c new file mode 100644 index 0000000000..d1e1c8cbd3 --- /dev/null +++ b/board/birdland/bav335x/board.c @@ -0,0 +1,430 @@ +/* + * board.c + * + * Board functions for Birdland Audio BAV335x Network Processor + * + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include <environment.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 + +static __maybe_unused struct ctrl_dev *cdev = + (struct ctrl_dev *)CTRL_DEVICE_BASE; + + + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct board_eeconfig *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) + return -ENODEV; + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct board_eeconfig))) + return -EIO; + + if (header->magic != BOARD_MAGIC) { + /* read the i2c eeprom again using only a 1 byte address */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct board_eeconfig))) + return -EIO; + + if (header->magic != BOARD_MAGIC) + return -EINVAL; + } + return 0; +} + + + + +enum board_type get_board_type(bool debug) +{ + int ecode; + struct board_eeconfig header; + + ecode = read_eeprom(&header); + if (ecode == 0) { + if (header.version[1] == 'A') { + if (debug) + puts("=== Detected Board model BAV335x Rev.A"); + return BAV335A; + } else if (header.version[1] == 'B') { + if (debug) + puts("=== Detected Board model BAV335x Rev.B"); + return BAV335B; + } else if (debug) { + puts("### Un-known board model in serial-EE\n"); + } + } else if (debug) { + switch (ecode) { + case -ENODEV: + puts("### Board doesn't have a serial-EE\n"); + break; + case -EINVAL: + puts("### Board serial-EE signature is incorrect.\n"); + break; + default: + puts("### IO Error reading serial-EE.\n"); + break; + } + } + +#if (CONFIG_BAV_VERSION == 1) + if (debug) + puts("### Selecting BAV335A as per config\n"); + return BAV335A; +#elif (CONFIG_BAV_VERSION == 2) + if (debug) + puts("### Selecting BAV335B as per config\n"); + return BAV335B; +#endif +#if (NOT_DEFINED == 2) +#error "SHOULD NEVER DISPLAY THIS" +#endif + + if (debug) + puts("### Defaulting to model BAV335x Rev.B\n"); + return BAV335B; +} + + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +static const struct ddr_data ddr3_bav335x_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + + +static struct emif_regs ddr3_bav335x_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* debug print detect status */ + (void)get_board_type(true); + + /* Get the frequency */ + /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */ + dpll_mpu_opp100.m = MPUPLL_M_1000; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* Set the USB Current Limit */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + TPS65217_USB_INPUT_CUR_LIMIT_1800MA, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("! tps65217_reg_write: could not set USB limit\n"); + + /* Set the Core Voltage (DCDC3) to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("! tps65217_reg_write: could not set Core Voltage\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set the MPU Voltage (DCDC2) */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, + TPS65217_DCDC_VOLT_SEL_1325MV)) { + puts("! tps65217_reg_write: could not set MPU Voltage\n"); + return; + } + + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) + puts("! tps65217_reg_write: could not set LDO3\n"); + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) + puts("! tps65217_reg_write: could not set LDO4\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr_bone_black; +} + +void set_uart_mux_conf(void) +{ +#if CONFIG_CONS_INDEX == 1 + enable_uart0_pin_mux(); +#elif CONFIG_CONS_INDEX == 2 + enable_uart1_pin_mux(); +#elif CONFIG_CONS_INDEX == 3 + enable_uart2_pin_mux(); +#elif CONFIG_CONS_INDEX == 4 + enable_uart3_pin_mux(); +#elif CONFIG_CONS_INDEX == 5 + enable_uart4_pin_mux(); +#elif CONFIG_CONS_INDEX == 6 + enable_uart5_pin_mux(); +#endif +} + +void set_mux_conf_regs(void) +{ + enum board_type board; + + board = get_board_type(false); + enable_board_pin_mux(board); +} + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + + +void sdram_init(void) +{ + config_ddr(400, &ioregs_bonelt, + &ddr3_bav335x_data, + &ddr3_bav335x_cmd_ctrl_data, + &ddr3_bav335x_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "BAV335xB"); + setenv("board_rev", "B"); /* Fix me, but why bother.. */ +#endif + return 0; +} +#endif + + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + + +/* + * This function will: + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int ecode, rv, n; + uint8_t mac_addr[6]; + struct board_eeconfig header; + __maybe_unused enum board_type board; + + /* Default manufacturing address; used when no EE or invalid */ + n = 0; + mac_addr[0] = 0; + mac_addr[1] = 0x20; + mac_addr[2] = 0x18; + mac_addr[3] = 0x1C; + mac_addr[4] = 0x00; + mac_addr[5] = 0x01; + + ecode = read_eeprom(&header); + /* if we have a valid EE, get mac address from there */ + if ((ecode == 0) && + is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) { + memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6); + } + + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + + board = get_board_type(false); + + /* Rev.A uses 10/100 PHY in mii mode */ + if (board == BAV335A) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } + /* Rev.B (default) uses GB PHY in rmii mode */ + else { + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if + = PHY_INTERFACE_MODE_RGMII; + } + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + +#endif + + return n; +} +#endif diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h new file mode 100644 index 0000000000..b598ce1e82 --- /dev/null +++ b/board/birdland/bav335x/board.h @@ -0,0 +1,59 @@ +/* + * board.c + * + * Board functions for Birdland Audio BAV335x Network Processor + * + * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Serial MagicE: AA 55 BA BE */ +#define BOARD_MAGIC 0xBEBA55AA +enum board_type {UNKNOWN, BAV335A, BAV335B}; + + +/* + * The BAV335x may use a built-in read-only serial EEProm. + * The Evaluation board, disables the write-protect so the Serial-EE + * Can be programmed during manufacturing to store fields such as + * a board serial number, ethernet mac address and other user fields. + * Additionally, the Serial-EE can store the specific version of the + * board it runs on, and overwrite the defaults in _defconfig + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct board_eeconfig { + unsigned int magic; + char name[HDR_NAME_LEN]; /* BAV3354 */ + char version[4]; /* 0B20 - Rev.B2 */ + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +enum board_type get_board_type(bool verbose_debug_output); + + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(enum board_type board); + +#endif diff --git a/board/birdland/bav335x/mux.c b/board/birdland/bav335x/mux.c new file mode 100644 index 0000000000..f18bfa4f60 --- /dev/null +++ b/board/birdland/bav335x/mux.c @@ -0,0 +1,190 @@ +/* + * mux.c + * + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + + +/* CPLD registers */ +#define I2C_CPLD_ADDR 0x35 +#define CFG_REG 0x10 + + +void enable_board_pin_mux(enum board_type board) +{ + configure_module_pin_mux(i2c1_pin_mux); + if (board == BAV335A) + configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */ + else + configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */ + + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); +} diff --git a/board/birdland/bav335x/u-boot.lds b/board/birdland/bav335x/u-boot.lds new file mode 100644 index 0000000000..fc80f215e3 --- /dev/null +++ b/board/birdland/bav335x/u-boot.lds @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/birdland/bav335x/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 14af660087..7181cac291 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -72,4 +72,10 @@ obj-$(CONFIG_P5020DS) += p_corenet/ obj-$(CONFIG_P5040DS) += p_corenet/ obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o + +ifdef CONFIG_SECURE_BOOT +obj-y += fsl_validate.o +obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o +endif + endif diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c new file mode 100644 index 0000000000..8500ba5838 --- /dev/null +++ b/board/freescale/common/cmd_esbc_validate.c @@ -0,0 +1,34 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <fsl_validate.h> + +static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2) + return cmd_usage(cmdtp); + + return fsl_secboot_validate(cmdtp, flag, argc, argv); +} + +/***************************************************/ +static char esbc_validate_help_text[] = + "esbc_validate hdr_addr <hash_val> - Validates signature using\n" + " RSA verification\n" + " $hdr_addr Address of header of the image\n" + " to be validated.\n" + " $hash_val -Optional\n" + " It provides Hash of public/srk key to be\n" + " used to verify signature.\n"; + +U_BOOT_CMD( + esbc_validate, 3, 0, do_esbc_validate, + "Validates signature on a given image using RSA verification", + esbc_validate_help_text +); diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c new file mode 100644 index 0000000000..5283648a4d --- /dev/null +++ b/board/freescale/common/fsl_validate.c @@ -0,0 +1,840 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_validate.h> +#include <fsl_secboot_err.h> +#include <fsl_sfp.h> +#include <fsl_sec.h> +#include <command.h> +#include <malloc.h> +#include <dm/uclass.h> +#include <u-boot/rsa-mod-exp.h> +#include <hash.h> +#include <fsl_secboot_err.h> +#ifndef CONFIG_MPC85xx +#include <asm/arch/immap_ls102xa.h> +#endif + +#define SHA256_BITS 256 +#define SHA256_BYTES (256/8) +#define SHA256_NIBBLES (256/4) +#define NUM_HEX_CHARS (sizeof(ulong) * 2) + +/* This array contains DER value for SHA-256 */ +static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, + 0x04, 0x20 + }; + +static u8 hash_val[SHA256_BYTES]; +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; + +void branch_to_self(void) __attribute__ ((noreturn)); + +/* + * This function will put core in infinite loop. + * This will be called when the ESBC can not proceed further due + * to some unknown errors. + */ +void branch_to_self(void) +{ + printf("Core is in infinite loop due to errors.\n"); +self: + goto self; +} + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 check_ie(struct fsl_secboot_img_priv *img) +{ + if (img->hdr.ie_flag) + return 1; + + return 0; +} + +/* This function returns the CSF Header Address of uboot + * For MPC85xx based platforms, the LAW mapping for NOR + * flash changes in uboot code. Hence the offset needs + * to be calculated and added to the new NOR flash base + * address + */ +#if defined(CONFIG_MPC85xx) +int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); + ulong flash_addr, addr; + int found = 0; + int i = 0; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_addr = flash_info[i].start[0]; + addr = flash_info[i].start[0] + csf_flash_offset; + if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { + debug("Barker found on addr %lx\n", addr); + found = 1; + break; + } + } + + if (!found) + return -1; + + *csf_addr = addr; + *flash_base_addr = flash_addr; + + return 0; +} +#else +/* For platforms like LS1020, correct flash address is present in + * the header. So the function reqturns flash base address as 0 + */ +int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + + if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN)) + return -1; + + *csf_addr = csf_hdr_addr; + *flash_base_addr = 0; + return 0; +} +#endif + +static int get_ie_info_addr(ulong *ie_addr) +{ + struct fsl_secboot_img_hdr *hdr; + struct fsl_secboot_sg_table *sg_tbl; + ulong flash_base_addr, csf_addr; + + if (get_csf_base_addr(&csf_addr, &flash_base_addr)) + return -1; + + hdr = (struct fsl_secboot_img_hdr *)csf_addr; + + /* For SoC's with Trust Architecture v1 with corenet bus + * the sg table field in CSF header has absolute address + * for sg table in memory. In other Trust Architecture, + * this field specifies the offset of sg table from the + * base address of CSF Header + */ +#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) + sg_tbl = (struct fsl_secboot_sg_table *) + (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); +#else + sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + + (ulong)hdr->psgtable); +#endif + + /* IE Key Table is the first entry in the SG Table */ +#if defined(CONFIG_MPC85xx) + *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr; +#else + *ie_addr = sg_tbl->src_addr; +#endif + + debug("IE Table address is %lx\n", *ie_addr); + return 0; +} + +#endif + +#ifdef CONFIG_KEY_REVOCATION +/* This function checks srk_table_flag in header and set/reset srk_flag.*/ +static u32 check_srk(struct fsl_secboot_img_priv *img) +{ + if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) + return 1; + + return 0; +} + +/* This function returns ospr's key_revoc values.*/ +static u32 get_key_revoc(void) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> + OSPR_KEY_REVOC_SHIFT; +} + +/* This function checks if selected key is revoked or not.*/ +static u32 is_key_revoked(u32 keynum, u32 rev_flag) +{ + if (keynum == UNREVOCABLE_KEY) + return 0; + + if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag) + return 1; + + return 0; +} + +/* It validates srk_table key lengths.*/ +static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries) +{ + int i = 0; + for (i = 0; i < num_entries; i++) { + if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) || + (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) || + (tbl[i].key_len == 2 * KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; + } + return 0; +} +#endif + +/* This function return length of public key.*/ +static inline u32 get_key_len(struct fsl_secboot_img_priv *img) +{ + return img->key_len; +} + +/* + * Handles the ESBC uboot client header verification failure. + * This function handles all the errors which might occur in the + * parsing and checking of ESBC uboot client header. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_header_verification_failure(void) +{ + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + + /* 29th bit of OSPR is ITS */ + u32 its = sfp_in32(&sfp_regs->ospr) >> 2; + + /* + * Read the SEC_MON status register + * Read SSM_ST field + */ + sts = sec_mon_in32(&sec_mon_regs->hp_stat); + if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { + if (its == 1) + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_SOFT_FAIL); + else + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_NON_SECURE); + } + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); +} + +/* + * Handles the ESBC uboot client image verification failure. + * This function handles all the errors which might occur in the + * public key hash comparison and signature verification of + * ESBC uboot client image. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_image_verification_failure(void) +{ + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + + u32 its = sfp_in32(&sfp_regs->ospr) & ITS_MASK >> ITS_BIT; + + /* + * Read the SEC_MON status register + * Read SSM_ST field + */ + sts = sec_mon_in32(&sec_mon_regs->hp_stat); + if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { + if (its == 1) { + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + } else { + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_NON_SECURE); + } + } +} + +static void fsl_secboot_bootscript_parse_failure(void) +{ + fsl_secboot_header_verification_failure(); +} + +/* + * Handles the errors in esbc boot. + * This function handles all the errors which might occur in the + * esbc boot phase. It will call the appropriate api to log the + * errors and set the error bits in the SEC_MON. + */ +void fsl_secboot_handle_error(int error) +{ + const struct fsl_secboot_errcode *e; + + for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; + e++) { + if (e->errcode == error) + printf("ERROR :: %x :: %s\n", error, e->name); + } + + switch (error) { + case ERROR_ESBC_CLIENT_HEADER_BARKER: + case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN: + case ERROR_ESBC_CLIENT_HEADER_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2: + case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: + case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: + case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: +#ifdef CONFIG_KEY_REVOCATION + case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: +#endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + /*@fallthrough@*/ + case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN: + case ERROR_IE_TABLE_NOT_FOUND: +#endif + fsl_secboot_header_verification_failure(); + break; + case ERROR_ESBC_SEC_RESET: + case ERROR_ESBC_SEC_DEQ: + case ERROR_ESBC_SEC_ENQ: + case ERROR_ESBC_SEC_DEQ_TO: + case ERROR_ESBC_SEC_JOBQ_STATUS: + case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY: + case ERROR_ESBC_CLIENT_HASH_COMPARE_EM: + fsl_secboot_image_verification_failure(); + break; + case ERROR_ESBC_MISSING_BOOTM: + fsl_secboot_bootscript_parse_failure(); + break; + case ERROR_ESBC_WRONG_CMD: + default: + branch_to_self(); + break; + } +} + +static void fsl_secblk_handle_error(int error) +{ + switch (error) { + case ERROR_ESBC_SEC_ENQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ); + break; + case ERROR_ESBC_SEC_DEQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ); + break; + case ERROR_ESBC_SEC_DEQ_TO: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO); + break; + default: + printf("Job Queue Output status %x\n", error); + fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS); + break; + } +} + +/* + * Calculate hash of key obtained via offset present in ESBC uboot + * client hdr. This function calculates the hash of key which is obtained + * through offset present in ESBC uboot client header. + */ +static int calc_img_key_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int i, srk = 0; + int ret = 0; + const char *algo_name = "sha256"; + + /* Calculate hash of the esbc key */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + if (ret) + return ret; + + /* Update hash for ESBC key */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); + srk = 1; + } +#endif + if (!srk) + ret = algo->hash_update(algo, ctx, + img->img_key, img->key_len, 1); + if (ret) + return ret; + + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) + return ret; + + for (i = 0; i < SHA256_BYTES; i++) + img->img_key_hash[i] = hash_val[i]; + + return 0; +} + +/* + * Calculate hash of ESBC hdr and ESBC. This function calculates the + * single hash of ESBC header and ESBC image. If SG flag is on, all + * SG entries are also hashed alongwith the complete SG table. + */ +static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int ret = 0; + int key_hash = 0; + const char *algo_name = "sha256"; + + /* Calculate the hash of the ESBC */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + /* Copy hash at destination buffer */ + if (ret) + return ret; + + /* Update hash for CSF Header */ + ret = algo->hash_update(algo, ctx, + (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); + if (ret) + return ret; + + /* Update the hash with that of srk table if srk flag is 1 + * If IE Table is selected, key is not added in the hash + * If neither srk table nor IE key table available, add key + * from header in the hash calculation + */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); + key_hash = 1; + } +#endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!key_hash && check_ie(img)) + key_hash = 1; +#endif + if (!key_hash) + ret = algo->hash_update(algo, ctx, + img->img_key, img->hdr.key_len, 0); + if (ret) + return ret; + + /* Update hash for actual Image */ + ret = algo->hash_update(algo, ctx, + (u8 *)img->hdr.pimg, img->hdr.img_size, 1); + if (ret) + return ret; + + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) + return ret; + + return 0; +} + +/* + * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the + * pointers for padding, DER value and hash. And finally, constructs EM' + * which includes hash of complete CSF header and ESBC image. If SG flag + * is on, hash of SG table and entries is also included. + */ +static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) +{ + /* + * RSA PKCSv1.5 encoding format for encoded message is below + * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash + * PS is Padding String + * DER is DER value for SHA-256 + * Hash is SHA-256 hash + * ********************************************************* + * representative points to first byte of EM initially and is + * filled with 0x0 + * representative is incremented by 1 and second byte is filled + * with 0x1 + * padding points to third byte of EM + * digest points to full length of EM - 32 bytes + * hash_id (DER value) points to 19 bytes before pDigest + * separator is one byte which separates padding and DER + */ + + size_t len; + u8 *representative; + u8 *padding, *digest; + u8 *hash_id, *separator; + int i; + + len = (get_key_len(img) / 2) - 1; + representative = img->img_encoded_hash_second; + representative[0] = 0; + representative[1] = 1; /* block type 1 */ + + padding = &representative[2]; + digest = &representative[1] + len - 32; + hash_id = digest - sizeof(hash_identifier); + separator = hash_id - 1; + + /* fill padding area pointed by padding with 0xff */ + memset(padding, 0xff, separator - padding); + + /* fill byte pointed by separator */ + *separator = 0; + + /* fill SHA-256 DER value pointed by HashId */ + memcpy(hash_id, hash_identifier, sizeof(hash_identifier)); + + /* fill hash pointed by Digest */ + for (i = 0; i < SHA256_BYTES; i++) + digest[i] = hash_val[i]; +} + +/* + * Reads and validates the ESBC client header. + * This function reads key and signature from the ESBC client header. + * If Scatter/Gather flag is on, lengths and offsets of images + * present as SG entries are also read. This function also checks + * whether the header is valid or not. + */ +static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) +{ + char buf[20]; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)img->ehdrloc; + u8 *k, *s; +#ifdef CONFIG_KEY_REVOCATION + u32 ret; + u32 key_num, key_revoc_flag, size; +#endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + struct ie_key_info *ie_info; + u32 ie_num, ie_revoc_flag, ie_key_len; +#endif + int key_found = 0; + + /* check barker code */ + if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) + return ERROR_ESBC_CLIENT_HEADER_BARKER; + + sprintf(buf, "%p", hdr->pimg); + setenv("img_addr", buf); + + if (!hdr->img_size) + return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + + /* Key checking*/ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk); + + if (ret != 0) + return ret; + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + + key_found = 1; + } +#endif + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!key_found && check_ie(img)) { + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + ie_info = (struct ie_key_info *)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) || + (ie_key_len == 2 * KEY_SIZE_BYTES / 2) || + (ie_key_len == 2 * KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; + key_found = 1; + } +#endif + + if (key_found == 0) { + /* check key length */ + if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) || + (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) || + (hdr->key_len == 2 * KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + key_found = 1; + } + + /* check signaure */ + if (get_key_len(img) == 2 * hdr->sign_len) { + /* check signature length */ + if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) || + (hdr->sign_len == KEY_SIZE_BYTES / 2) || + (hdr->sign_len == KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_SIG_LEN; + } else { + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN; + } + + memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); + + /* No SG support */ + if (hdr->sg_flag) + return ERROR_ESBC_CLIENT_HEADER_SG; + + /* modulus most significant bit should be set */ + k = (u8 *)&img->img_key; + + if ((k[0] & 0x80) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1; + + /* modulus value should be odd */ + if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2; + + /* Check signature value < modulus value */ + s = (u8 *)&img->img_sign; + + if (!(memcmp(s, k, hdr->sign_len) < 0)) + return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD; + + return ESBC_VALID_HDR; +} + +static inline int str2longbe(const char *p, ulong *num) +{ + char *endptr; + ulong tmp; + + if (!p) { + return 0; + } else { + tmp = simple_strtoul(p, &endptr, 16); + if (sizeof(ulong) == 4) + *num = cpu_to_be32(tmp); + else + *num = cpu_to_be64(tmp); + } + + return *p != '\0' && *endptr == '\0'; +} + +int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + ulong hash[SHA256_BYTES/sizeof(ulong)]; + char hash_str[NUM_HEX_CHARS + 1]; + ulong addr = simple_strtoul(argv[1], NULL, 16); + struct fsl_secboot_img_priv *img; + struct fsl_secboot_img_hdr *hdr; + void *esbc; + int ret, i, hash_cmd = 0; + u32 srk_hash[8]; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + + if (argc == 3) { + char *cp = argv[2]; + int i = 0; + + if (*cp == '0' && *(cp + 1) == 'x') + cp += 2; + + /* The input string expected is in hex, where + * each 4 bits would be represented by a hex + * sha256 hash is 256 bits long, which would mean + * num of characters = 256 / 4 + */ + if (strlen(cp) != SHA256_NIBBLES) { + printf("%s is not a 256 bits hex string as expected\n", + argv[2]); + return -1; + } + + for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) { + strncpy(hash_str, cp + (i * NUM_HEX_CHARS), + NUM_HEX_CHARS); + hash_str[NUM_HEX_CHARS] = '\0'; + if (!str2longbe(hash_str, &hash[i])) { + printf("%s is not a 256 bits hex string ", + argv[2]); + return -1; + } + } + + hash_cmd = 1; + } + + img = malloc(sizeof(struct fsl_secboot_img_priv)); + + if (!img) + return -1; + + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + + hdr = &img->hdr; + img->ehdrloc = addr; + esbc = (u8 *)img->ehdrloc; + + memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); + + /* read and validate esbc header */ + ret = read_validate_esbc_client_header(img); + + if (ret != ESBC_VALID_HDR) { + fsl_secboot_handle_error(ret); + goto exit; + } + + /* SRKH present in SFP */ + for (i = 0; i < NUM_SRKH_REGS; i++) + srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]); + + /* + * Calculate hash of key obtained via offset present in + * ESBC uboot client hdr + */ + ret = calc_img_key_hash(img); + if (ret) { + fsl_secblk_handle_error(ret); + goto exit; + } + + /* Compare hash obtained above with SRK hash present in SFP */ + if (hash_cmd) + ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES); + else + ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!hash_cmd && check_ie(img)) + ret = 0; +#endif + + if (ret != 0) { + fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY); + goto exit; + } + + ret = calc_esbchdr_esbc_hash(img); + if (ret) { + fsl_secblk_handle_error(ret); + goto exit; + } + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) { + fsl_secblk_handle_error(ret); + goto exit; + } + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); + + if (ret) { + fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM); + goto exit; + } + + printf("esbc_validate command successful\n"); + +exit: + return 0; +} diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 5aa11b12a4..e1148e568e 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -16,21 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "RAW timing DDR"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index 09b30b9aac..ab1c32d10e 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -6,35 +6,6 @@ #ifndef __DDR_H__ #define __DDR_H__ -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 2147483648u, - .capacity = 4294967296u, - .primary_sdram_width = 64, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 2, /* ECC */ - .burst_lengths_bitmask = 0x0c, - .tckmin_x_ps = 1071, - .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 6000, - .trp_ps = 13125, - .tras_ps = 34000, - .trc_ps = 48125, - .trfc_ps = 260000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 35000, -}; - struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/galaxy5200/Kconfig b/board/galaxy5200/Kconfig deleted file mode 100644 index 31035811e9..0000000000 --- a/board/galaxy5200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GALAXY5200 - -config SYS_BOARD - default "galaxy5200" - -config SYS_CONFIG_NAME - default "galaxy5200" - -endif diff --git a/board/galaxy5200/MAINTAINERS b/board/galaxy5200/MAINTAINERS deleted file mode 100644 index 614625d33f..0000000000 --- a/board/galaxy5200/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -GALAXY5200 BOARD -#M: Eric Millbrandt <emillbrandt@dekaresearch.com> -S: Orphan (since 2014-06) -F: board/galaxy5200/ -F: include/configs/galaxy5200.h -F: configs/galaxy5200_defconfig -F: configs/galaxy5200_LOWBOOT_defconfig diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile deleted file mode 100644 index e0fcd39515..0000000000 --- a/board/galaxy5200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := galaxy5200.o diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c deleted file mode 100644 index 5d957b7e70..0000000000 --- a/board/galaxy5200/galaxy5200.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messtechnik GmbH - * - * (C) Copyright 2009 - * Eric Millbrandt, DEKA Research and Development Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/io.h> - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32 (&sdram->mode, (SDRAM_EMODE)); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000)); -#endif - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - - /* auto refresh */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); - - /* set mode register */ - out_be32 (&sdram->mode, (SDRAM_MODE)); - - /* normal operation */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | hi_addr_bit)); - - /* set CDM clock enable register, set MPC5200B SDRAM bus */ - /* to reduced driver strength */ - out_be32 (&cdm->clock_enable, (0x00CFFFFF)); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make - * real use of CONFIG_SYS_SDRAM_BASE. The code does not - * work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram(int board_type) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - /* 256MB at 0x0 */ - out_be32 (&mm->sdram0, 0x0000001b); - /* disabled */ - out_be32 (&mm->sdram1, 0x10000000); - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32 (&mm->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - /* disabled */ - out_be32 (&mm->sdram0, 0); - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mm->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize + dramsize2; -} - -int checkboard(void) -{ - puts("Board: galaxy5200\n"); - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - debug ("init_ide_reset\n"); - - /* Configure TIMER_5 as GPIO output for ATA reset */ - /* Deassert reset */ - gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO; -} - -void ide_set_reset (int idereset) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - debug ("ide_reset(%d)\n", idereset); - - /* Configure TIMER_5 as GPIO output for ATA reset */ - if (idereset) { - gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO; - - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(50); - } else { - gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO; - udelay(50); - } -} -#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/board/jse/Kconfig b/board/jse/Kconfig deleted file mode 100644 index 48905fa76f..0000000000 --- a/board/jse/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_JSE - -config SYS_BOARD - default "jse" - -config SYS_CONFIG_NAME - default "JSE" - -endif diff --git a/board/jse/MAINTAINERS b/board/jse/MAINTAINERS deleted file mode 100644 index 818a5a0be4..0000000000 --- a/board/jse/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JSE BOARD -M: Stephen Williams <steve@icarus.com> -S: Maintained -F: board/jse/ -F: include/configs/JSE.h -F: configs/JSE_defconfig diff --git a/board/jse/Makefile b/board/jse/Makefile deleted file mode 100644 index feac3a8834..0000000000 --- a/board/jse/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright 2004 Picture Elements, Inc. -# Stephen Williams <steve@icarus.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = jse.o sdram.o flash.o host_bridge.o -obj-y += init.o diff --git a/board/jse/README.txt b/board/jse/README.txt deleted file mode 100644 index 84497db70f..0000000000 --- a/board/jse/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -JSE Configuration Details - -Memory Bank 0 -- Flash chip ---------------------------- - -0xfff00000 - 0xffffffff - -The flash chip is really only 512Kbytes, but the high address bit of -the 1Meg region is ignored, so the flash is replicated through the -region. Thus, this is consistent with a flash base address 0xfff80000. - -The placement at the end is to be consistent with reset behavior, -where the processor itself initially uses this bus to load the branch -vector and start running. - -On-Chip Memory --------------- - -0xf4000000 - 0xf4000fff - -The 405GPr includes a 4K on-chip memory that can be placed however -software chooses. I choose to place the memory at this address, to -keep it out of the cachable areas. - - -Memory Bank 1 -- SystemACE Controller -------------------------------------- - -0xf0000000 - 0xf00fffff - -The SystemACE chip is along on peripheral bank CS#1. We don't need -much space, but 1Meg is the smallest we can configure the chip to -allocate. We need it far away from the flash region, because this -region is set to be non-cached. - - -Internal Peripherals --------------------- - -0xef600300 - 0xef6008ff - -These are scattered various peripherals internal to the PPC405GPr -chip. - -SDRAM ------ - -0x00000000 - 0x07ffffff (128 MBytes) diff --git a/board/jse/flash.c b/board/jse/flash.c deleted file mode 100644 index a550f7d03e..0000000000 --- a/board/jse/flash.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#if CONFIG_SYS_MAX_FLASH_BANKS != 1 -#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*----------------------------------------------------------------------- - */ -/* - * This implementation assumes that the flash chips are uniform sector - * devices. This is true for all likely JSE devices. - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - unsigned idx; - unsigned long sector_size = info->size / info->sector_count; - - for (idx = 0; idx < info->sector_count; idx += 1) { - info->start[idx] = base + (idx * sector_size); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("ST Micro "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* (Reduced table of only parts expected in JSE boards.) */ - switch (info->flash_id) { - case FLASH_MAN_AMD | FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_MAN_STM | FLASH_AM040: - printf ("MM29W040W (512 Kbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - printf("Unknown flash manufacturer code: 0x%x\n", value); - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */ - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* Calculate the sector offsets (Use JSE Optimized code). */ - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay (1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c deleted file mode 100644 index 76c07b0c35..0000000000 --- a/board/jse/host_bridge.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ident "$Id:$" - -# include <common.h> -# include <pci.h> -# include "jse_priv.h" - -/* - * The JSE board has an Intel 21555 non-transparent bridge for - * communication with the host. We need to render it harmless on the - * JSE side, but leave it alone on the host (primary) side. Normally, - * this will all be done before the host BIOS can gain access to the - * board, due to the Primary Access Lockout bit. - * - * The host_bridge_init function is called as a late initialization - * function, after most of the board is set up, including a PCI scan. - */ - -void host_bridge_init (void) -{ - /* The bridge chip is at a fixed location. */ - pci_dev_t dev = PCI_BDF (0, 10, 0); - - /* Set PCI Class code -- - The primary side sees this class code at 0x08 in the - primary config space. This must be something other then a - bridge, or MS Windows starts doing weird stuff to me. */ - pci_write_config_dword (dev, 0x48, 0x04800000); - - /* Set subsystem ID -- - The primary side sees this value at 0x2c. We set it here so - that the host can tell what sort of device this is: - We are a Picture Elements [0x12c5] JSE [0x008a]. */ - pci_write_config_dword (dev, 0x6c, 0x008a12c5); - - /* Downstream (Primary-to-Secondary) BARs are set up mostly - off. We need only the Memory-0 Bar so that the host can get - at the CSR region to set up tables and the lot. */ - - /* Downstream Memory 0 setup (4K for CSR) */ - pci_write_config_dword (dev, 0xac, 0xfffff000); - /* Downstream Memory 1 setup (off) */ - pci_write_config_dword (dev, 0xb0, 0x00000000); - /* Downstream Memory 2 setup (off) */ - pci_write_config_dword (dev, 0xb4, 0x00000000); - /* Downstream Memory 3 setup (off) */ - pci_write_config_dword (dev, 0xb8, 0x00000000); - - /* Upstream (Secondary-to-Primary) BARs are used to get at - host memory from the JSE card. Create two regions: a small - one to manage individual word reads/writes, and a larger - one for doing bulk frame moves. */ - - /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */ - pci_write_config_dword (dev, 0xc4, 0xfffff000); - /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */ - pci_write_config_dword (dev, 0xc8, 0xfffff000); - - /* Upstream Memory 2 (BAR4) uses page translation, and is set - up in CCR1. Configure for 4K pages. */ - - /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout - bit as well, so we are done configuring after this - point. Therefore, this must be the last step. - - CC1[15:12]= 0 (disable I2O message unit) - CC1[11:8] = 0x5 (4K page size) - CC0[11] = 1 (Secondary Clock Disable: disable clock) - CC0[10] = 0 (Primary Access Lockout: allow primary access) - */ - pci_write_config_dword (dev, 0xcc, 0x05000800); -} diff --git a/board/jse/init.S b/board/jse/init.S deleted file mode 100644 index 4e449fef20..0000000000 --- a/board/jse/init.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* */ -/* */ -/* The layout for the PEI JSE board: */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - SystemACE */ -/* Bank 2 - not used */ -/* Bank 3 - not used */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - not used */ -/*------------------------------------------------------------------------- */ -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*----------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------- */ - /* Memory Bank 0 (Flash) initialization */ - /*----------------------------------------------------------------- */ - - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr diff --git a/board/jse/jse.c b/board/jse/jse.c deleted file mode 100644 index a0913c33f0..0000000000 --- a/board/jse/jse.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -# include <common.h> -# include <asm/ppc4xx.h> -# include <asm/processor.h> -# include <asm/io.h> -# include "jse_priv.h" - -/* - * This function is run very early, out of flash, and before devices are - * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue - * of being in the init_sequence array. - * - * The SDRAM has been initialized already -- start.S:start called - * init.S:init_sdram early on -- but it is not yet being used for - * anything, not even stack. So be careful. - */ -int board_early_init_f (void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the JSE board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED/UNUSED - | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive - | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive - | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive - | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high - | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) - | IRQ 31 (EXT IRQ 6) (unused) - +-------------------------------------------------------------------------*/ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* Configure the interface to the SystemACE MCU port. - The SystemACE is fast, but there is no reason to have - excessivly tight timings. So the settings are slightly - generous. */ - - /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, - WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, 0x01011000); - - /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); - - /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ - /* CPC0_CR1 |= PCIPW */ - mtdcr (0xb2, mfdcr (0xb2) | 0x00004000); - - return 0; -} - -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) -{ - return board_early_init_f (); -} - -#endif - -/* - * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is - * also in the init_sequence array) but later. Many more things are - * configured, but we are still running from flash. - */ -int checkboard (void) -{ - unsigned vers, status; - - /* check that the SystemACE chip is alive. */ - printf ("ACE: "); - vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16); - printf ("SystemACE %u.%u (build %u)", - (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); - - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); -#ifdef DEBUG - printf (" STATUS=0x%08x", status); -#endif - /* If the flash card is present and there is an initial error, - then force a restart of the program. */ - if (status & 0x00000010) { - printf (" CFDETECT"); - - if (status & 0x04) { - /* CONTROLREG = CFGPROG */ - writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - udelay (500); - /* CONTROLREG = CFGRESET */ - writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - udelay (500); - writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - /* CONTROLREG = CFGSTART */ - writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); - } - } - - /* Wait for the SystemACE to program its chain of devices. */ - while ((status & 0x84) == 0x00) { - udelay (500); - status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); - } - - if (status & 0x04) - printf (" CFG-ERROR"); - if (status & 0x80) - printf (" CFGDONE"); - - printf ("\n"); - - /* Force /RTS to active. The board it not wired quite - correctly to use cts/rtc flow control, so just force the - /RST active and forget about it. */ - writeb (readb (0xef600404) | 0x03, 0xef600404); - - printf ("JSE: ready\n"); - - return 0; -} - -/* **** No more functions called by board_init_f. **** */ - -/* - * This function is called by arch/powerpc/lib/board.c:board_init_r. At this - * point, basic setup is done, U-Boot has been moved into SDRAM and - * PCI has been set up. From here we done late setup. - */ -int misc_init_r (void) -{ - host_bridge_init (); - return 0; -} diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h deleted file mode 100644 index f61204bbae..0000000000 --- a/board/jse/jse_priv.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __jse_priv_H -#define __jse_prov_H -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern void host_bridge_init(void); - -#endif diff --git a/board/jse/sdram.c b/board/jse/sdram.c deleted file mode 100644 index 5639beddce..0000000000 --- a/board/jse/sdram.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -# define SDRAM_LEN 0x08000000 - -/* - * this is even after checkboard. It returns the size of the SDRAM - * that we have installed. This function is called by board_init_f - * in arch/powerpc/lib/board.c to initialize the memory and return what I - * found. - */ -phys_size_t initdram (int board_type) -{ - /* Configure the SDRAMS */ - - /* disable memory controller */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x00000000); - - udelay (500); - - /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0); - mtdcr (SDRAM0_CFGDATA, 0xffffffff); - - /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1); - mtdcr (SDRAM0_CFGDATA, 0xffffffff); - - /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - mtdcr (SDRAM0_CFGDATA, 0x00000000); - - /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR); - mtdcr (SDRAM0_CFGDATA, 0xffffffff); - - /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, 0x010a4016); - - /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, 0x00084001); - - /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - mtdcr (SDRAM0_CFGDATA, 0x04084001); - - /* Memory Bank 2 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - mtdcr (SDRAM0_CFGDATA, 0x00000000); - - /* Memory Bank 3 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - mtdcr (SDRAM0_CFGDATA, 0x00000000); - - /* refresh timer = 0x400 */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, 0x04000000); - - /* Power management idle timer set to the default. */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT); - mtdcr (SDRAM0_CFGDATA, 0x07c00000); - - udelay (500); - - /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x80e00000); - - return SDRAM_LEN; -} - -/* - * The U-Boot core, as part of the initialization to prepare for - * loading the monitor into SDRAM, requests of this function that the - * memory be tested. Return 0 if the memory tests OK. - */ -int testdram (void) -{ - unsigned long idx; - unsigned val; - unsigned errors; - volatile unsigned long *sdram; - -#ifdef DEBUG - printf ("SDRAM Controller Registers --\n"); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_CFG : 0x%08x\n", val); - - mtdcr (SDRAM0_CFGADDR, 0x24); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_STATUS: 0x%08x\n", val); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_B0CR : 0x%08x\n", val); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_B1CR : 0x%08x\n", val); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_TR : 0x%08x\n", val); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - val = mfdcr (SDRAM0_CFGDATA); - printf (" SDRAM0_RTR : 0x%08x\n", val); -#endif - - /* Wait for memory to be ready by testing MRSCMPbit - bit. Really, there should already have been plenty of time, - given it was started long ago. But, best to check. */ - for (idx = 0; idx < 1000000; idx += 1) { - mtdcr (SDRAM0_CFGADDR, 0x24); - val = mfdcr (SDRAM0_CFGDATA); - if (val & 0x80000000) - break; - } - - if (!(val & 0x80000000)) { - printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n"); - return 1; - } - - /* Start memory test. */ - printf ("test: %u MB - ", SDRAM_LEN / 1048576); - - sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE; - - printf ("write - "); - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { - sdram[idx + 0] = idx; - sdram[idx + 1] = ~idx; - } - - printf ("read - "); - errors = 0; - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { - if (sdram[idx + 0] != idx) - errors += 1; - if (sdram[idx + 1] != ~idx) - errors += 1; - if (errors > 0) - break; - } - - if (errors > 0) { - printf ("NOT OK\n"); - printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n", - sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx); - return 1; - } - - printf ("ok\n"); - return 0; -} diff --git a/board/korat/Kconfig b/board/korat/Kconfig deleted file mode 100644 index f434dea7f3..0000000000 --- a/board/korat/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_KORAT - -config SYS_BOARD - default "korat" - -config SYS_CONFIG_NAME - default "korat" - -endif diff --git a/board/korat/MAINTAINERS b/board/korat/MAINTAINERS deleted file mode 100644 index 8b968461f2..0000000000 --- a/board/korat/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KORAT BOARD -M: Larry Johnson <lrj@acm.org> -S: Maintained -F: board/korat/ -F: include/configs/korat.h -F: configs/korat_defconfig -F: configs/korat_perm_defconfig diff --git a/board/korat/Makefile b/board/korat/Makefile deleted file mode 100644 index 63914bc13b..0000000000 --- a/board/korat/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = korat.o -extra-y += init.o diff --git a/board/korat/README b/board/korat/README deleted file mode 100644 index e059f788c4..0000000000 --- a/board/korat/README +++ /dev/null @@ -1,64 +0,0 @@ -The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to -chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to -addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains -from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash -Bank #1 (with the starting address depending on the flash size detected at -runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0 -cannot be modified in the field. This also prevents FLASH0 from executing -commands to return chip information, so its configuration is hard-coded in -U-Boot. - -There are two versions of U-Boot for Korat: "permanent" and "upgradable". The -permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses -0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is -located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000 -for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are -used for the U-Boot environmental parameters, and addresses 0xF7FC0000 - -0xF7FDFFFF are used for the redundant copy of the parameters. These locations -are used by both versions of U-Boot. - -On booting, the permanent U-Boot in FLASH0 begins executing. After performing -minimal setup, it monitors the state of the board's Reset switch (GPIO47). If -the switch is sensed as open before a timeout period, then U-Boot branches to -address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the -beginning. If the switch remains closed thoughout the timeout period, the -permanent U-Boot activates the on-board buzzer until the switch is sensed as -opened. It then continues to execute without branching to FLASH1. The effect -of this is that normally the Korat board boots its upgradable U-Boot, but, if -this has been corrupted, the user can boot the permanent U-Boot, which can then -be used to erase and reload FLASH1 as needed. - -Note that it is not necessary for the permanent U-Boot to have all the latest -features, but only that it have sufficient functionality (working "tftp", -"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no -assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is -sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC. - -The build sequence: - - make korat_perm_config - make all - -builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining -preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build: - - make korat_config - make all - -creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and -leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined. - -2008-02-22, Larry Johnson <lrj@acm.org> - - -The CompactFlash(R) controller on the Korat board provides a hi-speed USB -interface. This may be connected to either a dedicated port on the on-board -USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot -environment variable "korat_usbcf" can be used to specify which of these two -USB host ports is used for CompactFlash. The valid setting for the variable are -the strings "pci" and "ppc". If the variable defined and set to "ppc", then the -PowerPC USB port is used. In all other cases the on-board USB controller is -used, but if "korat_usbcf" is defined but is set to a string other than the two -valid options, a warning is also issued. - -2009-01-28, Larry Johnson <lrj@acm.org> diff --git a/board/korat/config.mk b/board/korat/config.mk deleted file mode 100644 index 42e0060094..0000000000 --- a/board/korat/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# Korat (PPC440EPx) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(emul),1) -PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2 -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000 -endif - -ifndef CONFIG_KORAT_PERMANENT -LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds -endif diff --git a/board/korat/init.S b/board/korat/init.S deleted file mode 100644 index 20c5bddf6b..0000000000 --- a/board/korat/init.S +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G ) - - /* - * TLB entries for SDRAM are not needed on this platform. They are - * generated dynamically in the SPD DDR2 detection routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, - AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG ) - - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG ) - - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG ) - - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG ) - - /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ - tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG) - - /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG) - - tlbtab_end - -#if defined(CONFIG_KORAT_PERMANENT) - .globl korat_branch_absolute -korat_branch_absolute: - mtlr r3 - blr -#endif diff --git a/board/korat/korat.c b/board/korat/korat.c deleted file mode 100644 index d9ab2fd421..0000000000 --- a/board/korat/korat.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * (C) Copyright 2007-2010 - * Larry Johnson, lrj@acm.org - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fdt_support.h> -#include <i2c.h> -#include <libfdt.h> -#include <asm/ppc440.h> -#include <asm/bitops.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <asm/ppc4xx-uic.h> -#include <asm/processor.h> -#include <asm/4xx_pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size(ulong base, int banknum); - -#if defined(CONFIG_KORAT_PERMANENT) -void korat_buzzer(int const on) -{ - if (on) { - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80); - } else { - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80); - } -} -#endif - -int board_early_init_f(void) -{ - uint32_t sdr0_pfc1, sdr0_pfc2; - uint32_t reg; - int eth; - -#if defined(CONFIG_KORAT_PERMANENT) - unsigned mscount; - - extern void korat_branch_absolute(uint32_t addr); - - for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { - udelay(1000); - if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { - /* This call does not return. */ - korat_branch_absolute( - CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); - } - } - korat_buzzer(1); - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) - udelay(1000); - - korat_buzzer(0); -#endif - - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* - * Take sim card reader and CF controller out of reset. Also enable PHY - * auto-detect until board-specific PHY resets are available. - */ - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); - - /* Configure the two Ethernet PHYs. For each PHY, configure for fiber - * if the SFP module is present, and for copper if it is not present. - */ - for (eth = 0; eth < 2; ++eth) { - if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { - /* SFP module not present: configure PHY for copper. */ - /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | - 0x06 << (4 * eth)); - } else { - /* SFP module present: configure PHY for fiber and - enable output */ - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); - gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); - } - } - /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); - - /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ - udelay(1000); - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); - - /* select Ethernet (and optionally IIC1) pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; -#ifdef CONFIG_I2C_MULTI_BUS - sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); -#endif - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* PCI arbiter enabled */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); - - return 0; -} - -/* - * The boot flash on CS0 normally has its write-enable pin disabled, and so will - * not respond to CFI commands. This routine therefore fills in the flash - * information for the boot flash. (The flash at CS1 operates normally.) - */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) -{ - uint32_t addr; - int i; - - if (1 != banknum) - return 0; - - info->size = CONFIG_SYS_FLASH0_SIZE; - info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000; - info->flash_id = 0x01000000; - info->portwidth = 2; - info->chipwidth = 2; - info->buffer_size = 32; - info->erase_blk_tout = 16384; - info->write_tout = 2; - info->buffer_write_tout = 5; - info->vendor = 2; - info->cmd_reset = 0x00F0; - info->interface = 2; - info->legacy_unlock = 0; - info->manufacturer_id = 1; - info->device_id = 0x007E; - -#if CONFIG_SYS_FLASH0_SIZE == 0x01000000 - info->device_id2 = 0x2101; -#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 - info->device_id2 = 0x2301; -#else -#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE -#endif - - info->ext_addr = 0x0040; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0055; - info->addr_unlock1 = 0x00000555; - info->addr_unlock2 = 0x000002AA; - info->name = "CFI conformant"; - for (i = 0, addr = -info->size; - i < info->sector_count; - ++i, addr += 0x20000) { - info->start[i] = addr; - info->protect[i] = 0x00; - } - return 1; -} - -static int man_data_read(unsigned int addr) -{ - /* - * Read an octet of data from address "addr" in the manufacturer's - * information serial EEPROM, or -1 on error. - */ - u8 data[2]; - - if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) || - 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) { - debug("man_data_read(0x%02X) failed\n", addr); - return -1; - } - debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]); - return data[0]; -} - -static unsigned int man_data_field_addr(unsigned int const field) -{ - /* - * The manufacturer's information serial EEPROM contains a sequence of - * zero-delimited fields. Return the starting address of field "field", - * or 0 on error. - */ - unsigned addr, i; - - if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1)) - /* Only format "A" is currently supported */ - return 0; - - for (addr = 2, i = 1; i < field && addr < 256; ++addr) { - if ('\0' == man_data_read(addr)) - ++i; - } - return (addr < 256) ? addr : 0; -} - -static char *man_data_read_field(char s[], unsigned const field, - unsigned const length) -{ - /* - * Place the null-terminated contents of field "field" of length - * "length" from the manufacturer's information serial EEPROM into - * string "s[length + 1]" and return a pointer to s, or return 0 on - * error. In either case the original contents of s[] is not preserved. - */ - unsigned addr, i; - - addr = man_data_field_addr(field); - if (0 == addr || addr + length >= 255) - return 0; - - for (i = 0; i < length; ++i) { - int const c = man_data_read(addr++); - - if (c <= 0) - return 0; - - s[i] = (char)c; - } - if (0 != man_data_read(addr)) - return 0; - - s[i] = '\0'; - return s; -} - -static void set_serial_number(void) -{ - /* - * If the environmental variable "serial#" is not set, try to set it - * from the manufacturer's information serial EEPROM. - */ - char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2]; - - if (getenv("serial#")) - return; - - if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH)) - return; - - s[MAN_INFO_LENGTH] = '-'; - if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD, - MAN_MAC_ADDR_LENGTH)) - return; - - setenv("serial#", s); -} - -static void set_mac_addresses(void) -{ - /* - * If the environmental variables "ethaddr" and/or "eth1addr" are not - * set, try to set them from the manufacturer's information serial - * EEPROM. - */ - -#if MAN_MAC_ADDR_LENGTH % 2 != 0 -#error MAN_MAC_ADDR_LENGTH must be an even number -#endif - - char s[(3 * MAN_MAC_ADDR_LENGTH) / 2]; - char *src; - char *dst; - - if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) - return; - - if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1, - MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH)) - return; - - for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) { - *dst++ = *src++; - *dst++ = *src++; - *dst++ = ':'; - } - if (0 == getenv("ethaddr")) - setenv("ethaddr", s); - - if (0 == getenv("eth1addr")) { - ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2]; - setenv("eth1addr", s); - } -} - -int misc_init_r(void) -{ - uint32_t pbcr; - int size_val; - uint32_t reg; - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; - char const *const act = getenv("usbact"); - char const *const usbcf = getenv("korat_usbcf"); - - /* - * Re-do FLASH1 sizing and adjust flash start and offset. - */ - gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; - gd->bd->bi_flashoffset = 0; - - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(flash1_size) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - - /* - * Re-do FLASH1 sizing and adjust flash offset to reserve space for - * environment - */ - gd->bd->bi_flashoffset = - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; - - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ -#if defined(CONFIG_KORAT_PERMANENT) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - flash_info + 1); -#else - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - flash_info); -#endif - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - flash_info); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - flash_info); - - /* - * USB suff... - */ - /* - * Select the USB controller on the 440EPx ("ppc") or on the PCI bus - * ("pci") for the CompactFlash. - */ - if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) { - /* - * If environment variable "usbcf" is defined and set to "ppc", - * then connect the CompactFlash controller to the PowerPC USB - * port. - */ - printf("Attaching CompactFlash controller to PPC USB\n"); - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10); - } else { - if (usbcf != NULL && (strcmp(usbcf, "pci") != 0)) - printf("Warning: \"korat_usbcf\" is not set to a legal " - "value (\"ppc\" or \"pci\")\n"); - - printf("Attaching CompactFlash controller to PCI USB\n"); - } - if (act == NULL || strcmp(act, "hostdev") == 0) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - /* - * To enable the USB 2.0 Device function - * through the UTMI interface - */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* clear resets */ - udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy) Device(ext phy)\n"); - - } else if (strcmp(act, "dev") == 0) { - /*-------------------PATCH-------------------------------*/ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay(1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay(1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay(1000); - mtsdr(SDR0_SRST1, 0x60306000); - /*-------------------PATCH-------------------------------*/ - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* clear resets */ - udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device(int phy)\n"); - } - - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); - mtsdr(SDR0_SRST1, reg); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - set_serial_number(); - set_mac_addresses(); - gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1); - - return 0; -} - -int checkboard(void) -{ - char const *const s = getenv("serial#"); - u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0); - - printf("Board: Korat, Rev. %X", rev); - if (s) - printf(", serial# %s", s); - - printf(".\n Ethernet PHY 0: "); - if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL)) - printf("fiber"); - else - printf("copper"); - - printf(", PHY 1: "); - if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL)) - printf("fiber"); - else - printf("copper"); - - printf(".\n"); -#if defined(CONFIG_KORAT_PERMANENT) - printf(" Executing permanent copy of U-Boot.\n"); -#endif - return 0; -} - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); -} -#endif - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* First do 440EP(x) common setup */ - __pci_target_init(hose); - - /* - * Set up Configuration registers for on-board NEC uPD720101 USB - * controller. - */ - pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[4]; - int rc; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR mapping */ - val[0] = 1; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; - rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds deleted file mode 100644 index bee4d9a9a2..0000000000 --- a/board/korat/u-boot-F7FC.lds +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xF7FBFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xF7FBF000 : - { - arch/powerpc/cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 08fcaf21b3..3d019b0142 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); } +void omap3_set_aux_cr_secure(u32 acr) +{ + struct emu_hal_params_rx51 emu_romcode_params = { 0, }; + + emu_romcode_params.num_params = 2; + emu_romcode_params.param1 = acr; + + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); +} + /* * Routine: omap3_update_aux_cr_secure_rx51 * Description: Modify the contents Auxiliary Control Register. @@ -350,19 +361,13 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) */ static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) { - struct emu_hal_params_rx51 emu_romcode_params = { 0, }; u32 acr; /* Read ACR */ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; - - emu_romcode_params.num_params = 2; - emu_romcode_params.param1 = acr; - - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); + omap3_set_aux_cr_secure(acr); } /* diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 80ef8fdcb2..018dddba15 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -21,6 +21,7 @@ #include <asm/arch/pwm.h> #endif #include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> @@ -180,6 +181,14 @@ int board_late_init(void) /* Make sure we finish initing the LCD */ tegra_lcd_check_next_stage(gd->fdt_blob, 1); #endif +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (tegra_cpu_is_non_secure()) { + printf("CPU is in NS mode\n"); + setenv("cpu_ns_mode", "1"); + } else { + setenv("cpu_ns_mode", ""); + } +#endif return 0; } diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index daa74a4be0..52425a8f6d 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; */ void pinmux_init(void) { - pinmux_set_tristate_input_clamping(); + pinmux_clear_tristate_input_clamping(); gpio_config_table(jetson_tk1_gpio_inits, ARRAY_SIZE(jetson_tk1_gpio_inits)); diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index de4eb35598..863721b2a3 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,77 +15,47 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { /* gpio, init_val */ - GPIO_INIT(C7, IN), - GPIO_INIT(G0, OUT0), - GPIO_INIT(G1, OUT0), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), GPIO_INIT(G2, IN), GPIO_INIT(G3, IN), + GPIO_INIT(G4, IN), GPIO_INIT(H2, OUT0), - GPIO_INIT(H3, OUT0), GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT0), + GPIO_INIT(H7, IN), GPIO_INIT(I0, OUT0), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, IN), + GPIO_INIT(I1, IN), GPIO_INIT(I6, IN), GPIO_INIT(J0, IN), - GPIO_INIT(J2, IN), GPIO_INIT(K1, OUT0), GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), GPIO_INIT(K4, OUT0), - GPIO_INIT(K5, OUT0), GPIO_INIT(K6, OUT0), GPIO_INIT(N7, IN), - GPIO_INIT(O0, IN), GPIO_INIT(O1, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O3, IN), GPIO_INIT(O4, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P0, OUT0), - GPIO_INIT(P1, OUT0), GPIO_INIT(P2, OUT0), GPIO_INIT(Q0, IN), - GPIO_INIT(Q1, IN), - GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), GPIO_INIT(Q5, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, OUT0), GPIO_INIT(R2, OUT0), GPIO_INIT(R4, IN), - GPIO_INIT(R5, OUT0), GPIO_INIT(R7, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, IN), - GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, IN), GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U0, OUT0), + GPIO_INIT(T1, IN), + GPIO_INIT(U0, IN), GPIO_INIT(U1, IN), GPIO_INIT(U2, IN), - GPIO_INIT(U3, OUT0), - GPIO_INIT(U4, OUT0), + GPIO_INIT(U3, IN), + GPIO_INIT(U4, IN), GPIO_INIT(U5, IN), GPIO_INIT(U6, IN), GPIO_INIT(V0, IN), GPIO_INIT(V1, IN), - GPIO_INIT(W2, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, OUT0), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, OUT0), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X4, IN), GPIO_INIT(X7, OUT0), GPIO_INIT(BB3, OUT0), GPIO_INIT(BB5, OUT0), @@ -93,10 +63,7 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { GPIO_INIT(BB7, OUT0), GPIO_INIT(CC1, IN), GPIO_INIT(CC2, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(EE1, OUT0), - GPIO_INIT(FF1, OUT0), - GPIO_INIT(FF2, IN), + GPIO_INIT(EE2, OUT1), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ @@ -114,152 +81,152 @@ static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ - PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), @@ -279,30 +246,30 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), - PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT), PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), }; diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig new file mode 100644 index 0000000000..8df9421b57 --- /dev/null +++ b/board/quipos/cairo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_CAIRO + +config SYS_BOARD + default "cairo" + +config SYS_VENDOR + default "quipos" + +config SYS_CONFIG_NAME + default "omap3_cairo" + +endif diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile new file mode 100644 index 0000000000..445088f27b --- /dev/null +++ b/board/quipos/cairo/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 DENX Software Engineering +# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cairo.o diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c new file mode 100644 index 0000000000..b97a09ab15 --- /dev/null +++ b/board/quipos/cairo/cairo.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014 DENX + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Derived from code written by Robert Aigner (ra@spiid.net) + * + * Itself derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <netdev.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> +#include <asm/omap_mmc.h> +#include "cairo.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. + */ +u8 omap3_evm_need_extvbus(void) +{ + u8 retval = 0; + + /* TODO: verify if cairo handheld platform needs extvbus programming */ + + return retval; +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_CAIRO(); +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + * + * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6 + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->sharing = SAMSUNG_SHARING; + timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); + timings->ctrla = SAMSUNG_V_ACTIMA_165; + timings->ctrlb = SAMSUNG_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = SAMSUNG_V_MR_165; +} +#endif + +static const struct ns16550_platdata cairo_serial = { + OMAP34XX_UART2, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(cairo_uart) = { + "serial_omap", + &cairo_serial +}; + +/* force SPL booting into U-Boot, not Linux */ +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h new file mode 100644 index 0000000000..50734d0104 --- /dev/null +++ b/board/quipos/cairo/cairo.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) DENX + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Original code (C) Copyright 2010 + * Robert Aigner (ra@spiid.net) + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _EVM_H_ +#define _EVM_H_ + + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 Cairo board", + "NAND", +}; + +/* + * OMAP3 Cairo handheld hardware revision + */ +enum { + OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */ + OMAP3_CAIRO_BOARD_GEN_2, +}; + +#define MUX_CAIRO() \ +MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \ + (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ + +#endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 9cf54e51ac..9d0eb91977 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -355,7 +355,7 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO - default m + default n ---help--- Say y here if the LCD panel needs to be configured via i2c. This will add a bitbang i2c controller using gpios to talk to the LCD. diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 9a287d3c30..ef3c93711b 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -8,6 +8,7 @@ F: configs/ba10_tv_box_defconfig F: configs/Chuwi_V7_CW0825_defconfig F: configs/Cubieboard_defconfig F: configs/Hyundai_A7HD_defconfig +F: configs/jesurun_q5_defconfig F: configs/Mele_A1000_defconfig F: configs/Mele_M3_defconfig F: configs/Mini-X_defconfig @@ -30,7 +31,10 @@ F: configs/Bananapro_defconfig F: configs/i12-tvbox_defconfig F: configs/Linksprite_pcDuino3_defconfig F: configs/Linksprite_pcDuino3_fdt_defconfig +F: configs/Orangepi_defconfig +F: configs/Orangepi_mini_defconfig F: configs/qt840a_defconfig +F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/Ippo_q8h_v1_2_defconfig @@ -64,6 +68,11 @@ F: include/configs/sun7i.h F: configs/Cubieboard2_defconfig F: configs/Cubietruck_defconfig +FORFUN-Q88DB TABLET +M: Jens Lucius <info@jenslucius.com> +S: Maintained +F: configs/forfun_q88db_defconfig + GEMEI-G9 TABLET M: Priit Laes <plaes@plaes.org> S: Maintained @@ -100,11 +109,21 @@ M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained F: configs/Marsboard_A10_defconfig +MELE I7 BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/Mele_I7_defconfig + MELE M5 BOARD M: Ian Campbell <ijc@hellion.org.uk> S: Maintained F: configs/Mele_M5_defconfig +MK808C BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/MK808C_defconfig + MSI-PRIMO73 BOARD M: Siarhei Siamashka <siarhei.siamashka@gmail.com> S: Maintained @@ -119,3 +138,8 @@ TZX-Q8-713B7 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained F: configs/TZX-Q8-713B7_defconfig + +WEXLER-TAB7200 BOARD +M: Aleksei Mamlin <mamlinav@gmail.com> +S: Maintained +F: configs/Wexler_TAB7200_defconfig diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index e52d54c32e..660b18ebbd 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -24,7 +24,7 @@ static struct dram_para dram_para = { # include "dram_timings_sun4i.h" .active_windowing = 1, #endif - .tpr3 = 0, + .tpr3 = CONFIG_DRAM_TPR3, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig new file mode 100644 index 0000000000..dd9816ec24 --- /dev/null +++ b/board/sysam/amcore/Kconfig @@ -0,0 +1,22 @@ +if TARGET_AMCORE + +config SYS_CPU + string + default "mcf530x" + +config SYS_BOARD + string + default "amcore" + +config SYS_VENDOR + string + default "sysam" + +config SYS_CONFIG_NAME + string + default "amcore" + +endif + + + diff --git a/board/sysam/amcore/MAINTAINERS b/board/sysam/amcore/MAINTAINERS new file mode 100644 index 0000000000..fe5dd9bf39 --- /dev/null +++ b/board/sysam/amcore/MAINTAINERS @@ -0,0 +1,6 @@ +AMCORE BOARD +M: Angelo Dureghello <angelo@sysam.it> +S: Maintained +F: board/sysam/amcore/ +F: include/configs/amcore.h +F: configs/amcore_defconfig diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile new file mode 100644 index 0000000000..051186f0d5 --- /dev/null +++ b/board/sysam/amcore/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = amcore.o diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c new file mode 100644 index 0000000000..42b7c23f06 --- /dev/null +++ b/board/sysam/amcore/amcore.c @@ -0,0 +1,101 @@ +/* + * Board functions for Sysam AMCORE (MCF5307 based) board + * + * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file copies memory testdram() from sandburst/common/sb_common.c + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +void init_lcd(void) +{ + /* setup for possible K0108 lcd connected on the parallel port */ + sim_t *sim = (sim_t *)(MMAP_SIM); + + out_be16(&sim->par, 0x300); + + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); + + out_be16(&gpio->paddr, 0xfcff); + out_be16(&gpio->padat, 0x0c00); +} + +int checkboard(void) +{ + puts("Board: "); + puts("AMCORE v.001(alpha)\n"); + + init_lcd(); + + return 0; +} + +/* + * in initdram we are here executing from flash + * case 1: + * is with no ACR/flash cache enabled + * nop = 40ns (scope measured) + */ +void fudelay(int usec) +{ + while (usec--) + asm volatile ("nop"); +} + +phys_size_t initdram(int board_type) +{ + u32 dramsize, RC; + + sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC); + + /* + * SDRAM MT48LC4M32B2 details + * Memory block 0: 16 MB of SDRAM at address $00000000 + * Port size: 32-bit port + * + * Memory block 0 wired as follows: + * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 + * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 + * + * Ensure that there is a delay of at least 100 microseconds from + * processor reset to the following code so that the SDRAM is ready + * for commands. + */ + fudelay(100); + + /* + * DCR + * set proper RC as per specification + */ + RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* 0x8000 is the faster option */ + out_be16(&dc->dcr, 0x8200 | RC); + + /* + * DACR0, page mode continuous, CMD on A20 0x0300 + */ + out_be32(&dc->dacr0, 0x00003304); + + dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; + out_be32(&dc->dmr0, dramsize|1); + + /* issue a PRECHARGE ALL */ + out_be32(&dc->dacr0, 0x0000330c); + out_be32((u32 *)0x00000004, 0xbeaddeed); + /* issue AUTOREFRESH */ + out_be32(&dc->dacr0, 0x0000b304); + /* let refresh occour */ + fudelay(1); + + out_be32(&dc->dacr0, 0x0000b344); + out_be32((u32 *)0x00000c00, 0xbeaddeed); + + return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); +} diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk new file mode 100644 index 0000000000..d01a8bb567 --- /dev/null +++ b/board/sysam/amcore/config.mk @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/sysam/amcore/u-boot.lds b/board/sysam/amcore/u-boot.lds new file mode 100644 index 0000000000..2f7a24132c --- /dev/null +++ b/board/sysam/amcore/u-boot.lds @@ -0,0 +1,87 @@ +/* + * Linker script for Sysam AMCORE board + * + * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text : + { + arch/m68k/cpu/mcf530x/start.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.sdata) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss*) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig index 0e4cd69a2d..738dc80551 100644 --- a/board/tqc/tqm5200/Kconfig +++ b/board/tqc/tqm5200/Kconfig @@ -1,16 +1,3 @@ -if TARGET_AEV - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "aev" - -endif - if TARGET_CHARON config SYS_BOARD @@ -24,19 +11,6 @@ config SYS_CONFIG_NAME endif -if TARGET_TB5200 - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TB5200" - -endif - if TARGET_TQM5200 config SYS_BOARD diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS index d3eb543140..12d143d73f 100644 --- a/board/tqc/tqm5200/MAINTAINERS +++ b/board/tqc/tqm5200/MAINTAINERS @@ -9,9 +9,6 @@ F: configs/cam5200_defconfig F: configs/cam5200_niosflash_defconfig F: configs/fo300_defconfig F: configs/MiniFAP_defconfig -F: include/configs/TB5200.h -F: configs/TB5200_defconfig -F: configs/TB5200_B_defconfig F: configs/TQM5200_defconfig F: configs/TQM5200_B_defconfig F: configs/TQM5200_B_HIGHBOOT_defconfig diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index 80c1eba87c..f7c97b72c8 100644 --- a/board/tqc/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o +obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c deleted file mode 100644 index 876258d8f7..0000000000 --- a/board/tqc/tqm5200/cmd_tb5200.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 - 2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * TB5200 specific functions - */ -/*#define DEBUG*/ - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_CMD_BSP) -#if defined (CONFIG_TB5200) - -#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL - -static void led_init(void) -{ - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - /* configure timer 4 for simple GPIO output */ - gpt->gpt4.emsr |= 0x00000024; -} - -int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - led_init(); - - if (strcmp (argv[1], "on") == 0) { - debug ("switch status LED on\n"); - gpt->gpt4.emsr |= (1 << 4); - } else if (strcmp (argv[1], "off") == 0) { - debug ("switch status LED off\n"); - gpt->gpt4.emsr &= ~(1 << 4); - } else { - printf ("Usage:\nled on/off\n"); - return 1; - } - - return 0; -} - -static void sm501_backlight (unsigned int state) -{ - if (state == 1) { - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= - (1 << 26) | (1 << 27); - } else if (state == 0) - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= - ~((1 << 26) | (1 << 27)); -} - -int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp (argv[1], "on") == 0) { - debug ("switch backlight on\n"); - sm501_backlight (1); - } else if (strcmp (argv[1], "off") == 0) { - debug ("switch backlight off\n"); - sm501_backlight (0); - } else { - printf ("Usage:\nbacklight on/off\n"); - return 1; - } - - return 0; -} - -U_BOOT_CMD( - led , 2, 1, cmd_led, - "switch status LED on or off", - "on/off" -); - -U_BOOT_CMD( - backlight , 2, 1, cmd_backlight, - "switch backlight on or off", - "on/off" - ); - -#endif /* CONFIG_STK52XX */ -#endif diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index e9363ea394..4d4f29da74 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -258,11 +258,6 @@ phys_size_t initdram (int board_type) int checkboard (void) { -#if defined(CONFIG_AEVFIFO) - puts ("Board: AEVFIFO\n"); - return 0; -#endif - #if defined(CONFIG_TQM5200S) # define MODULE_NAME "TQM5200S" #else @@ -271,8 +266,6 @@ int checkboard (void) #if defined(CONFIG_STK52XX) # define CARRIER_NAME "STK52xx" -#elif defined(CONFIG_TB5200) -# define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) # define CARRIER_NAME "CAM5200" #elif defined(CONFIG_FO300) @@ -762,7 +755,7 @@ void video_get_info_str (int line_number, char *info) if (line_number == 1) { strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \ - defined(CONFIG_STK52XX) || defined(CONFIG_TB5200) + defined(CONFIG_STK52XX) } else if (line_number == 2) { #if defined (CONFIG_CHARON) strcpy (info, " on a CHARON carrier board"); @@ -770,9 +763,6 @@ void video_get_info_str (int line_number, char *info) #if defined (CONFIG_STK52XX) strcpy (info, " on a STK52xx carrier board"); #endif -#if defined (CONFIG_TB5200) - strcpy (info, " on a TB5200 carrier board"); -#endif #if defined (CONFIG_FO300) strcpy (info, " on a FO300 carrier board"); #endif diff --git a/board/w7o/Kconfig b/board/w7o/Kconfig deleted file mode 100644 index fd1b422318..0000000000 --- a/board/w7o/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_W7OLMC - -config SYS_BOARD - default "w7o" - -config SYS_CONFIG_NAME - default "W7OLMC" - -endif - -if TARGET_W7OLMG - -config SYS_BOARD - default "w7o" - -config SYS_CONFIG_NAME - default "W7OLMG" - -endif diff --git a/board/w7o/MAINTAINERS b/board/w7o/MAINTAINERS deleted file mode 100644 index bfedee5748..0000000000 --- a/board/w7o/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -W7O BOARD -M: Erik Theisen <etheisen@mindspring.com> -S: Maintained -F: board/w7o/ -F: include/configs/W7OLMC.h -F: configs/W7OLMC_defconfig -F: include/configs/W7OLMG.h -F: configs/W7OLMG_defconfig diff --git a/board/w7o/Makefile b/board/w7o/Makefile deleted file mode 100644 index 955de50e4f..0000000000 --- a/board/w7o/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ - watchdog.o -obj-y += init.o post1.o diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c deleted file mode 100644 index 879cb6133c..0000000000 --- a/board/w7o/cmd_vpd.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_CMD_BSP) - -#include "vpd.h" - -/* ====================================================================== - * Interpreter command to retrieve board specific Vital Product Data, "VPD" - * ====================================================================== - */ -int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - VPD vpd; /* Board specific data struct */ - uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR; - - /* Validate usage */ - if (argc > 2) - return cmd_usage(cmdtp); - - /* Passed in EEPROM address */ - if (argc == 2) - dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16); - - /* Read VPD and output it */ - if (!vpd_get_data (dev_addr, &vpd)) { - vpd_print (&vpd); - return 0; - } - - return 1; -} - -U_BOOT_CMD( - vpd, 2, 1, do_vpd, - "Read Vital Product Data", - "[dev_addr]\n" - " - Read VPD Data from default address, or device address 'dev_addr'." -); - -#endif diff --git a/board/w7o/errors.h b/board/w7o/errors.h deleted file mode 100644 index 05540fb2d2..0000000000 --- a/board/w7o/errors.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ERRORS_H_ -#define _ERRORS_H_ - -#define ERR_FF -1 /* led test value(2) */ -#define ERR_00 0x0000 /* led test value(2) */ -#define ERR_LED 0x01 /* led test failed (1)(3)(4) */ -#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */ -#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */ -#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */ -#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */ -#define ERR_ADDG 0x08 /* start Address ghosting test (13) */ -#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */ -#define ERR_POST1 0x0a /* post1 tests complete */ -#define ERR_TMP1 0x0b /* */ -#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */ -#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */ -#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */ -#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */ -#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */ -#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */ -#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */ -#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */ -#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */ -#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */ -#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */ -#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */ -#define ERR_RTCG 0x18 /* start RTC test */ -#define ERR_RTCBAT 0x19 /* RTC battery failure */ -#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */ -#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */ -#define ERR_FPGAG 0x20 /* fault during FPGA programming */ -#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */ -#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */ -#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */ -#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */ -#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */ -#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */ -#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */ -#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */ -#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */ -#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */ -#define ERR_TempG 0x2b /* start temp sensor tests */ -#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */ -#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */ -#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */ -#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */ -#define ERR_lm75r 0x30 /* temp sensor read failure */ -#define ERR_lm75w 0x31 /* temp sensor write failure */ - - -#define ERR_POSTOK 0x55 /* PANIC: psych... OK */ - -#if !defined(__ASSEMBLY__) -extern void log_stat(int errcode); -extern void log_warn(int errcode); -extern void log_err(int errcode); -#endif - -/* -Debugging suggestions: -(1) periferal data bus shorted or crossed -(2) general processor halt, check reset, watch dog, power supply ripple, processor clock. -(3) check p_we, p_r/w, p_oe, p_rdy lines. -(4) check LED buffers -(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip. -(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip. -(7) check SDRAM control lines and clocks -(8) check decoupling caps, replace LSW SDRAM -(9) check decoupling caps, replace MSW SDRAM -(10) -(11) -(12) -(13) SDRAM address shorted or unconnected, check sdram caps -*/ -#endif /* _ERRORS_H_ */ diff --git a/board/w7o/flash.c b/board/w7o/flash.c deleted file mode 100644 index 26bddc4235..0000000000 --- a/board/w7o/flash.c +++ /dev/null @@ -1,927 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#include <watchdog.h> - -/* info for FLASH chips */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word8(flash_info_t *info, ulong dest, ulong data); -static int write_word32(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -unsigned long flash_init(void) -{ - int i; - unsigned long size_b0, base_b0; - unsigned long size_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Get Size of Boot and Main Flashes */ - size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - return 0; - } - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size_b1, size_b1 << 20); - return 0; - } - - /* Calculate base addresses */ - base_b0 = -size_b0; - - /* Setup offsets for Boot Flash */ - flash_get_offsets(base_b0, &flash_info[0]); - - /* Protect board level data */ - (void) flash_protect(FLAG_PROTECT_SET, - base_b0, - flash_info[0].start[1] - 1, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - /* Protect the FPGA image */ - (void) flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM, - FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN - - 1, &flash_info[1]); - - /* Protect the default boot image */ - (void) flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN, - FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN + - 0x600000 - 1, &flash_info[1]); - - /* Setup offsets for Main Flash */ - flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); - - return size_b0 + size_b1; -} - -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table - FOR BOOT ROM ONLY!!! */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} /* end flash_get_offsets() */ - -void flash_print_info(flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("1 x AMD "); - break; - case FLASH_MAN_STM: - printf("1 x STM "); - break; - case FLASH_MAN_INTEL: - printf("2 x Intel "); - break; - default: - printf("Unknown Vendor "); - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - printf("AM29LV040 (4096 Kbit, uniform sector size)\n"); - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) - printf("M29W040B (4096 Kbit, uniform block size)\n"); - else - printf("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n"); - break; - case FLASH_28F320J3A: - printf("28F320J3A (32 Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: - printf("28F640J3A (64 Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: - printf("28F128J3A (128 Mbit = 128K x 128)\n"); - break; - default: - printf("Unknown Chip Type\n"); - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) { - printf(" Size: %ld KB in %d Blocks\n", - info->size >> 10, info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - } - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf("\n"); -} /* end flash_print_info() */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong) addr; - - /* Setup default type */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - - /* Test for Boot Flash */ - if (base == FLASH_BASE0_PRELIM) { - unsigned char value; - volatile unsigned char *addr2 = (unsigned char *) addr; - - /* Write auto select command: read Manufacturer ID */ - *(addr2 + 0x555) = 0xaa; - *(addr2 + 0x2aa) = 0x55; - *(addr2 + 0x555) = 0x90; - - /* Manufacture ID */ - value = *addr2; - switch (value) { - case (unsigned char) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (unsigned char) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - *addr2 = 0xf0; /* no or unknown flash */ - return 0; - } - - /* Device ID */ - value = *(addr2 + 1); - switch (value) { - case (unsigned char) AMD_ID_LV040B: - case (unsigned char) STM_ID_29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - default: - *addr2 = 0xf0; /* => no or unknown flash */ - return 0; - } - } else { /* MAIN Flash */ - unsigned long value; - volatile unsigned long *addr2 = (unsigned long *) addr; - - /* Write auto select command: read Manufacturer ID */ - *addr2 = 0x90909090; - - /* Manufacture ID */ - value = *addr2; - switch (value) { - case (unsigned long) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - *addr2 = 0xff; /* no or unknown flash */ - return 0; - } - - /* Device ID - This shit is interleaved... */ - value = *(addr2 + 1); - switch (value) { - case (unsigned long) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * 2; - break; /* => 2 X 4 MB */ - case (unsigned long) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000 * 2; - break; /* => 2 X 8 MB */ - case (unsigned long) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * 2; - break; /* => 2 X 16 MB */ - default: - *addr2 = 0xff; /* => no or unknown flash */ - } - } - - /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */ - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - /* set up sector start address table */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - break; - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + - (i * 0x00020000 * 2); /* 2 Banks */ - break; - } - - /* Test for Boot Flash */ - if (base == FLASH_BASE0_PRELIM) { - volatile unsigned char *addr2; - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (AX .. A0) = 0x02 - * D0 = 1 if protected - */ - addr2 = (volatile unsigned char *) (info->start[i]); - info->protect[i] = *(addr2 + 2) & 1; - } - - /* Restore read mode */ - *(unsigned char *) base = 0xF0; /* Reset NORMAL Flash */ - } else { /* Main Flash */ - volatile unsigned long *addr2; - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (AX .. A0) = 0x02 - * D0 = 1 if protected - */ - addr2 = (volatile unsigned long *) (info->start[i]); - info->protect[i] = *(addr2 + 2) & 0x1; - } - - /* Restore read mode */ - *(unsigned long *) base = 0xFFFFFFFF; /* Reset Flash */ - } - - return info->size; -} /* end flash_get_size() */ - -static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout) -{ - int i; - - volatile uchar *vaddr = (uchar *) addr; - - /* Loop X times */ - for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */ - udelay(10); - /* Pause 10 us */ - - /* Check for completion */ - if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) - return 0; - - /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */ - if (!(i % 110000)) - putc('.'); - - /* Kick the dog if needed */ - WATCHDOG_RESET(); - } - - return 1; -} /* wait_for_DQ7() */ - -static int flash_erase8(flash_info_t *info, int s_first, int s_last) -{ - int tcode, rcode = 0; - volatile uchar *addr = (uchar *) (info->start[0]); - volatile uchar *sector_addr; - int flag, prot, sect; - - /* Validate arguments */ - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - /* Check for KNOWN flash type */ - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - /* Check for protected sectors */ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - sector_addr = (uchar *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_STM) - printf("Erasing block %p\n", sector_addr); - else - printf("Erasing sector %p\n", sector_addr); - - /* Disable interrupts which might cause timeout */ - flag = disable_interrupts(); - - *(addr + 0x555) = (uchar) 0xAA; - *(addr + 0x2aa) = (uchar) 0x55; - *(addr + 0x555) = (uchar) 0x80; - *(addr + 0x555) = (uchar) 0xAA; - *(addr + 0x2aa) = (uchar) 0x55; - *sector_addr = (uchar) 0x30; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - * Takes up to 6 seconds. - */ - tcode = wait_for_DQ7((ulong) sector_addr, 0x80, 6000); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Make sure we didn't timeout */ - if (tcode) { - printf("Timeout\n"); - rcode = 1; - } - } - } - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (uchar *) info->start[0]; - *addr = (uchar) 0xF0; /* reset bank */ - - printf(" done\n"); - return rcode; -} /* end flash_erase8() */ - -static int flash_erase32(flash_info_t *info, int s_first, int s_last) -{ - int flag, sect; - ulong start, now, last; - int prot = 0; - - /* Validate arguments */ - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - /* Check for KNOWN flash type */ - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf("Can erase only Intel flash types - aborted\n"); - return 1; - } - - /* Check for protected sectors */ - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - WATCHDOG_RESET(); - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout */ - flag = disable_interrupts(); - - *addr = 0x00500050; /* clear status register */ - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Wait at least 80us - let's wait 1 ms */ - udelay(1000); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - /* suspend erase */ - *addr = 0x00B000B0; - /* reset to read mode */ - *addr = 0x00FF00FF; - return 1; - } - - /* - * show that we're waiting - * every second (?) - */ - if ((now - last) > 990) { - putc('.'); - last = now; - } - } - *addr = 0x00FF00FF; /* reset to read mode */ - } - } - printf(" done\n"); - return 0; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) - return flash_erase8(info, s_first, s_last); - else - return flash_erase32(info, s_first, s_last); -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_buff8(flash_info_t *info, uchar *src, ulong addr, - ulong cnt) -{ - ulong cp, wp, data; - ulong start; - int i, l, rc; - - start = get_timer(0); - - wp = (addr & ~3); /* get lower word - aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - rc = write_word8(info, wp, data); - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word8(info, wp, data); - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - if (get_timer(start) > 1000) { /* every second */ - WATCHDOG_RESET(); - putc('.'); - start = get_timer(0); - } - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return write_word8(info, wp, data); -} - -#define FLASH_WIDTH 4 /* flash bus width in bytes */ -static int write_buff32(flash_info_t *info, uchar *src, ulong addr, - ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong start; - - start = get_timer(0); - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - /* get lower FLASH_WIDTH aligned address */ - wp = (addr & ~(FLASH_WIDTH - 1)); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - rc = write_word32(info, wp, data); - if (rc != 0) - return rc; - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i = 0; i < FLASH_WIDTH; ++i) - data = (data << 8) | *src++; - - rc = write_word32(info, wp, data); - if (rc != 0) - return rc; - - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - if (get_timer(start) > 990) { /* every second */ - putc('.'); - start = get_timer(0); - } - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return write_word32(info, wp, data); -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int retval; - - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) - retval = write_buff8(info, src, addr, cnt); - else - retval = write_buff32(info, src, addr, cnt); - - return retval; -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -static int write_word8(flash_info_t *info, ulong dest, ulong data) -{ - volatile uchar *addr2 = (uchar *) (info->start[0]); - volatile uchar *dest2 = (uchar *) dest; - volatile uchar *data2 = (uchar *) &data; - int flag; - int i, tcode, rcode = 0; - - /* Check if Flash is (sufficently) erased */ - if ((*((volatile uchar *)dest) & (uchar)data) != (uchar)data) - return 2; - - for (i = 0; i < (4 / sizeof(uchar)); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *(addr2 + 0x555) = (uchar) 0xAA; - *(addr2 + 0x2aa) = (uchar) 0x55; - *(addr2 + 0x555) = (uchar) 0xA0; - - dest2[i] = data2[i]; - - /* Wait for write to complete, up to 1ms */ - tcode = wait_for_DQ7((ulong) &dest2[i], data2[i], 1); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Make sure we didn't timeout */ - if (tcode) - rcode = 1; - } - - return rcode; -} - -static int write_word32(flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - WATCHDOG_RESET(); - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x00FF00FF; /* restore read mode */ - return 1; - } - } - - *addr = 0x00FF00FF; /* restore read mode */ - - return 0; -} - -static int _flash_protect(flash_info_t *info, long sector) -{ - int i; - int flag; - ulong status; - int rcode = 0; - volatile long *addr = (long *)sector; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - /* Disable interrupts which might cause Flash to timeout */ - flag = disable_interrupts(); - - /* Issue command */ - *addr = 0x00500050L; /* Clear the status register */ - *addr = 0x00600060L; /* Set lock bit setup */ - *addr = 0x00010001L; /* Set lock bit confirm */ - - /* Wait for command completion */ - for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */ - udelay(10); - if ((*addr & 0x00800080L) == 0x00800080L) - break; - } - - /* Not successful? */ - status = *addr; - if (status != 0x00800080L) { - printf("Protect %x sector failed: %x\n", - (uint) sector, (uint) status); - rcode = 1; - } - - /* Restore read mode */ - *addr = 0x00ff00ffL; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - break; - case FLASH_AM040: /* No soft sector protection */ - break; - } - - /* Turn protection on for this sector */ - for (i = 0; i < info->sector_count; i++) { - if (info->start[i] == sector) { - info->protect[i] = 1; - break; - } - } - - return rcode; -} - -static int _flash_unprotect(flash_info_t *info, long sector) -{ - int i; - int flag; - ulong status; - int rcode = 0; - volatile long *addr = (long *) sector; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - /* Disable interrupts which might cause Flash to timeout */ - flag = disable_interrupts(); - - *addr = 0x00500050L; /* Clear the status register */ - *addr = 0x00600060L; /* Clear lock bit setup */ - *addr = 0x00D000D0L; /* Clear lock bit confirm */ - - /* Wait for command completion */ - for (i = 0; i < 80; i++) { /* 700ms timeout, wait 800 */ - udelay(10000); /* Delay 10ms */ - if ((*addr & 0x00800080L) == 0x00800080L) - break; - } - - /* Not successful? */ - status = *addr; - if (status != 0x00800080L) { - printf("Un-protect %x sector failed: %x\n", - (uint) sector, (uint) status); - *addr = 0x00ff00ffL; - rcode = 1; - } - - /* restore read mode */ - *addr = 0x00ff00ffL; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - break; - case FLASH_AM040: /* No soft sector protection */ - break; - } - - /* - * Fix Intel's little red wagon. Reprotect - * sectors that were protected before we undid - * protection on a specific sector. - */ - for (i = 0; i < info->sector_count; i++) { - if (info->start[i] != sector) { - if (info->protect[i]) { - if (_flash_protect(info, info->start[i])) - rcode = 1; - } - } else /* Turn protection off for this sector */ - info->protect[i] = 0; - } - - return rcode; -} - -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int rcode; - - if (prot) - rcode = _flash_protect(info, info->start[sector]); - else - rcode = _flash_unprotect(info, info->start[sector]); - - return rcode; -} diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c deleted file mode 100644 index a27e8ab88f..0000000000 --- a/board/w7o/fpga.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * and - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <common.h> -#include "w7o.h" -#include <asm/processor.h> -#include <linux/compiler.h> -#include "errors.h" - -static void -fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr) -{ - unsigned long i; - volatile unsigned long val; - volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */ - - for (i = 0; i < len; i++, src++) { - val = *src; - *dest = (unsigned short) ((val & 0xff000000L) >> 16); - *dest = (unsigned short) ((val & 0x00ff0000L) >> 8); - *dest = (unsigned short) (val & 0x0000ff00L); - *dest = (unsigned short) ((val & 0x000000ffL) << 8); - } - - /* Terminate programming with 4 C clocks */ - dest = daddr; - val = *(unsigned short *) dest; - val = *(unsigned short *) dest; - val = *(unsigned short *) dest; - val = *(unsigned short *) dest; - -} - - -int -fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr) -{ - int i; /* index, intr disable flag */ - int start; /* timer */ - unsigned long greg, grego; /* GPIO & output register */ - unsigned long length; /* image size in words */ - unsigned long *source; /* image source addr */ - unsigned short *dest; /* destination FPGA addr */ - volatile unsigned short *ndest; /* temp dest FPGA addr */ - unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */ - unsigned long eirq = GPIO_XCV_IRQ; - int retval = -1; /* Function return value */ - __maybe_unused volatile unsigned short val; /* temp val */ - - /* Setup some basic values */ - length = (size / 4) + 1; /* size in words, rounding UP - is OK */ - source = (unsigned long *) saddr; - dest = (unsigned short *) daddr; - - /* Get DCR output register */ - grego = in32(PPC405GP_GPIO0_OR); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Setup timeout timer */ - start = get_timer(0); - - /* Wait for FPGA init line to go low */ - while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { - /* Check for timeout - 100us max, so use 3ms */ - if (get_timer(start) > 3) { - printf(" failed to start init.\n"); - log_warn(ERR_XINIT0); /* Don't halt */ - - /* Reset line stays low */ - goto done; /* I like gotos... */ - } - } - - /* Unreset FPGA */ - grego |= GPIO_XCV_PROG; /* PROG line high */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Wait for FPGA end of init period = init line go hi */ - while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { - - /* Check for timeout */ - if (get_timer(start) > 3) { - printf(" failed to exit init.\n"); - log_warn(ERR_XINIT1); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - goto done; - } - } - - /* Now program FPGA ... */ - ndest = dest; - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { - /* Toggle IRQ/GPIO */ - greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ - greg |= eirq; /* toggle irq/gpio */ - mtdcr(CPC0_CR0, greg); /* ... just do it */ - - /* turn on open drain for CNFG */ - greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */ - greg |= cnfg; /* CNFG open drain */ - out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */ - - /* Turn output enable on for CNFG */ - greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ - greg |= cnfg; /* CNFG tristate inactive */ - out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ - - /* Setup FPGA for programming */ - grego &= ~cnfg; /* CONFIG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - /* - * Program the FPGA - */ - printf("\n destination: 0x%lx ", (unsigned long) ndest); - - fpga_img_write(source, length, (unsigned short *) ndest); - - /* Done programming */ - grego |= cnfg; /* CONFIG line high */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Turn output enable OFF for CNFG */ - greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ - greg &= ~cnfg; /* CNFG tristate inactive */ - out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ - - /* Toggle IRQ/GPIO */ - greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ - greg &= ~eirq; /* toggle irq/gpio */ - mtdcr(CPC0_CR0, greg); /* ... just do it */ - - /* XXX - Next FPGA addr */ - ndest = (unsigned short *) ((char *) ndest + 0x00100000L); - cnfg >>= 1; /* XXX - Next */ - eirq >>= 1; - } - - /* Terminate programming with 4 C clocks */ - ndest = dest; - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { - val = *ndest; - val = *ndest; - val = *ndest; - val = *ndest; - ndest = (unsigned short *) ((char *) ndest + 0x00100000L); - } - - /* Setup timer */ - start = get_timer(0); - - /* Wait for FPGA end of programming period = Test DONE low */ - while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { - - /* Check for timeout */ - if (get_timer(start) > 3) { - printf(" done failed to come high.\n"); - log_warn(ERR_XDONE1); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - goto done; - } - } - - printf("\n FPGA load succeeded\n"); - retval = 0; /* Program OK */ - -done: - return retval; -} - -/* FPGA image is stored in flash */ -extern flash_info_t flash_info[]; - -int init_fpga(void) -{ - unsigned int i, j, ptr; /* General purpose */ - unsigned char bufchar; /* General purpose character */ - unsigned char *buf; /* Start of image pointer */ - unsigned long len; /* Length of image */ - unsigned char *fn_buf; /* Start of filename string */ - unsigned int fn_len; /* Length of filename string */ - unsigned char *xcv_buf; /* Pointer to start of image */ - unsigned long xcv_len; /* Length of image */ - unsigned long crc; /* 30bit crc in image */ - unsigned long calc_crc; /* Calc'd 30bit crc */ - int retval = -1; - - /* Tell the world what we are doing */ - printf("FPGA: "); - - /* - * Get address of first sector where the FPGA - * image is stored. - */ - buf = (unsigned char *) flash_info[1].start[0]; - - /* - * Get the stored image's CRC & length. - */ - crc = *(unsigned long *) (buf + 4); /* CRC is first long word */ - len = *(unsigned long *) (buf + 8); /* Image len is next long */ - - /* Pedantic */ - if ((len < 0x133A4) || (len > 0x80000)) - goto bad_image; - - /* - * Get the file name pointer and length. - * filename length is next short - */ - fn_len = (*(unsigned short *) (buf + 12) & 0xff); - fn_buf = buf + 14; - - /* - * Get the FPGA image pointer and length length. - */ - xcv_buf = fn_buf + fn_len; /* pointer to fpga image */ - xcv_len = len - 14 - fn_len; /* fpga image length */ - - /* Check for uninitialized FLASH */ - if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL) - || (len == 0)) - goto bad_image; - - /* - * Calculate and Check the image's CRC. - */ - calc_crc = crc32(0, xcv_buf, xcv_len); - if (crc != calc_crc) { - printf("\nfailed - bad CRC\n"); - goto done; - } - - /* Output the file name */ - printf("file name : "); - for (i = 0; i < fn_len; i++) { - bufchar = fn_buf[+i]; - if (bufchar < ' ' || bufchar > '~') - bufchar = '.'; - putc(bufchar); - } - - /* - * find rest of display data - */ - ptr = 15; /* Offset to ncd filename - length in fpga image */ - j = xcv_buf[ptr]; /* Get len of ncd filename */ - if (j > 32) - goto bad_image; - ptr = ptr + j + 3; /* skip ncd filename string + - 3 bytes more bytes */ - - /* - * output target device string - */ - j = xcv_buf[ptr++] - 1; /* len of targ str less term */ - if (j > 32) - goto bad_image; - printf("\n target : "); - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar < ' ' || bufchar > '~') - bufchar = '.'; - putc(bufchar); - } - - /* - * output compilation date string and time string - */ - ptr += 3; /* skip 2 bytes */ - printf("\n synth time : "); - j = (xcv_buf[ptr++] - 1); /* len of date str less term */ - if (j > 32) - goto bad_image; - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar < ' ' || bufchar > '~') - bufchar = '.'; - putc(bufchar); - } - - ptr += 3; /* Skip 2 bytes */ - printf(" - "); - j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */ - if (j > 32) - goto bad_image; - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar < ' ' || bufchar > '~') - bufchar = '.'; - putc(bufchar); - } - - /* - * output crc and length strings - */ - printf("\n len & crc : 0x%lx 0x%lx", len, crc); - - /* - * Program the FPGA. - */ - retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len, - (unsigned short *) 0xfd000000L); - return retval; - -bad_image: - printf("\n BAD FPGA image format @ %lx\n", - flash_info[1].start[0]); - log_warn(ERR_XIMAGE); -done: - return retval; -} - -void test_fpga(unsigned short *daddr) -{ - int i; - volatile unsigned short *ndest = daddr; - - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { -#if defined(CONFIG_W7OLMG) - ndest[0x7e] = 0x55aa; - if (ndest[0x7e] != 0x55aa) - log_warn(ERR_XRW1 + i); - ndest[0x7e] = 0xaa55; - if (ndest[0x7e] != 0xaa55) - log_warn(ERR_XRW1 + i); - ndest[0x7e] = 0xc318; - if (ndest[0x7e] != 0xc318) - log_warn(ERR_XRW1 + i); - -#elif defined(CONFIG_W7OLMC) - ndest[0x800] = 0x55aa; - ndest[0x801] = 0xaa55; - ndest[0x802] = 0xc318; - ndest[0x4800] = 0x55aa; - ndest[0x4801] = 0xaa55; - ndest[0x4802] = 0xc318; - if ((ndest[0x800] != 0x55aa) || - (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318)) - log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */ - if ((ndest[0x4800] != 0x55aa) || - (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318)) - log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */ - -#else -#error "Unknown W7O board configuration" -#endif - } - - printf(" FPGA ready\n"); - return; -} diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c deleted file mode 100644 index 8f4fe310d7..0000000000 --- a/board/w7o/fsboot.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Wave 7 Optics, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <elf.h> - -/* - * FIXME: Add code to test image and it's header. - */ -static int -image_check(ulong addr) -{ - return valid_elf_image(addr); -} - -void -init_fsboot(void) -{ - char *envp; - ulong loadaddr; - ulong testaddr; - ulong alt_loadaddr; - char buf[9]; - - /* - * Get test image address - */ - if ((envp = getenv("testaddr")) != NULL) - testaddr = simple_strtoul(envp, NULL, 16); - else - testaddr = -1; - - /* - * Are we going to test boot and image? - */ - if ((testaddr != -1) && image_check(testaddr)) { - - /* Set alt_loadaddr */ - alt_loadaddr = testaddr; - sprintf(buf, "%lX", alt_loadaddr); - setenv("alt_loadaddr", buf); - - /* Clear test_addr */ - setenv("testaddr", NULL); - - /* - * Save current environment with alt_loadaddr, - * and cleared testaddr. - */ - saveenv(); - - /* - * Setup temporary loadaddr to alt_loadaddr - * XXX - DO NOT SAVE ENVIRONMENT! - */ - loadaddr = alt_loadaddr; - sprintf(buf, "%lX", loadaddr); - setenv("loadaddr", buf); - - } else { /* Normal boot */ - setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */ - setenv("testaddr", NULL); /* Clear testaddr */ - saveenv(); - } - - return; -} diff --git a/board/w7o/init.S b/board/w7o/init.S deleted file mode 100644 index dfde149956..0000000000 --- a/board/w7o/init.S +++ /dev/null @@ -1,244 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - addi r3, 0, EBC0_CFG - mtdcr EBC0_CFGADDR, r3 - addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ - ori r4, r4, 0x0 /* Drive CS with external master */ - mtdcr EBC0_CFGDATA, r4 - - /******************************************************************** - * Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, CPC0_CR1 - ori r4, r4, 0x4000 - mtdcr CPC0_CR1, r4 - - /******************************************************************** - * Memory Bank 0 (Flash Bank 0) initialization - *******************************************************************/ - addi r3, 0, PB1AP - mtdcr EBC0_CFGADDR, r3 - addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h - ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l - mtdcr EBC0_CFGDATA, r4 - - addi r3, 0, PB0CR - mtdcr EBC0_CFGADDR, r3 - addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h - ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l - mtdcr EBC0_CFGDATA, r4 - - /******************************************************************** - * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. - *******************************************************************/ - addi r3, 0, PB7AP - mtdcr EBC0_CFGADDR, r3 - addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h - ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l - mtdcr EBC0_CFGDATA, r4 - - addi r3, 0, PB7CR - mtdcr EBC0_CFGADDR, r3 - addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h - ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l - mtdcr EBC0_CFGDATA, r4 - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Serial Presence Detect, "SPD," reads the SDRAM EEPROM - * via the IIC bus and then configures the SDRAM memory - * banks appropriately. If Auto Memory Configuration is - * is not used, it is assumed that a 4MB 11x8x2, non-ECC, - * SDRAM is soldered down. - * - * Notes: Expects that the stack is already setup. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save link register */ - - /* - * First call spd_sdram to try to init SDRAM according to the - * contents of the SPD EEPROM. If the SPD EEPROM is blank or - * erronious, spd_sdram returns 0 in R3. - */ - li r3,0 - bl spd_sdram - addic. r3, r3, 0 /* Check for error, save dram size */ - bne ..sdri_done /* If it worked, we're done... */ - - /******************************************************************** - * If SPD detection fails, we'll default to 4MB, 11x8x2, as this - * is the SMALLEST SDRAM size the 405 supports. We can do this - * because W7O boards have soldered on RAM, and there will always - * be some amount present. If we were using DIMMs, we should hang - * the board instead, since it doesn't have any RAM to continue - * running with. - *******************************************************************/ - - /* - * Disable memory controller to allow - * values to be changed. - */ - addi r3, 0, SDRAM0_CFG - mtdcr SDRAM0_CFGADDR, r3 - addis r4, 0, 0x0 - ori r4, r4, 0x0 - mtdcr SDRAM0_CFGDATA, r4 - - /* - * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 - * All other banks are disabled. - */ - addi r3, 0, SDRAM0_B0CR - mtdcr SDRAM0_CFGADDR, r3 - addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ - ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ - mtdcr SDRAM0_CFGDATA, r4 - - /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ - addi r4, 0, 0 /* Zero the data reg */ - - addi r3, r3, 4 /* Point to MB1CF reg */ - mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ - mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ - - addi r3, r3, 4 /* Point to MB2CF reg */ - mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ - mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ - - addi r3, r3, 4 /* Point to MB3CF reg */ - mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ - mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ - - /******************************************************************** - * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. - * To set the appropriate timings, we assume sdram is - * 100MHz (pc100 compliant). - *******************************************************************/ - - /* - * Set up SDTR1 - */ - addi r3, 0, SDRAM0_TR - mtdcr SDRAM0_CFGADDR, r3 - addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ - ori r4, r4, 0x400D - mtdcr SDRAM0_CFGDATA, r4 - - /* - * Set RTR - */ - addi r3, 0, SDRAM0_RTR - mtdcr SDRAM0_CFGADDR, r3 - addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ - mtdcr SDRAM0_CFGDATA, r4 - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait 200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - addi r3, 0, SDRAM0_CFG - mtdcr SDRAM0_CFGADDR, r3 - addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ - ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ - mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */ - -..sdri_done: - /* restore and return */ - lwz r0, +12(r1) /* Get saved link register */ - addi r1, r1, +8 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/w7o/post1.S b/board/w7o/post1.S deleted file mode 100644 index aae5387212..0000000000 --- a/board/w7o/post1.S +++ /dev/null @@ -1,724 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * and - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Description: - * Routine to exercise memory for the bringing up of our boards. - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#include <watchdog.h> - -#include "errors.h" - -#define _ASMLANGUAGE - - .globl test_sdram - .globl test_led - .globl log_stat - .globl log_warn - .globl log_err - .globl temp_uart_init - .globl post_puts - .globl disp_hex - -/***************************************************** -******* Text Strings for low level printing ****** -******* In section got2 ******* -*****************************************************/ - -/* - * Define the text strings for errors and warnings. - * Switch to .data section. - */ - .section ".data" -err_str: .asciz "*** POST ERROR = " -warn_str: .asciz "*** POST WARNING = " -end_str: .asciz "\r\n" - -/* - * Enter the labels in Global Entry Table (GOT). - * Switch to .got2 section. - */ - START_GOT - GOT_ENTRY(err_str) - GOT_ENTRY(warn_str) - GOT_ENTRY(end_str) - END_GOT - -/* - * Switch back to .text section. - */ - .text - -/**************************************** - **************************************** - ******** LED register test ******** - **************************************** - ***************************************/ -test_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - WATCHDOG_RESET /* Reset the watchdog */ - - addi r3, 0, ERR_FF /* first test value is ffff */ - addi r4, r3, 0 /* save copy of pattern */ - bl set_led /* store first test value */ - bl get_led /* read it back */ - xor. r4, r4, r3 /* compare to original */ -#if defined(CONFIG_W7OLMC) - andi. r4, r4, 0x00ff /* lmc has 8 bits */ -#else - andi. r4, r4, 0xffff /* lmg has 16 bits */ -#endif - beq LED2 /* next test */ - addi r3, 0, ERR_LED /* error code = 1 */ - bl log_err /* display error and halt */ -LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */ - addi r4, r3, 0 /* save copy of pattern */ - bl set_led /* store first test value */ - bl get_led /* read it back */ - xor. r4, r4, r3 /* compare to original */ -#if defined(CONFIG_W7OLMC) - andi. r4, r4, 0x00ff /* lmc has 8 bits */ -#else - andi. r4, r4, 0xffff /* lmg has 16 bits */ -#endif - beq LED3 /* next test */ - addi r3, 0, ERR_LED /* error code = 1 */ - bl log_err /* display error and halt */ - -LED3: /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -/**************************************** - **************************************** - ******** SDRAM TESTS ******** - **************************************** - ***************************************/ -test_sdram: - /* called with mem size in r3 */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stmw r30, +8(r1) /* save R30,R31 */ - /* r30 is log2(mem size) */ - /* r31 is mem size */ - - /* take log2 of total mem size */ - addi r31, r3, 0 /* save total mem size */ - addi r30, 0, 0 /* clear r30 */ -l2_loop: - srwi. r31, r31, 1 /* shift right 1 */ - addi r30, r30, 1 /* count shifts */ - bne l2_loop /* loop till done */ - addi r30, r30, -1 /* correct for over count */ - addi r31, r3, 0 /* save original size */ - - /* now kick the dog and test the mem */ - WATCHDOG_RESET /* Reset the watchdog */ - bl Data_Buster /* test crossed/shorted data lines */ - addi r3, r30, 0 /* get log2(memsize) */ - addi r4, r31, 0 /* get memsize */ - bl Ghost_Buster /* test crossed/shorted addr lines */ - addi r3, r31, 0 /* get mem size */ - bl Bit_Buster /* check for bad internal bits */ - - /* restore stack and return */ - lmw r30, +8(r1) /* Restore r30, r31 */ - lwz r0, +20(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +16 /* Remove frame from stack */ - blr /* Return to calling function */ - - -/**************************************** - ******** sdram data bus test ******** - ***************************************/ -Data_Buster: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -24(r1) /* Save back chain and move SP */ - stw r0, +28(r1) /* Save link register */ - stmw r28, 8(r1) /* save r28 - r31 on stack */ - /* r31 i/o register */ - /* r30 sdram base address */ - /* r29 5555 syndrom */ - /* r28 aaaa syndrom */ - - /* set up led register for this test */ - addi r3, 0, ERR_RAMG /* set led code to 1 */ - bl log_stat /* store test value */ - /* now test the dram data bus */ - xor r30, r30, r30 /* load r30 with base addr of sdram */ - addis r31, 0, 0x5555 /* load r31 with test value */ - ori r31, r31, 0x5555 - stw r31,0(r30) /* sto the value */ - lwz r29,0(r30) /* read it back */ - xor r29,r31,r29 /* compare it to original */ - addis r31, 0, 0xaaaa /* load r31 with test value */ - ori r31, r31, 0xaaaa - stw r31,0(r30) /* sto the value */ - lwz r28,0(r30) /* read it back */ - xor r28,r31,r28 /* compare it to original */ - or r3,r28,r29 /* or together both error terms */ - /* - * Now that we have the error bits, - * we have to decide which part they are in. - */ - bl get_idx /* r5 is now index to error */ - addi r3, r3, ERR_RAMG - cmpwi r3, ERR_RAMG /* check for errors */ - beq db_done /* skip if no errors */ - bl log_err /* log the error */ - -db_done: - lmw r28, 8(r1) /* restore r28 - r31 from stack */ - lwz r0, +28(r1) /* Get saved link register */ - addi r1, r1, +24 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******** test for address ghosting in dram ******** - ***************************************************/ - -Ghost_Buster: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -36(r1) /* Save back chain and move SP */ - stw r0, +40(r1) /* Save link register */ - stmw r25, 8(r1) /* save r25 - r31 on stack */ - /* r31 = scratch register */ - /* r30 is main referance loop counter, - 0 to 23 */ - /* r29 is ghost loop count, 0 to 22 */ - /* r28 is referance address */ - /* r27 is ghost address */ - /* r26 is log2 (mem size) = - number of byte addr bits */ - /* r25 is mem size */ - - /* save the log2(mem size) and mem size */ - addi r26, r3, 0 /* r26 is number of byte addr bits */ - addi r25, r4, 0 /* r25 is mem size in bytes */ - - /* set the leds for address ghost test */ - addi r3, 0, ERR_ADDG - bl set_led - - /* first fill memory with zeros */ - srwi r31, r25, 2 /* convert bytes to longs */ - mtctr r31 /* setup byte counter */ - addi r28, 0, 0 /* start at address at 0 */ - addi r31, 0, 0 /* data value = 0 */ -clr_loop: - stw r31, 0(r28) /* Store zero value */ - addi r28, r28, 4 /* Increment to next word */ - andi. r27, r28, 0xffff /* check for 2^16 loops */ - bne clr_skip /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -clr_skip: - bdnz clr_loop /* Round and round... */ - - /* now do main test */ - addi r30, 0, 0 /* start referance counter at 0 */ -outside: - /* - * Calculate the referance address - * the referance address is calculated by setting the (r30-1) - * bit of the base address - * when r30=0, the referance address is the base address. - * thus the sequence 0,1,2,4,8,..,2^(n-1) - * setting the bit is done with the following shift functions. - */ - WATCHDOG_RESET /* Reset the watchdog */ - - addi r31, 0, 1 /* r31 = 1 */ - slw r28, r31, r30 /* set bit coresponding to loop cnt */ - srwi r28, r28, 1 /* then shift it right one so */ - /* we start at location 0 */ - /* fill referance address with Fs */ - addi r31, 0, 0x00ff /* r31 = one byte of set bits */ - stb r31,0(r28) /* save ff in referance address */ - - /* ghost (inner) loop, now check all posible ghosted addresses */ - addi r29, 0, 0 /* start ghosted loop counter at 0 */ -inside: - /* - * Calculate the ghost address by flipping one - * bit of referance address. This gives the - * sequence 1,2,4,8,...,2^(n-1) - */ - addi r31, 0, 1 /* r31 = 1 */ - slw r27, r31, r29 /* set bit coresponding to loop cnt */ - xor r27, r28, r27 /* ghost address = ref addr with - bit flipped*/ - - /* now check for ghosting */ - lbz r31,0(r27) /* get content of ghost addr */ - cmpwi r31, 0 /* compare read value to 0 */ - bne Casper /* we found a ghost! */ - - /* now close ghost ( inner ) loop */ - addi r29, r29, 1 /* increment inner loop counter */ - cmpw r29, r26 /* check for last inner loop */ - blt inside /* do more inner loops */ - - /* now close referance ( outer ) loop */ - addi r31, 0, 0 /* r31 = zero */ - stb r31, 0(28) /* zero out the altered address loc. */ - /* - * Increment and check for end, count is zero based. - * With the ble, this gives us one more loops than - * address bits for sequence 0,1,2,4,8,...2^(n-1) - */ - addi r30, r30, 1 /* increment outer loop counter */ - cmpw r30, r26 /* check for last inner loop */ - ble outside /* do more outer loops */ - - /* were done, lets go home */ - b gb_done -Casper: /* we found a ghost !! */ - addi r3, 0, ERR_ADDF /* get indexed error message */ - bl log_err /* log error led error code */ -gb_done: /* pack your bags, and go home */ - lmw r25, 8(r1) /* restore r25 - r31 from stack */ - lwz r0, +40(r1) /* Get saved link register */ - addi r1, r1, +36 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - -/**************************************************** - ******** SDRAM data fill tests ********** - ***************************************************/ -Bit_Buster: - /* called with mem size in r3 */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - stw r5, +12(r1) /* save r5 */ - - addis r5, r3, 0 /* save mem size */ - - /* Test 55555555 */ - addi r3, 0, ERR_R55G /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0x5555 - ori r4, r4, 0x5555 - bl fill_test - - /* Test aaaaaaaa */ - addi r3, 0, ERR_RAAG /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0xAAAA - ori r4, r4, 0xAAAA - bl fill_test - - /* Test 00000000 */ - addi r3, 0, ERR_R00G /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0 - ori r4, r4, 0 - bl fill_test - - /* restore stack and return */ - lwz r5, +12(r1) /* restore r4 */ - lwz r4, +8(r1) /* restore r4 */ - lwz r0, +20(r1) /* Get saved link register */ - addi r1, r1, +16 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******** fill test ******** - ***************************************************/ -/* tests memory by filling with value, and reading back */ -/* r5 = Size of memory in bytes */ -/* r4 = Value to write */ -/* r3 = Error code */ -fill_test: - mflr r0 /* Get link register */ - stwu r1, -32(r1) /* Save back chain and move SP */ - stw r0, +36(r1) /* Save link register */ - stmw r27, 8(r1) /* save r27 - r31 on stack */ - /* r31 - scratch register */ - /* r30 - memory address */ - mr r27, r3 - mr r28, r4 - mr r29, r5 - - WATCHDOG_RESET /* Reset the watchdog */ - - /* first fill memory with Value */ - srawi r31, r29, 2 /* convert bytes to longs */ - mtctr r31 /* setup counter */ - addi r30, 0, 0 /* Make r30 = addr 0 */ -ft_0: stw r28, 0(r30) /* Store value */ - addi r30, r30, 4 /* Increment to next word */ - andi. r31, r30, 0xffff /* check for 2^16 loops */ - bne ft_0a /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -ft_0a: bdnz ft_0 /* Round and round... */ - - WATCHDOG_RESET /* Reset the watchdog */ - - /* Now confirm Value is in memory */ - srawi r31, r29, 2 /* convert bytes to longs */ - mtctr r31 /* setup counter */ - addi r30, 0, 0 /* Make r30 = addr 0 */ -ft_1: lwz r31, 0(r30) /* get value from memory */ - xor. r31, r31, r28 /* Writen = Read ? */ - bne ft_err /* If bad, than halt */ - addi r30, r30, 4 /* Increment to next word */ - andi. r31, r30, 0xffff /* check for 2^16 loops*/ - bne ft_1a /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -ft_1a: bdnz ft_1 /* Round and round... */ - - WATCHDOG_RESET /* Reset the watchdog */ - - b fill_done /* restore and return */ - -ft_err: addi r29, r27, 0 /* save current led code */ - addi r27, r31, 0 /* get pattern in r27 */ - bl get_idx /* get index from r27 */ - add r27, r27, r29 /* add index to old led code */ - bl log_err /* output led err code, halt CPU */ - -fill_done: - lmw r27, 8(r1) /* restore r27 - r31 from stack */ - lwz r0, +36(r1) /* Get saved link register */ - addi r1, r1, +32 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******* get error index from r3 pattern ******** - ***************************************************/ -get_idx: /* r3 = (MSW(r3) !=0)*2 + - (LSW(r3) !=0) */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - andi. r4, r3, 0xffff /* check for lower bits */ - beq gi2 /* skip if no bits set */ - andis. r4, r3, 0xffff /* check for upper bits */ - beq gi3 /* skip if no bits set */ - addi r3, 0, 3 /* both upper and lower bits set */ - b gi_done -gi2: andis. r4, r3, 0xffff /* check for upper bits*/ - beq gi4 /* skip if no bits set */ - addi r3, 0, 2 /* only upper bits set */ - b gi_done -gi3: addi r3, 0, 1 /* only lower bits set */ - b gi_done -gi4: addi r3, 0, 0 /* no bits set */ -gi_done: - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -/**************************************************** - ******** set LED to R5 and hang ******** - ***************************************************/ -log_stat: /* output a led code and continue */ -set_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ -#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */ - xori r3,r3, 0xffff /* complement led code, active low */ - sth r3, 0(r4) /* store first test value */ - xori r3,r3, 0xffff /* complement led code, active low */ -#else /* if not gateway, then don't invert */ - sth r3, 0(r4) /* store first test value */ -#endif - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -get_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ - lhz r3, 0(r4) /* store first test value */ -#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */ - xori r3,r3, 0xffff /* complement led code, active low */ -#endif - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -log_err: /* output the error and hang the board ( for now ) */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r3, +8(r1) /* save a copy of error code */ - bl set_led /* set the led pattern */ - GET_GOT /* get GOT address in r14 */ - lwz r3,GOT(err_str) /* get address of string */ - bl post_puts /* output the warning string */ - lwz r3, +8(r1) /* get error code */ - addi r4, 0, 2 /* set disp length to 2 nibbles */ - bl disp_hex /* output the error code */ - lwz r3,GOT(end_str) /* get address of string */ - bl post_puts /* output the warning string */ -halt: - b halt /* hang */ - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -log_warn: /* output a warning, then continue with operations */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stw r3, +8(r1) /* save a copy of error code */ - stw r14, +12(r1) /* save a copy of r14 (used by GOT) */ - - bl set_led /* set the led pattern */ - GET_GOT /* get GOT address in r14 */ - lwz r3,GOT(warn_str) /* get address of string */ - bl post_puts /* output the warning string */ - lwz r3, +8(r1) /* get error code */ - addi r4, 0, 2 /* set disp length to 2 nibbles */ - bl disp_hex /* output the error code */ - lwz r3,GOT(end_str) /* get address of string */ - bl post_puts /* output the warning string */ - - addis r3, 0, 64 /* has a long delay */ - mtctr r3 -log_2: - WATCHDOG_RESET /* this keeps dog from barking, */ - /* and takes time */ - bdnz log_2 /* loop till time expires */ - - /* restore stack and return */ - lwz r0, +20(r1) /* Get saved link register */ - lwz r14, +12(r1) /* restore r14 */ - mtlr r0 /* Restore link register */ - addi r1, r1, +16 /* Remove frame from stack */ - blr /* Return to calling function */ - -/******************************************************************* - * temp_uart_init - * Temporary UART initialization routine - * Sets up UART0 to run at 9600N81 off of the internal clock. - * R3-R4 are used. - ******************************************************************/ -temp_uart_init: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save link register */ - - addis r3, 0, 0xef60 - ori r3, r3, 0x0303 /* r3 = UART0_LCR */ - addi r4, 0, 0x83 /* n81 format, divisor regs enabled */ - stb r4, 0(r3) - - /* set baud rate to use internal clock, - baud = (200e6/16)/31/42 = 9600 */ - - addis r3, 0, 0xef60 /* Address of baud divisor reg */ - ori r3, r3, 0x0300 /* UART0_DLM */ - addi r4, 0, +42 /* uart baud divisor LSB = 93 */ - stb r4, 0(r3) /* baud = (200 /16)/14/93 */ - - addi r3, r3, 0x0001 /* uart baud divisor addr */ - addi r4, 0, 0 - stb r4, 0(r3) /* Divisor Latch MSB = 0 */ - - addis r3, 0, 0xef60 - ori r3, r3, 0x0303 /* r3 = UART0_LCR */ - addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */ - stb r4, 0(r3) - - /* output a few line feeds */ - addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ - addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ - - /* restore stack and return */ - lwz r0, +12(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +8 /* Remove frame from stack */ - blr /* Return to calling function */ - -/********************************************************************** - ** post_putc - ** outputs charactor in R3 - ** r3 returns the error code ( -1 if there is an error ) - *********************************************************************/ - -post_putc: - - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -20(r1) /* Save back chain and move SP */ - stw r0, +24(r1) /* Save link register */ - stmw r29, 8(r1) /* save r29 - r31 on stack - r31 - uart base address - r30 - delay counter - r29 - scratch reg */ - - addis r31, 0, 0xef60 /* Point to uart base */ - ori r31, r31, 0x0300 - addis r30, 0, 152 /* Load about 10,000,000 ticks. */ -pputc_lp: - lbz r29, 5(r31) /* Read Line Status Register */ - andi. r29, r29, 0x20 /* Check THRE status */ - bne thre_set /* Branch if FIFO empty */ - addic. r30, r30, -1 /* Decrement and check if empty. */ - bne pputc_lp /* Try, try again */ - addi r3, 0, -1 /* Load error code for timeout */ - b pputc_done /* Bail out with error code set */ -thre_set: - stb r3, 0(r31) /* Store character to UART */ - addi r3, 0, 0 /* clear error code */ -pputc_done: - lmw r29, 8(r1) /*restore r29 - r31 from stack */ - lwz r0, +24(r1) /* Get saved link register */ - addi r1, r1, +20 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************************** - post_puts - Accepts a null-terminated string pointed to by R3 - Outputs to the serial port until 0x00 is found. - r3 returns the error code ( -1 if there is an error ) -*****************************************************************/ -post_puts: - - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r31, 8(r1) /* save r31 - char pointer */ - - addi r31, r3, 0 /* move pointer to R31 */ -pputs_nxt: - lbz r3, 0(r31) /* Get next character */ - addic. r3, r3, 0 /* Check for zero */ - beq pputs_term /* bail out if zero */ - bl post_putc /* output the char */ - addic. r3, r3, 0 /* check for error */ - bne pputs_err - addi r31, r31, 1 /* point to next char */ - b pputs_nxt /* loop till term */ -pputs_err: - addi r3, 0, -1 /* set error code */ - b pputs_end /* were outa here */ -pputs_term: - addi r3, 0, 1 /* set success code */ - /* restore stack and return */ -pputs_end: - lwz r31, 8(r1) /* restore r27 - r31 from stack */ - lwz r0, +16(r1) /* Get saved link register */ - addi r1, r1, +12 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/******************************************************************** - ***** disp_hex - ***** Routine to display a hex value from a register. - ***** R3 is value to display - ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word - ***** Returns -1 in R3 if there is an error ( ie serial port hangs ) - ***** Returns 0 in R3 if no error - *******************************************************************/ -disp_hex: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stmw r30, 8(r1) /* save r30 - r31 on stack */ - /* r31 output char */ - /* r30 uart base address */ - addi r30, 0, 8 /* Go through 8 nibbles. */ - addi r31, r3, 0 -pputh_nxt: - rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */ - andi. r3, r31, 0x0f /* Get nibble. */ - addi r3, r3, 0x30 /* Add zero's ASCII code. */ - cmpwi r3, 0x03a - blt pputh_out - addi r3, r3, 0x07 /* 0x27 for lower case. */ -pputh_out: - cmpw r30, r4 - bgt pputh_skip - bl post_putc - addic. r3, r3, 0 /* check for error */ - bne pputh_err -pputh_skip: - addic. r30, r30, -1 - bne pputh_nxt - xor r3, r3, r3 /* Clear error code */ - b pputh_done -pputh_err: - addi r3, 0, -1 /* set error code */ -pputh_done: - /* restore stack and return */ - lmw r30, 8(r1) /* restore r30 - r31 from stack */ - lwz r0, +20(r1) /* Get saved link register */ - addi r1, r1, +16 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c deleted file mode 100644 index 76b65975ce..0000000000 --- a/board/w7o/post2.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * and - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <rtc.h> -#include "errors.h" -#include "dtt.h" - -/* for LM75 DTT POST test */ -#define DTT_READ_TEMP 0x0 -#define DTT_CONFIG 0x1 -#define DTT_TEMP_HYST 0x2 -#define DTT_TEMP_SET 0x3 - -#if defined(CONFIG_RTC_M48T35A) -void rtctest(void) -{ - volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9); - struct rtc_time tmp; - - /* set up led code for RTC tests */ - log_stat(ERR_RTCG); - - /* - * Do RTC battery test. The first write after power up - * fails if battery is low. - */ - *tchar = 0xaa; - if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT); - *tchar = 0x55; /* Reset test address */ - - /* - * Now lets check the validity of the values in the RTC. - */ - rtc_get(&tmp); - if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) | - (tmp.tm_min < 0) | (tmp.tm_min > 59) | - (tmp.tm_hour < 0) | (tmp.tm_hour > 23) | - (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) | - (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) | - (tmp.tm_year < 2000) | (tmp.tm_year > 2500) | - (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) { - log_warn(ERR_RTCTIM); - rtc_reset(); - } - - /* - * Now lets do a check to see if the NV RAM is there. - */ - *tchar = 0xaa; - if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL); - *tchar = 0x55; /* Reset test address */ - -} /* rtctest() */ -#endif /* CONFIG_RTC_M48T35A */ - - -#ifdef CONFIG_DTT_LM75 -int dtt_test(int sensor) -{ - short temp, trip, hyst; - - /* get values */ - temp = dtt_read(sensor, DTT_READ_TEMP) / 256; - trip = dtt_read(sensor, DTT_TEMP_SET) / 256; - hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256; - - /* check values */ - if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) || - (trip != CONFIG_SYS_DTT_MAX_TEMP) || - (temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP)) - return 1; - - return 0; -} /* dtt_test() */ -#endif /* CONFIG_DTT_LM75 */ - -/*****************************************/ - -void post2(void) -{ -#if defined(CONFIG_RTC_M48T35A) - rtctest(); -#endif /* CONFIG_RTC_M48T35A */ - -#ifdef CONFIG_DTT_LM75 - log_stat(ERR_TempG); - if(dtt_test(2) != 0) log_warn(ERR_Ttest0); - if(dtt_test(4) != 0) log_warn(ERR_Ttest1); -#endif /* CONFIG_DTT_LM75 */ -} /* post2() */ diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug deleted file mode 100644 index 5740efb7ef..0000000000 --- a/board/w7o/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c deleted file mode 100644 index fbcc3944dc..0000000000 --- a/board/w7o/vpd.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if defined(VXWORKS) -#include <stdio.h> -#include <string.h> -#define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0 -extern char iicReadByte(char, char); -extern ulong_t crc32(unsigned char *, unsigned long); -#else -#include <common.h> -#endif - -#include "vpd.h" - -/* - * vpd_reader() - reads VPD data from I2C EEPROMS. - * returns pointer to buffer or NULL. - */ -static unsigned char *vpd_reader(unsigned char *buf, unsigned dev_addr, - unsigned off, unsigned count) -{ - unsigned offset = off; /* Calculated offset */ - - /* - * The main board EEPROM contains - * SDRAM SPD in the first 128 bytes, - * so skew the offset. - */ - if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR) - offset += SDRAM_SPD_DATA_SIZE; - - /* Try to read the I2C EEPROM */ -#if defined(VXWORKS) - { - int i; - - for (i = 0; i < count; ++i) - buf[i] = iicReadByte(dev_addr, offset + i); - } -#else - if (eeprom_read(dev_addr, offset, buf, count)) { - printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n", - count, dev_addr, offset); - return NULL; - } -#endif - - return buf; -} - - -/* - * vpd_get_packet() - returns next VPD packet or NULL. - */ -static vpd_packet_t *vpd_get_packet(vpd_packet_t * vpd_packet) -{ - vpd_packet_t *packet = vpd_packet; - - if (packet != NULL) { - if (packet->identifier == VPD_PID_TERM) - return NULL; - else - packet = (vpd_packet_t *) ((char *) packet + - packet->size + 2); - } - - return packet; -} - - -/* - * vpd_find_packet() - Locates and returns the specified - * VPD packet or NULL on error. - */ -static vpd_packet_t *vpd_find_packet(vpd_t * vpd, unsigned char ident) -{ - vpd_packet_t *packet = (vpd_packet_t *) &vpd->packets; - - /* Guaranteed illegal */ - if (ident == VPD_PID_GI) - return NULL; - - /* Scan tuples looking for a match */ - while ((packet->identifier != ident) && - (packet->identifier != VPD_PID_TERM)) - packet = vpd_get_packet(packet); - - /* Did we find it? */ - if ((packet->identifier) && (packet->identifier != ident)) - return NULL; - return packet; -} - - -/* - * vpd_is_valid() - Validates contents of VPD data - * in I2C EEPROM. Returns 1 for - * success or 0 for failure. - */ -static int vpd_is_valid(unsigned dev_addr, unsigned char *buf) -{ - unsigned num_bytes; - vpd_packet_t *packet; - vpd_t *vpd = (vpd_t *) buf; - unsigned short stored_crc16, calc_crc16 = 0xffff; - - /* Check Eyecatcher */ - if (strncmp - ((char *) (vpd->header.eyecatcher), VPD_EYECATCHER, - VPD_EYE_SIZE) != 0) { - unsigned offset = 0; - - if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR) - offset += SDRAM_SPD_DATA_SIZE; - printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, - offset); - - return 0; - } - - /* Check Length */ - if (vpd->header.size > VPD_MAX_EEPROM_SIZE) { - printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n", - dev_addr, vpd->header.size); - return 0; - } - - /* Now find the termination packet */ - packet = vpd_find_packet(vpd, VPD_PID_TERM); - if (packet == NULL) { - printf("Error: VPD EEPROM 0x%x missing termination packet\n", - dev_addr); - return 0; - } - - /* Calculate data size */ - num_bytes = (unsigned long) ((unsigned char *) packet - - (unsigned char *) vpd + - sizeof(vpd_packet_t)); - - /* Find stored CRC and clear it */ - packet = vpd_find_packet(vpd, VPD_PID_CRC); - if (packet == NULL) { - printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr); - return 0; - } - memcpy(&stored_crc16, packet->data, sizeof(ushort)); - memset(packet->data, 0, sizeof(ushort)); - - /* OK, lets calculate the CRC and check it */ -#if defined(VXWORKS) - calc_crc16 = (0xffff & crc32(buf, num_bytes)); -#else - calc_crc16 = (0xffff & crc32(0, buf, num_bytes)); -#endif - /* Now restore the CRC */ - memcpy(packet->data, &stored_crc16, sizeof(ushort)); - if (stored_crc16 != calc_crc16) { - printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n", - dev_addr, stored_crc16); - return 0; - } - - return 1; -} - - -/* - * size_ok() - Check to see if packet size matches - * size of data we want. Returns 1 for - * good match or 0 for failure. - */ -static int size_ok(vpd_packet_t *packet, unsigned long size) -{ - if (packet->size != size) { - printf("VPD Packet 0x%x corrupt.\n", packet->identifier); - return 0; - } - return 1; -} - - -/* - * strlen_ok() - Check to see if packet size matches - * strlen of the string we want to populate. - * Returns 1 for valid length or 0 for failure. - */ -static int strlen_ok(vpd_packet_t *packet, unsigned long length) -{ - if (packet->size >= length) { - printf("VPD Packet 0x%x corrupt.\n", packet->identifier); - return 0; - } - return 1; -} - - -/* - * get_vpd_data() - populates the passed VPD structure 'vpdInfo' - * with data obtained from the specified - * I2C EEPROM 'dev_addr'. Returns 0 for - * success or 1 for failure. - */ -int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo) -{ - unsigned char buf[VPD_EEPROM_SIZE]; - vpd_t *vpd = (vpd_t *) buf; - vpd_packet_t *packet; - - if (vpdInfo == NULL) - return 1; - - /* - * Fill vpdInfo with 0s to blank out - * unused fields, fill vpdInfo->ethAddrs - * with all 0xffs so that other's code can - * determine how many real Ethernet addresses - * there are. OUIs starting with 0xff are - * broadcast addresses, and would never be - * permantely stored. - */ - memset((void *) vpdInfo, 0, sizeof(VPD)); - memset((void *) &vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs)); - vpdInfo->_devAddr = dev_addr; - - /* Read the minimum size first */ - if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL) - return 1; - - /* Check validity of VPD data */ - if (!vpd_is_valid(dev_addr, buf)) { - printf("VPD Data is INVALID!\n"); - return 1; - } - - /* - * Walk all the packets and populate - * the VPD info structure. - */ - packet = (vpd_packet_t *) &vpd->packets; - do { - switch (packet->identifier) { - case VPD_PID_GI: - printf("Error: Illegal VPD value\n"); - break; - case VPD_PID_PID: - if (strlen_ok(packet, MAX_PROD_ID)) { - strncpy(vpdInfo->productId, - (char *) (packet->data), - packet->size); - } - break; - case VPD_PID_REV: - if (size_ok(packet, sizeof(char))) - vpdInfo->revisionId = *packet->data; - break; - case VPD_PID_SN: - if (size_ok(packet, sizeof(unsigned long))) { - memcpy(&vpdInfo->serialNum, - packet->data, - sizeof(unsigned long)); - } - break; - case VPD_PID_MANID: - if (size_ok(packet, sizeof(unsigned char))) - vpdInfo->manuID = *packet->data; - break; - case VPD_PID_PCO: - if (size_ok(packet, sizeof(unsigned long))) { - memcpy(&vpdInfo->configOpt, - packet->data, - sizeof(unsigned long)); - } - break; - case VPD_PID_SYSCLK: - if (size_ok(packet, sizeof(unsigned long))) - memcpy(&vpdInfo->sysClk, - packet->data, - sizeof(unsigned long)); - break; - case VPD_PID_SERCLK: - if (size_ok(packet, sizeof(unsigned long))) - memcpy(&vpdInfo->serClk, - packet->data, - sizeof(unsigned long)); - break; - case VPD_PID_FLASH: - if (size_ok(packet, 9)) { /* XXX - hardcoded, - padding in struct */ - memcpy(&vpdInfo->flashCfg, packet->data, 9); - } - break; - case VPD_PID_ETHADDR: - memcpy(vpdInfo->ethAddrs, packet->data, packet->size); - break; - case VPD_PID_POTS: - if (size_ok(packet, sizeof(char))) - vpdInfo->numPOTS = (unsigned) *packet->data; - break; - case VPD_PID_DS1: - if (size_ok(packet, sizeof(char))) - vpdInfo->numDS1 = (unsigned) *packet->data; - case VPD_PID_GAL: - case VPD_PID_CRC: - case VPD_PID_TERM: - break; - default: - printf("Warning: Found unknown VPD packet ID 0x%x\n", - packet->identifier); - break; - } - } while ((packet = vpd_get_packet(packet))); - - return 0; -} - - -/* - * vpd_init() - Initialize default VPD environment - */ -int vpd_init(unsigned char dev_addr) -{ - return 0; -} - - -/* - * vpd_print() - Pretty print the VPD data. - */ -void vpd_print(VPD *vpdInfo) -{ - const char *const sp = ""; - const char *const sfmt = "%4s%-20s: \"%s\"\n"; - const char *const cfmt = "%4s%-20s: '%c'\n"; - const char *const dfmt = "%4s%-20s: %ld\n"; - const char *const hfmt = "%4s%-20s: %08lX\n"; - const char *const dsfmt = "%4s%-20s: %d\n"; - const char *const hsfmt = "%4s%-20s: %04X\n"; - const char *const dhfmt = "%4s%-20s: %ld (%lX)\n"; - - printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr); - - if (vpdInfo->productId[0]) - printf(sfmt, sp, "Product ID", vpdInfo->productId); - else - printf(sfmt, sp, "Product ID", "UNKNOWN"); - - if (vpdInfo->revisionId) - printf(cfmt, sp, "Revision ID", vpdInfo->revisionId); - - if (vpdInfo->serialNum) - printf(dfmt, sp, "Serial Number", vpdInfo->serialNum); - - if (vpdInfo->manuID) - printf(dfmt, sp, "Manufacture ID", (long) vpdInfo->manuID); - - if (vpdInfo->configOpt) - printf(hfmt, sp, "Configuration", vpdInfo->configOpt); - - if (vpdInfo->sysClk) - printf(dhfmt, sp, "System Clock", vpdInfo->sysClk, - vpdInfo->sysClk); - - if (vpdInfo->serClk) - printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk, - vpdInfo->serClk); - - if (vpdInfo->numPOTS) - printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS); - - if (vpdInfo->numDS1) - printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1); - - /* Print Ethernet Addresses */ - if (vpdInfo->ethAddrs[0][0] != 0xff) { - int i, j; - - printf("%4sEtherNet Address(es): ", sp); - for (i = 0; i < MAX_ETH_ADDRS; i++) { - if (vpdInfo->ethAddrs[i][0] != 0xff) { - for (j = 0; j < 6; j++) { - printf("%02X", - vpdInfo->ethAddrs[i][j]); - if (((j + 1) % 6) != 0) - printf(":"); - else - printf(" "); - } - if (((i + 1) % 3) == 0) - printf("\n%24s: ", sp); - } - } - printf("\n"); - } - - if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) { - printf("Main Flash Configuration:\n"); - printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg); - printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev); - printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth); - printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs); - printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols); - printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth); - printf(dsfmt, sp, "WE Data Width", - vpdInfo->flashCfg.weDataWidth); - } -} diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h deleted file mode 100644 index 2395b18a90..0000000000 --- a/board/w7o/vpd.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _VPD_H_ -#define _VPD_H_ - -/* - * Main Flash Configuration. - */ -typedef struct flashCfg_s { - unsigned short mfg; /* Manufacture ID */ - unsigned short dev; /* Device ID */ - unsigned char devWidth; /* Device Width */ - unsigned char numDevs; /* Number of devices */ - unsigned char numCols; /* Number of columns */ - unsigned char colWidth; /* Width of a column */ - unsigned char weDataWidth; /* Write/Erase Data Width */ -} flashCfg_t; - -/* - * Vital Product Data - VPD - */ -#define MAX_PROD_ID 15 -#define MAX_ETH_ADDRS 10 -typedef unsigned char EthAddr[6]; -typedef struct vpd { - unsigned char _devAddr; /* Device address during read */ - char productId[MAX_PROD_ID]; /* Product ID */ - char revisionId; /* Revision ID as a char */ - unsigned long serialNum; /* Serial number */ - unsigned char manuID; /* Manufact ID - byte int */ - unsigned long configOpt; /* Config Option - bit field */ - unsigned long sysClk; /* System clock in Hertz */ - unsigned long serClk; /* Ext. clock in Hertz */ - flashCfg_t flashCfg; /* Flash configuration */ - unsigned long numPOTS; /* Number of POTS lines */ - unsigned long numDS1; /* Number of DS1 circuits */ - EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */ -} VPD; - - -#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */ -#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */ - -/* - * PIDs - Packet Identifiers - */ -#define VPD_PID_GI 0x0 /* Guaranted Illegal */ -#define VPD_PID_PID 0x1 /* Product Identifier */ -#define VPD_PID_REV 0x2 /* Product Revision */ -#define VPD_PID_SN 0x3 /* Serial Number */ -#define VPD_PID_MANID 0x4 /* Manufacture ID */ -#define VPD_PID_PCO 0x5 /* Product configuration */ -#define VPD_PID_SYSCLK 0x6 /* System Clock */ -#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */ -#define VPD_PID_CRC 0x8 /* VPD CRC */ -#define VPD_PID_FLASH 0x9 /* Flash Configuration */ -#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */ -#define VPD_PID_GAL 0xB /* Galileo Switch Config */ -#define VPD_PID_POTS 0xC /* Number of POTS Lines */ -#define VPD_PID_DS1 0xD /* Number of DS1s */ -#define VPD_PID_TERM 0xFF /* Termination packet */ - -/* - * VPD - Eyecatcher/Magic - */ -#define VPD_EYECATCHER "W7O" -#define VPD_EYE_SIZE 3 -typedef struct vpd_header { - unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */ - unsigned short size __attribute__((packed)); /* size of EEPROM */ -} vpd_header_t; - - -#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \ - sizeof(vpd_header_t)) -typedef struct vpd_s { - vpd_header_t header; - unsigned char packets[VPD_DATA_SIZE]; -} vpd_t; - -typedef struct vpd_packet { - unsigned char identifier; - unsigned char size; - unsigned char data[1]; -} vpd_packet_t; - -/* - * VPD configOpt bit mask - */ -#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */ -#define VPD_HAS_RTC 0x2 /* Battery backed RTC */ -#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */ -#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */ -#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */ -#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */ -#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */ -#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */ -#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */ -#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */ -#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */ -#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */ -#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */ -#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */ -#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */ -#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */ -#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */ - -#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */ - -extern int vpd_get_data(unsigned char dev_addr, VPD *vpd); -extern void vpd_print(VPD *vpdInfo); - -#endif /* _VPD_H_ */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c deleted file mode 100644 index afbbaf58e5..0000000000 --- a/board/w7o/w7o.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include "w7o.h" -#include <asm/processor.h> - -#include "vpd.h" -#include "errors.h" -#include <watchdog.h> - -unsigned long get_dram_size (void); -void sdram_init(void); - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ -#if defined(CONFIG_W7OLMG) - /* - * Setup GPIO pins - reset devices. - */ - out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ - out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ - out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive - * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive - * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive - * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive - * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, - INT0 highest priority */ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - -#elif defined(CONFIG_W7OLMC) - /* - * Setup GPIO pins - */ - out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ - out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ - out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive - * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, - INT0 highest priority */ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - -#else /* Unknown */ -# error "Unknown W7O board configuration" -#endif - - WATCHDOG_RESET (); /* Reset the watchdog */ - temp_uart_init (); /* init the uart for debug */ - WATCHDOG_RESET (); /* Reset the watchdog */ - test_led (); /* test the LEDs */ - test_sdram (get_dram_size ()); /* test the dram */ - log_stat (ERR_POST1); /* log status,post1 complete */ - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - VPD vpd; - - puts ("Board: "); - - /* VPD data present in I2C EEPROM */ - if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) { - /* - * Known board type. - */ - if (vpd.productId[0] && - ((strncmp (vpd.productId, "GMM", 3) == 0) || - (strncmp (vpd.productId, "CMM", 3) == 0))) { - - /* Output board information on startup */ - printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID); - return (0); - } - } - - puts ("### Unknown HW ID - assuming NOTHING\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in arch/powerpc/cpu/ppc4xx - */ - sdram_init(); - - return get_dram_size (); -} - -unsigned long get_dram_size (void) -{ - int tmp, i, regs[4]; - int size = 0; - - /* Get bank Size registers */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ - regs[0] = mfdcr (SDRAM0_CFGDATA); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ - regs[1] = mfdcr (SDRAM0_CFGDATA); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ - regs[2] = mfdcr (SDRAM0_CFGDATA); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ - regs[3] = mfdcr (SDRAM0_CFGDATA); - - /* compute the size, add each bank if enabled */ - for (i = 0; i < 4; i++) { - if (regs[i] & 0x0001) { /* if enabled, */ - tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */ - tmp = 0x400000 << tmp; /* Size bits X 4MB = size */ - size += tmp; - } - } - - return size; -} - -int misc_init_f (void) -{ - return 0; -} - -static void w7o_env_init (VPD * vpd) -{ - /* - * Read VPD - */ - if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0) - return; - - /* - * Known board type. - */ - if (vpd->productId[0] && - ((strncmp (vpd->productId, "GMM", 3) == 0) || - (strncmp (vpd->productId, "CMM", 3) == 0))) { - char buf[30]; - char *eth; - char *serial = getenv ("serial#"); - char *ethaddr = getenv ("ethaddr"); - - /* Set 'serial#' envvar if serial# isn't set */ - if (!serial) { - sprintf (buf, "%s-%ld", vpd->productId, - vpd->serialNum); - setenv ("serial#", buf); - } - - /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ - eth = (char *)(vpd->ethAddrs[0]); - if (ethaddr - && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) { - /* Now setup ethaddr */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eth[0], eth[1], eth[2], eth[3], eth[4], - eth[5]); - setenv ("ethaddr", buf); - } - } -} /* w7o_env_init() */ - - -int misc_init_r (void) -{ - VPD vpd; /* VPD information */ - -#if defined(CONFIG_W7OLMG) - unsigned long greg; /* GPIO Register */ - - greg = in32 (PPC405GP_GPIO0_OR); - - /* - * XXX - Unreset devices - this should be moved into VxWorks driver code - */ - greg |= 0x41800000L; /* SAM, PHY, Galileo */ - - out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ -#endif /* CONFIG_W7OLMG */ - - /* - * Initialize W7O environment variables - */ - w7o_env_init (&vpd); - - /* - * Initialize the FPGA(s). - */ - if (init_fpga () == 0) - test_fpga ((unsigned short *) CONFIG_FPGAS_BASE); - - /* More POST testing. */ - post2 (); - - /* Done with hardware initialization and POST. */ - log_stat (ERR_POSTOK); - - /* Call silly, fail safe boot init routine */ - init_fsboot (); - - return (0); -} diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h deleted file mode 100644 index 9ef682c66f..0000000000 --- a/board/w7o/w7o.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _W7O_H_ -#define _W7O_H_ -#include <config.h> - -/* AMCC 405GP PowerPC GPIO registers */ -#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */ -#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ -#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ -#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ - -/* LMG FPGA <=> CPU GPIO signals */ -#define LMG_XCV_INIT 0x10000000L -#define LMG_XCV_PROG 0x04000000L -#define LMG_XCV_DONE 0x00400000L -#define LMG_XCV_CNFG_0 0x08000000L -#define LMG_XCV_IRQ_0 0x0L - -/* LMC FPGA <=> CPU GPIO signals */ -#define LMC_XCV_INIT 0x00800000L -#define LMC_XCV_PROG 0x40000000L -#define LMC_XCV_DONE 0x01000000L -#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */ -#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */ -#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */ -#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */ -#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */ -#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */ - - -/* - * Setup FPGA <=> GPIO mappings - */ -#if defined(CONFIG_W7OLMG) -# define GPIO_XCV_INIT LMG_XCV_INIT -# define GPIO_XCV_PROG LMG_XCV_PROG -# define GPIO_XCV_DONE LMG_XCV_DONE -# define GPIO_XCV_CNFG LMG_XCV_CNFG_0 -# define GPIO_XCV_IRQ LMG_XCV_IRQ_0 -# define GPIO_GPIO_1 0x40000000L -# define GPIO_GPIO_6 0x02000000L -# define GPIO_GPIO_7 0x01000000L -# define GPIO_GPIO_8 0x00800000L -#elif defined(CONFIG_W7OLMC) -# define GPIO_XCV_INIT LMC_XCV_INIT -# define GPIO_XCV_PROG LMC_XCV_PROG -# define GPIO_XCV_DONE LMC_XCV_DONE -# define GPIO_XCV_CNFG LMC_XCV_CNFG_0 -# define GPIO_XCV_IRQ LMC_XCV_IRQ_0 -#else -# error "Unknown W7O board configuration" -#endif - -/* Power On Self Tests */ -extern void post2(void); -extern int test_led(void); -extern int test_sdram(unsigned long size); -extern void test_fpga(unsigned short *daddr); - -/* FGPA */ -extern int init_fpga(void); - -/* Misc */ -extern int temp_uart_init(void); -extern void init_fsboot(void); - -#endif /* _W7O_H_ */ diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c deleted file mode 100644 index ff1b212096..0000000000 --- a/board/w7o/watchdog.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * W7O board level hardware watchdog. - */ -#include <common.h> -#include <config.h> - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> - -void hw_watchdog_reset(void) -{ - volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000); - - /* - * Read the LMG's hwd register and toggle the - * watchdog bit to reset it. On the LMC, just - * reading it is enough, but toggling the bit - * doen't hurt either. - */ - *hwd = *hwd ^ 0x8000; - -} /* hw_watchdog_reset() */ - -#endif /* CONFIG_HW_WATCHDOG */ |
