diff options
Diffstat (limited to 'board')
195 files changed, 2121 insertions, 1303 deletions
diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig deleted file mode 100644 index f12b96829d..0000000000 --- a/board/Marvell/db-88f6820-gp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_88F6820_GP - -config SYS_BOARD - default "db-88f6820-gp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-88f6820-gp" - -endif diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg index cc05792556..1f748db37c 100644 --- a/board/Marvell/db-88f6820-gp/kwbimage.cfg +++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig deleted file mode 100644 index 428a5e1516..0000000000 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_MV784MP_GP - -config SYS_BOARD - default "db-mv784mp-gp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-mv784mp-gp" - -endif diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index d7aa1499ad..9305284117 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -87,40 +87,32 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1545 PHY */ -void reset_phy(void) +int board_phy_config(struct phy_device *phydev) { - u8 phy_addr[] = CONFIG_PHY_ADDR; - u16 devadr = phy_addr[0]; - char *name = "neta0"; u16 reg; - if (miiphy_set_current_dev(name)) - return; - /* Enable QSGMII AN */ /* Set page to 4 */ - miiphy_write(name, devadr, 0x16, 4); + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); /* Enable AN */ - miiphy_write(name, devadr, 0x0, 0x1140); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); /* Set page to 0 */ - miiphy_write(name, devadr, 0x16, 0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); /* Phy C_ANEG */ - miiphy_read(name, devadr, 0x4, ®); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); reg |= 0x1E0; - miiphy_write(name, devadr, 0x4, reg); + phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); /* Soft-Reset */ - miiphy_write(name, devadr, 22, 0x0000); - miiphy_write(name, devadr, 0, 0x9140); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); /* Power up the phy */ - miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); - miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); - printf("88E1545 Initialized on %s\n", name); + printf("88E1545 Initialized\n"); + return 0; } -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg index cc05792556..1f748db37c 100644 --- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile new file mode 100644 index 0000000000..e66aeb8467 --- /dev/null +++ b/board/Synology/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Phil Sutter <phil@nwl.cc> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cmd_syno.o diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/common/cmd_syno.c new file mode 100644 index 0000000000..20544e29c4 --- /dev/null +++ b/board/Synology/common/cmd_syno.c @@ -0,0 +1,227 @@ +/* + * Commands to deal with Synology specifics. + * + * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <spi.h> +#include <spi_flash.h> +#include <linux/mtd/mtd.h> + +#include <asm/io.h> +#include "../drivers/ddr/marvell/axp/ddr3_init.h" + +#define ETH_ALEN 6 +#define ETHADDR_MAX 4 +#define SYNO_SN_TAG "SN=" +#define SYNO_CHKSUM_TAG "CHK=" + + +static int do_syno_populate(int argc, char * const argv[]) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + struct spi_flash *flash; + unsigned long addr = 0x80000; /* XXX: parameterize this? */ + loff_t offset = 0x007d0000; + loff_t len = 0x00010000; + char *buf, *bufp; + char var[128]; + char val[128]; + int ret, n; + + /* XXX: arg parsing to select flash here? */ + + flash = spi_flash_probe(bus, cs, speed, mode); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", bus, cs); + return 1; + } + + buf = map_physmem(addr, len, MAP_WRBACK); + if (!buf) { + puts("Failed to map physical memory\n"); + return 1; + } + + ret = spi_flash_read(flash, offset, len, buf); + if (ret) { + puts("Failed to read from SPI flash\n"); + goto out_unmap; + } + + for (n = 0; n < ETHADDR_MAX; n++) { + char ethaddr[ETH_ALEN]; + int i, sum = 0; + unsigned char csum = 0; + + for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) { + sum += bufp[i]; + csum += bufp[i]; + ethaddr[i] = bufp[i]; + } + if (!sum) /* MAC address empty */ + continue; + if (csum != bufp[i]) { /* seventh byte is checksum value */ + printf("Invalid MAC address for interface %d!\n", n); + continue; + } + if (n == 0) + sprintf(var, "ethaddr"); + else + sprintf(var, "eth%daddr", n); + snprintf(val, sizeof(val) - 1, + "%02x:%02x:%02x:%02x:%02x:%02x", + ethaddr[0], ethaddr[1], ethaddr[2], + ethaddr[3], ethaddr[4], ethaddr[5]); + printf("parsed %s = %s\n", var, val); + setenv(var, val); + } + if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) { + char *snp, *csump; + int csum = 0; + unsigned long c; + + snp = bufp = buf + 32 + strlen(SYNO_SN_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + csum += bufp[n]; + bufp[n] = '\0'; + + /* should come right after, but you never know */ + bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG); + if (!bufp) { + printf("Serial number checksum tag missing!\n"); + goto out_unmap; + } + + csump = bufp += strlen(SYNO_CHKSUM_TAG); + for (n = 0; bufp[n] && bufp[n] != ','; n++) + ; + bufp[n] = '\0'; + + if (strict_strtoul(csump, 10, &c) || c != csum) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + printf("parsed SN = %s\n", snp); + setenv("SN", snp); + } else { /* old style format */ + unsigned char csum = 0; + + for (n = 0, bufp = buf + 32; n < 10; n++) + csum += bufp[n]; + + if (csum != bufp[n]) { + puts("Invalid serial number found!\n"); + ret = 1; + goto out_unmap; + } + bufp[n] = '\0'; + printf("parsed SN = %s\n", buf + 32); + setenv("SN", buf + 32); + } +out_unmap: + unmap_physmem(buf, len); + return ret; +} + +/* map bit position to function in POWER_MNG_CTRL_REG */ +static const char * const pwr_mng_bit_func[] = { + "audio", + "ge3", "ge2", "ge1", "ge0", + "pcie00", "pcie01", "pcie02", "pcie03", + "pcie10", "pcie11", "pcie12", "pcie13", + "bp", + "sata0_link", "sata0_core", + "lcd", + "sdio", + "usb0", "usb1", "usb2", + "idma", "xor0", "crypto", + NULL, + "tdm", + "pcie20", "pcie30", + "xor1", + "sata1_link", "sata1_core", + NULL, +}; + +static int do_syno_clk_gate(int argc, char * const argv[]) +{ + u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + const char *func, *state; + int i, val; + + if (argc < 2) + return -1; + + if (!strcmp(argv[1], "get")) { + puts("Clock Gating:\n"); + for (i = 0; i < 32; i++) { + func = pwr_mng_bit_func[i]; + if (!func) + continue; + state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF"; + printf("%s:\t\t%s\n", func, state); + } + return 0; + } + if (argc < 4) + return -1; + if (!strcmp(argv[1], "set")) { + func = argv[2]; + state = argv[3]; + for (i = 0; i < 32; i++) { + if (!pwr_mng_bit_func[i]) + continue; + if (!strcmp(func, pwr_mng_bit_func[i])) + break; + } + if (i == 32) { + printf("Error: name '%s' not known\n", func); + return -1; + } + val = state[0] != '0'; + pwr_mng_ctrl_reg |= (val << i); + pwr_mng_ctrl_reg &= ~(!val << i); + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + } + return 0; +} + +static int do_syno(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + const char *cmd; + int ret = 0; + + if (argc < 2) + goto usage; + + cmd = argv[1]; + --argc; + ++argv; + + if (!strcmp(cmd, "populate_env")) + ret = do_syno_populate(argc, argv); + else if (!strcmp(cmd, "clk_gate")) + ret = do_syno_clk_gate(argc, argv); + + if (ret != -1) + return ret; +usage: + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + syno, 5, 1, do_syno, + "Synology specific commands", + "populate_env - Read vendor data from SPI flash into environment\n" + "clk_gate (get|set name 1|0) - Manage clock gating\n" +); diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile new file mode 100644 index 0000000000..0f4c32d57c --- /dev/null +++ b/board/Synology/ds414/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Phil Sutter <phil@nwl.cc> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ds414.o diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c new file mode 100644 index 0000000000..d563e896f3 --- /dev/null +++ b/board/Synology/ds414/ds414.c @@ -0,0 +1,185 @@ +/* + * + * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/mbus.h> + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" +#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */ + +#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30)) +#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15)) +#define DS414_GPP_OUT_VAL_HIGH (0) + +#define DS414_GPP_OUT_POL_LOW (0) +#define DS414_GPP_OUT_POL_MID (0) +#define DS414_GPP_OUT_POL_HIGH (0) + +#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30))) +#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \ + BIT(13) | BIT(14) | BIT(15))) +#define DS414_GPP_OUT_ENA_HIGH (~0) + +static const u32 ds414_mpp_control[] = { + 0x11111111, + 0x22221111, + 0x22222222, + 0x00000000, + 0x11110000, + 0x00004000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +/* DDR3 static MC configuration */ + +/* 1G_v1 (4x2Gbits) adapted by DS414 */ +MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /*Dunit Control Low Register */ + {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */ + + {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */ + + {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ + {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ + {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ + {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */ + {0x00001428, 0x000F8830}, /*Dunit Control High Register */ + {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */ + {0x0000147C, 0x0000C671}, + + {0x000014a0, 0x00000001}, + {0x000014a8, 0x00000100}, /*2:1 */ + {0x00020220, 0x00000006}, + + {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ + {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ + {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */ + + {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */ + {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */ + + {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/ + {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ + + {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /*MR0 */ + {0x000015D4, 0x00000044}, /*MR1 */ + {0x000015D8, 0x00000010}, /*MR2 */ + {0x000015DC, 0x00000000}, /*MR3 */ + + {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ + {0x000015EC, 0xF800A225}, /*DDR PHY */ + + {0x0, 0x0} +}; + +MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +MV_BIN_SERDES_CFG ds414_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000, + { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, + PEX_BUS_DISABLED }, + 0x0040, serdes_change_m_phy + } +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + return &ds414_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &ds414_serdes_cfg[0]; +} + +u8 board_sat_r_get(u8 dev_num, u8 reg) +{ + return (0x1 << 1 | 1); +} + +int board_early_init_f(void) +{ + int i; + + /* Set GPP Out value */ + reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); + reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); + reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); + + /* set GPP polarity */ + reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); + reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); + reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); + + /* Set GPP Out Enable */ + reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); + reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); + reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); + + for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++) + reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); + + return 0; +} + +int board_init(void) +{ + u32 pwr_mng_ctrl_reg; + + /* Adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Gate unused clocks + * + * Note: Disabling unused PCIe lanes will hang PCI bus scan. + * Once this is resolved, bits 10-12, 26 and 27 can be + * unset here as well. + */ + pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); + pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ + pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */ + pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */ + pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */ + pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */ + pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */ + pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */ + reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); + + return 0; +} + +int checkboard(void) +{ + puts("Board: DS414\n"); + + return 0; +} diff --git a/board/Synology/ds414/kwbimage.cfg b/board/Synology/ds414/kwbimage.cfg new file mode 100644 index 0000000000..1f748db37c --- /dev/null +++ b/board/Synology/ds414/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk index 05a4162dbc..53d3f34692 100644 --- a/board/amcc/yucca/config.mk +++ b/board/amcc/yucca/config.mk @@ -9,12 +9,6 @@ # AMCC 440SPe Reference Platform (yucca) board # -ifeq ($(ramsym),1) -CONFIG_SYS_TEXT_BASE = 0x07FD0000 -else -CONFIG_SYS_TEXT_BASE = 0xfffb0000 -endif - PLATFORM_CPPFLAGS += -DCONFIG_440=1 ifeq ($(debug),1) diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig deleted file mode 100644 index 0b67ebde93..0000000000 --- a/board/avnet/fx12mm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_FX12MM - -config SYS_BOARD - default "fx12mm" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "fx12mm" - -endif diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS deleted file mode 100644 index c92e258df9..0000000000 --- a/board/avnet/fx12mm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -FX12MM BOARD -M: Georg Schardt <schardt@team-ctech.de> -S: Maintained -F: board/avnet/fx12mm/ -F: include/configs/fx12mm.h -F: configs/fx12mm_defconfig -F: configs/fx12mm_flash_defconfig diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile deleted file mode 100644 index 618b42f891..0000000000 --- a/board/avnet/fx12mm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fx12mm.o - -include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c deleted file mode 100644 index 92e1cfb75f..0000000000 --- a/board/avnet/fx12mm/fx12mm.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Author: Xilinx Inc. - * - * Modified by: - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0) { - printf("Avnet Virtex4 FX12 with no serial #"); - } else { - printf("Avnet Virtex4 FX12 Minimodul # "); - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - } - putc('\n'); - return 0; -} diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h deleted file mode 100644 index 94f682f8ec..0000000000 --- a/board/avnet/fx12mm/xparameters.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * CAUTION: This file is based on the xparameters.h automatically - * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 - */ - -#ifndef __XPARAMETER_H__ -#define __XPARAMETER_H__ - -/* RS232 */ -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 -#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 - - -/* INT_C */ -#define XPAR_XPS_INTC_0_DEVICE_ID 0 -#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 - -/* CPU core clock */ -#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 - -/* RAM */ -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 - -/* FLASH */ -#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 - -#endif diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig deleted file mode 100644 index 079387b707..0000000000 --- a/board/avnet/v5fx30teval/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_V5FX30TEVAL - -config SYS_BOARD - default "v5fx30teval" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "v5fx30teval" - -endif diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS deleted file mode 100644 index 91dde7a5c8..0000000000 --- a/board/avnet/v5fx30teval/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -V5FX30TEVAL BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/avnet/v5fx30teval/ -F: include/configs/v5fx30teval.h -F: configs/v5fx30teval_defconfig -F: configs/v5fx30teval_flash_defconfig diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile deleted file mode 100644 index 8c41af02d4..0000000000 --- a/board/avnet/v5fx30teval/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += v5fx30teval.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c deleted file mode 100644 index 68b0eb959d..0000000000 --- a/board/avnet/v5fx30teval/v5fx30teval.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Avnet Virtex 5 FX30 Evaluation Board\n"); - return 0; -} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h deleted file mode 100644 index 95b8c285ad..0000000000 --- a/board/avnet/v5fx30teval/xparameters.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 0000000000..927d8765d6 --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,27 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +config CMD_ATF + bool "Enable ATF query commands" + default y + help + Enable vendor specific ATF query commands such as SPI and SD/MMC + devices access, low level environment query, boot device layout + and node count. + +endif diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS new file mode 100644 index 0000000000..c84d3b553d --- /dev/null +++ b/board/cavium/thunderx/MAINTAINERS @@ -0,0 +1,6 @@ +THUNDERX BOARD +M: Sergey Temerkhanov <s.temerkhanov@gmail.com> +S: Maintained +F: board/cavium/thunderx/ +F: include/configs/thunderx_88xx.h +F: configs/thunderx_88xx_defconfig diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 0000000000..c78c414cdf --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o atf.o diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c new file mode 100644 index 0000000000..6ab9de944f --- /dev/null +++ b/board/cavium/thunderx/atf.c @@ -0,0 +1,312 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <asm/io.h> + +#include <asm/system.h> +#include <cavium/thunderx_svc.h> +#include <cavium/atf.h> +#include <cavium/atf_part.h> + +#include <asm/psci.h> + +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_MMC_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NOR_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_pcount(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_PART_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_part(struct storage_partition *part, unsigned int index) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_GET_PART; + regs.regs[1] = (uintptr_t)part; + regs.regs[2] = index; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_erase_nor(uintptr_t offset, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_ERASE; + regs.regs[1] = offset; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_MMC_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_dram_size(unsigned int node) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_DRAM_SIZE; + regs.regs[1] = node; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_node_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NODE_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_string(size_t index, char *str) +{ + uint64_t *buf = (void *)str; + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_STRING; + regs.regs[1] = index; + + smc_call(®s); + + if (regs.regs > 0) { + buf[0] = regs.regs[0]; + buf[1] = regs.regs[1]; + buf[2] = regs.regs[2]; + buf[3] = regs.regs[3]; + + return 1; + } else { + return regs.regs[0]; + } +} + +#ifdef CONFIG_CMD_ATF + +static void atf_print_ver(void) +{ + struct pt_regs regs; + regs.regs[0] = ARM_STD_SVC_VERSION; + + smc_call(®s); + + printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]); + + regs.regs[0] = THUNDERX_SVC_VERSION; + + smc_call(®s); + + printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]); +} + +static void atf_print_uid(void) +{ +} + +static void atf_print_part_table(void) +{ + size_t pcount; + unsigned long i; + int ret; + char *ptype; + + struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + + pcount = atf_get_pcount(); + + printf("Partition count: %lu\n\n", pcount); + printf("%10s %10s %10s\n", "Type", "Size", "Offset"); + + for (i = 0; i < pcount; i++) { + ret = atf_get_part(part, i); + + if (ret < 0) { + printf("Uknown error while reading partition: %d\n", + ret); + return; + } + + switch (part->type) { + case PARTITION_NBL1FW_REST: + ptype = "NBL1FW"; + break; + case PARTITION_BL2_BL31: + ptype = "BL2_BL31"; + break; + case PARTITION_UBOOT: + ptype = "BOOTLDR"; + break; + case PARTITION_KERNEL: + ptype = "KERNEL"; + break; + case PARTITION_DEVICE_TREE: + ptype = "DEVTREE"; + break; + default: + ptype = "UNKNOWN"; + } + printf("%10s %10d %10lx\n", ptype, part->size, part->offset); + } +} + +int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ssize_t ret; + size_t size, offset; + void *buffer = 0; + unsigned int index, node; + char str[4 * sizeof(uint64_t)]; + + if ((argc == 5) && !strcmp(argv[1], "readmmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "readnor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_nor(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writenor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_nor(offset, buffer, size); + } else if ((argc == 2) && !strcmp(argv[1], "part")) { + atf_print_part_table(); + } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) { + offset = simple_strtoul(argv[2], NULL, 10); + size = simple_strtoul(argv[3], NULL, 10); + + ret = atf_erase_nor(offset, size); + } else if ((argc == 2) && !strcmp(argv[1], "envcount")) { + ret = atf_env_count(); + printf("Number of environment strings: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "envstring")) { + index = simple_strtoul(argv[2], NULL, 10); + ret = atf_env_string(index, str); + if (ret > 0) + printf("Environment string %d: %s\n", index, str); + else + printf("Return code: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) { + node = simple_strtoul(argv[2], NULL, 10); + ret = atf_dram_size(node); + printf("DRAM size: %zd Mbytes\n", ret >> 20); + } else if ((argc == 2) && !strcmp(argv[1], "nodes")) { + ret = atf_node_count(); + printf("Nodes count: %zd\n", ret); + } else if ((argc == 2) && !strcmp(argv[1], "ver")) { + atf_print_ver(); + } else if ((argc == 2) && !strcmp(argv[1], "uid")) { + atf_print_uid(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + atf, 10, 1, do_atf, + "issue calls to ATF", + "\t readmmc addr offset size - read MMC card\n" + "\t readnor addr offset size - read NOR flash\n" + "\t writemmc addr offset size - write MMC card\n" + "\t writenor addr offset size - write NOR flash\n" + "\t erasenor offset size - erase NOR flash\n" + "\t nodes - number of nodes\n" + "\t dramsize node - size of DRAM attached to node\n" + "\t envcount - number of environment strings\n" + "\t envstring index - print the environment string\n" + "\t part - print MMC partition table\n" + "\t ver - print ATF call set versions\n" +); + +#endif diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 0000000000..b9267676dc --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,102 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <linux/compiler.h> + +#include <cavium/atf.h> + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +#include <dm/platdata.h> +#include <dm/platform_data/serial_pl01x.h> + +static const struct pl01x_serial_platdata serial0 = { + .base = CONFIG_SYS_SERIAL0, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static const struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int timer_init(void) +{ + return 0; +} + +int dram_init(void) +{ + ssize_t node_count = atf_node_count(); + ssize_t dram_size; + int node; + + printf("Initializing\nNodes in system: %zd\n", node_count); + + gd->ram_size = 0; + + for (node = 0; node < node_count; node++) { + dram_size = atf_dram_size(node); + printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); + gd->ram_size += dram_size; + } + + gd->ram_size -= MEM_BASE; + + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + puts("DRAM size:"); + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + return rc; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + printf("DEBUG: PCI Init TODO *****\n"); +} +#endif diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk deleted file mode 100644 index 1af25e158a..0000000000 --- a/board/cobra5272/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 462ab05556..cd992941aa 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -4,14 +4,7 @@ * See file CREDITS for list of people who contributed to this * project. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index bef2570af6..f69aeb6d13 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -6,19 +6,7 @@ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk deleted file mode 100644 index b378ac8a60..0000000000 --- a/board/dbau1x00/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMD development board AMD Alchemy DbAu1x00, MIPS32 core -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index bd20f6e4b0..75e6f0ef5a 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <asm/mipsregs.h> #include <asm/io.h> diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 842fb76e58..409f8ee477 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -1,8 +1,8 @@ /* Memory sub-system initialization code */ #include <config.h> +#include <mach/au1x00.h> #include <asm/regdef.h> -#include <asm/au1x00.h> #include <asm/mipsregs.h> #define AU1500_SYS_ADDR 0xB1900000 diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 6a8fca61a0..e582abbaef 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -16,7 +16,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -1023,10 +1022,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 2c17156586..eb10a6f364 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index df90476a77..4b2303e849 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -408,22 +408,22 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, sizeof(f_link)); break; case 0x98: /* XAUI interface */ - sprintf(alias, "phy_xaui_slot1"); + strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); - sprintf(alias, "phy_xaui_slot2"); + strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; case 0x9e: /* XAUI interface */ case 0x9a: case 0x93: case 0x91: - sprintf(alias, "phy_xaui_slot1"); + strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); break; case 0x97: /* XAUI interface */ case 0xc3: - sprintf(alias, "phy_xaui_slot2"); + strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; default: diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 51d2814a43..be114cebef 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif +obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o endif diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 8bbe85bb3b..dfa3e2100e 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -11,6 +11,11 @@ static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + if (fsl_check_boot_mode_secure() == 0) { + printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); + return 0; + } + printf("Core is entering spin loop.\n"); loop: goto loop; @@ -21,10 +26,29 @@ loop: static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + char *hash_str = NULL; + uintptr_t haddr; + int ret; + if (argc < 2) return cmd_usage(cmdtp); + else if (argc > 2) + /* Second arg - Optional - Hash Str*/ + hash_str = argv[2]; + + /* First argument - header address -32/64bit */ + haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16); - return fsl_secboot_validate(cmdtp, flag, argc, argv); + /* With esbc_validate command, Image address must be + * part of header. So, the function is called + * by passing this argument as 0. + */ + ret = fsl_secboot_validate(haddr, hash_str, 0); + if (ret) + return 1; + + printf("esbc_validate command successful\n"); + return 0; } /***************************************************/ @@ -45,6 +69,6 @@ U_BOOT_CMD( U_BOOT_CMD( esbc_halt, 1, 0, do_esbc_halt, - "Put the core in spin loop ", + "Put the core in spin loop (Secure Boot Only)", "" ); diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c new file mode 100644 index 0000000000..ecfcc8253a --- /dev/null +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -0,0 +1,70 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_validate.h> +#include <fsl_sfp.h> + +#ifdef CONFIG_LS102XA +#include <asm/arch/immap_ls102xa.h> +#endif + +#if defined(CONFIG_MPC85xx) +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#else +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +} + +int fsl_setenv_chain_of_trust(void) +{ + /* Check Boot Mode + * If Boot Mode is Non-Secure, no changes are required + */ + if (fsl_check_boot_mode_secure() == 0) + return 0; + + /* If Boot mode is Secure, set the environment variables + * bootdelay = 0 (To disable Boot Prompt) + * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + */ + setenv("bootdelay", "0"); + setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); + return 0; +} diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index b510c71c40..8fd6dd63b1 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -24,6 +24,10 @@ #define SHA256_NIBBLES (256/4) #define NUM_HEX_CHARS (sizeof(ulong) * 2) +#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ + ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ + ((key_len) == 2 * KEY_SIZE_BYTES)) + /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, @@ -179,20 +183,97 @@ static u32 is_key_revoked(u32 keynum, u32 rev_flag) return 0; } -/* It validates srk_table key lengths.*/ -static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries) +/* It read validates srk_table key lengths.*/ +static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) { int i = 0; - for (i = 0; i < num_entries; i++) { - if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES))) + u32 ret, key_num, key_revoc_flag, size; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + for (i = 0; i < hdr->len_kr.num_srk; i++) { + if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; } + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + + return 0; +} +#endif + +static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + /* check key length */ + if (!CHECK_KEY_LEN(hdr->key_len)) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + return 0; +} + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + u32 ie_key_len, ie_revoc_flag, ie_num; + struct ie_key_info *ie_info; + + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!CHECK_KEY_LEN(ie_key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; return 0; } #endif + /* This function return length of public key.*/ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) { @@ -289,6 +370,13 @@ void fsl_secboot_handle_error(int error) printf("ERROR :: %x :: %s\n", error, e->name); } + /* If Boot Mode is secure, transition the SNVS state and issue + * reset based on type of failure and ITS setting. + * If Boot mode is non-secure, return from this function. + */ + if (fsl_check_boot_mode_secure() == 0) + return; + switch (error) { case ERROR_ESBC_CLIENT_HEADER_BARKER: case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: @@ -455,13 +543,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) return ret; /* Update hash for actual Image */ -#ifdef CONFIG_ESBC_ADDR_64BIT - ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1); -#else ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1); -#endif + (u8 *)img->img_addr, img->img_size, 1); if (ret) return ret; @@ -541,13 +624,9 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) struct fsl_secboot_img_hdr *hdr = &img->hdr; void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; + u32 ret = 0; + #ifdef CONFIG_KEY_REVOCATION - u32 ret; - u32 key_num, key_revoc_flag, size; -#endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) - struct ie_key_info *ie_info; - u32 ie_num, ie_revoc_flag, ie_key_len; #endif int key_found = 0; @@ -555,93 +634,48 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; -#ifdef CONFIG_ESBC_ADDR_64BIT - sprintf(buf, "%llx", hdr->pimg64); -#else - sprintf(buf, "%x", hdr->pimg); -#endif + /* If Image Address is not passed as argument to function, + * then Address and Size must be read from the Header. + */ + if (img->img_addr == 0) { + #ifdef CONFIG_ESBC_ADDR_64BIT + img->img_addr = hdr->pimg64; + #else + img->img_addr = hdr->pimg; + #endif + } + + sprintf(buf, "%lx", img->img_addr); setenv("img_addr", buf); if (!hdr->img_size) return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + img->img_size = hdr->img_size; + /* Key checking*/ #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { - if ((hdr->len_kr.num_srk == 0) || - (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) - return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; - - key_num = hdr->len_kr.srk_sel; - if (key_num == 0 || key_num > hdr->len_kr.num_srk) - return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; - - /* Get revoc key from sfp */ - key_revoc_flag = get_key_revoc(); - ret = is_key_revoked(key_num, key_revoc_flag); - if (ret) - return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; - - size = hdr->len_kr.num_srk * sizeof(struct srk_table); - - memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); - - ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk); - + ret = read_validate_srk_tbl(img); if (ret != 0) return ret; - - img->key_len = img->srk_tbl[key_num - 1].key_len; - - memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), - img->key_len); - key_found = 1; } #endif #if defined(CONFIG_FSL_ISBC_KEY_EXT) if (!key_found && check_ie(img)) { - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; - ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; - if (ie_info->num_keys == 0 || ie_info->num_keys > 32) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; - - ie_num = hdr->ie_key_sel; - if (ie_num == 0 || ie_num > ie_info->num_keys) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; - - ie_revoc_flag = ie_info->key_revok; - if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) - return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; - - ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; - - if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) || - (ie_key_len == 2 * KEY_SIZE_BYTES / 2) || - (ie_key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; - - memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), - ie_key_len); - - img->key_len = ie_key_len; + ret = read_validate_ie_tbl(img); + if (ret != 0) + return ret; key_found = 1; } #endif if (key_found == 0) { - /* check key length */ - if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) || - (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) || - (hdr->key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; - - memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); - - img->key_len = hdr->key_len; - + ret = read_validate_single_key(img); + if (ret != 0) + return ret; key_found = 1; } @@ -698,27 +732,73 @@ static inline int str2longbe(const char *p, ulong *num) return *p != '\0' && *endptr == '\0'; } +/* Function to calculate the ESBC Image Hash + * and hash from Digital signature. + * The Two hash's are compared to yield the + * result of signature validation. + */ +static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) +{ + int ret; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + ret = calc_esbchdr_esbc_hash(img); + if (ret) + return ret; + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) + return ret; + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) + if (ret) + return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; + + return 0; +} + +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_addr) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; - ulong addr = simple_strtoul(argv[1], NULL, 16); struct fsl_secboot_img_priv *img; struct fsl_secboot_img_hdr *hdr; void *esbc; int ret, i, hash_cmd = 0; u32 srk_hash[8]; - uint32_t key_len; - struct key_prop prop; -#if !defined(USE_HOSTCC) - struct udevice *mod_exp_dev; -#endif - if (argc == 3) { - char *cp = argv[2]; + if (arg_hash_str != NULL) { + const char *cp = arg_hash_str; int i = 0; if (*cp == '0' && *(cp + 1) == 'x') @@ -731,7 +811,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, */ if (strlen(cp) != SHA256_NIBBLES) { printf("%s is not a 256 bits hex string as expected\n", - argv[2]); + arg_hash_str); return -1; } @@ -741,7 +821,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, hash_str[NUM_HEX_CHARS] = '\0'; if (!str2longbe(hash_str, &hash[i])) { printf("%s is not a 256 bits hex string ", - argv[2]); + arg_hash_str); return -1; } } @@ -756,9 +836,11 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + /* Update the information in Private Struct */ hdr = &img->hdr; - img->ehdrloc = addr; - esbc = (u8 *)(uintptr_t)img->ehdrloc; + img->ehdrloc = haddr; + img->img_addr = img_addr; + esbc = (u8 *)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); @@ -800,51 +882,12 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, goto exit; } - ret = calc_esbchdr_esbc_hash(img); + ret = calculate_cmp_img_sig(img); if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* Construct encoded hash EM' wrt PKCSv1.5 */ - construct_img_encoded_hash_second(img); - - /* Fill prop structure for public key */ - memset(&prop, 0, sizeof(struct key_prop)); - key_len = get_key_len(img) / 2; - prop.modulus = img->img_key; - prop.public_exponent = img->img_key + key_len; - prop.num_bits = key_len * 8; - prop.exp_len = key_len; - - ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); - if (ret) { - printf("RSA: Can't find Modular Exp implementation\n"); - return -EINVAL; - } - - ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, - &prop, img->img_encoded_hash); - if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* - * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 - * memcmp returns zero on success - * memcmp returns non-zero on failure - */ - ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, - img->hdr.sign_len); - - if (ret) { - fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM); + fsl_secboot_handle_error(ret); goto exit; } - printf("esbc_validate command successful\n"); - exit: - return 0; + return ret; } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 9f6b0e7f31..113295f64a 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -216,6 +216,39 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #else printf("Not implemented\n"); #endif + } else if (strcmp(argv[1], "sd") == 0) { +#ifdef QIXIS_LBMAP_SD + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD); + set_rcw_src(QIXIS_RCW_SRC_SD); + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "sd_qspi") == 0) { +#ifdef QIXIS_LBMAP_SD_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD_QSPI); + set_rcw_src(QIXIS_RCW_SRC_SD); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "qspi") == 0) { +#ifdef QIXIS_LBMAP_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_QSPI); + set_rcw_src(QIXIS_RCW_SRC_QSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; @@ -255,6 +288,9 @@ U_BOOT_CMD( "- hard reset to default bank\n" "qixis_reset altbank - reset to alternate bank\n" "qixis_reset nand - reset to nand\n" + "qixis_reset sd - reset to sd\n" + "qixis_reset sd_qspi - reset to sd with qspi support\n" + "qixis_reset qspi - reset to qspi\n" "qixis watchdog <watchdog_period> - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" "qixis_reset dump - display the QIXIS registers\n" diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index 022f38b117..e55a03090a 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -29,7 +29,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 1; /* read out the first block, get the config data information */ - n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); if (!n) { free(tmp_buf); return 1; diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index f1bed51d30..1bd65a8e55 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void) * The IR chip can show up under the following addresses: * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) * 0x09 (Verified on T1040RDB-PA) - * 0x38 (Verified on T2080QDS, T2081QDS) + * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) */ static int find_ir_chip_on_i2c(void) { @@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override) (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif u32 fusesr; - u8 vid; + u8 vid, buf; int vdd_target, vdd_current, vdd_last; int ret, i2caddress; unsigned long vdd_string_override; @@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } + /* check IR chip work on Intel mode*/ + ret = i2c_read(i2caddress, + IR36021_INTEL_MODE_OOFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } + /* get the voltage ID from fuse status register */ fusesr = in_be32(&gur->dcfg_fusesr); /* diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index a9c7bb4790..9182c20bc9 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -11,6 +11,10 @@ #define IR36021_LOOP1_VOUT_OFFSET 0x9A #define IR36021_MFR_ID_OFFSET 0x92 #define IR36021_MFR_ID 0x43 +#define IR36021_INTEL_MODE_OOFSET 0x14 +#define IR36021_MODE_MASK 0x20 +#define IR36021_INTEL_MODE 0x00 +#define IR36021_AMD_MODE 0x20 /* step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 6f0fea1a35..f41985d2f6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -125,11 +124,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index e7e893a1ae..f3ba41a5fd 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 172a55b988..55437e843d 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -170,7 +170,7 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname) bus->read = hydra_mdio_read; bus->write = hydra_mdio_write; bus->reset = hydra_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); hmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 62b163580b..3f11f5f279 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -175,7 +175,7 @@ static int super_hydra_mdio_init(char *realbusname, char *fakebusname) bus->read = super_hydra_mdio_read; bus->write = super_hydra_mdio_write; bus->reset = super_hydra_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); hmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c index 4dead9c045..20785b1bb3 100644 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index d572a5fbed..f470306135 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c index 9aaf6db997..9747d904b2 100644 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c index 9aaf6db997..9747d904b2 100644 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009-2010 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c index be351befec..bf3e08a8cf 100644 --- a/board/freescale/ls1021aqds/eth.c +++ b/board/freescale/ls1021aqds/eth.c @@ -113,7 +113,7 @@ static int ls1021a_mdio_init(char *realbusname, char *fakebusname) bus->read = ls1021a_mdio_read; bus->write = ls1021a_mdio_write; bus->reset = ls1021a_mdio_reset; - sprintf(bus->name, fakebusname); + strcpy(bus->name, fakebusname); lsmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index be3358a564..5f4ec9d878 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -22,6 +22,7 @@ #include <fsl_sec.h> #include <spl.h> #include <fsl_devdis.h> +#include <fsl_validate.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -369,6 +370,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index f82e567c84..616e0bfd39 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -30,6 +30,7 @@ #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif +#include <fsl_validate.h> DECLARE_GLOBAL_DATA_PTR; @@ -549,6 +550,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 0c7f648b6c..65a0af1930 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -7,3 +7,5 @@ F: configs/ls1043aqds_defconfig F: configs/ls1043aqds_nor_ddr3_defconfig F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig +F: configs/ls1043aqds_sdcard_qspi_defconfig +F: configs/ls1043aqds_qspi_defconfig diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 6261a778aa..a6fd7a35f5 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -94,3 +94,4 @@ a) Promjet Boot b) NOR boot c) NAND boot d) SD boot +e) QSPI boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 42d906824a..3d3c53385a 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -132,9 +132,22 @@ void dram_init_banksize(void) * The address needs to add the offset of its bank. */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index b7fc360e2c..88b10a0f2f 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -136,7 +136,7 @@ static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) bus->read = ls1043aqds_mdio_read; bus->write = ls1043aqds_mdio_write; bus->reset = ls1043aqds_mdio_reset; - sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index d6696ca812..01db078222 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -40,11 +40,14 @@ enum { #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x1 int checkboard(void) { char buf[64]; -#ifndef CONFIG_SD_BOOT +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -52,6 +55,8 @@ int checkboard(void) #ifdef CONFIG_SD_BOOT puts("SD\n"); +#elif defined(CONFIG_QSPI_BOOT) + puts("QSPI\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -218,7 +223,17 @@ void board_retimer_init(void) int board_early_init_f(void) { +#ifdef CONFIG_LPUART + u8 uart; +#endif fsl_lsch2_early_init_f(); +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif return 0; } @@ -303,6 +318,16 @@ int board_init(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..7783521b95 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +20124000 00001100 00000096 00000001 diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 0637ecf2a7..ebc9d47468 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -412,7 +412,7 @@ static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) bus->read = ls2080a_qds_mdio_read; bus->write = ls2080a_qds_mdio_write; bus->reset = ls2080a_qds_mdio_reset; - sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/m5208evbe/config.mk b/board/freescale/m5208evbe/config.mk deleted file mode 100644 index c15a9cfba6..0000000000 --- a/board/freescale/m5208evbe/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk deleted file mode 100644 index 1af25e158a..0000000000 --- a/board/freescale/m5249evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5253demo/config.mk b/board/freescale/m5253demo/config.mk deleted file mode 100644 index 45474652a8..0000000000 --- a/board/freescale/m5253demo/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk deleted file mode 100644 index 1af25e158a..0000000000 --- a/board/freescale/m5253evbe/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5272c3/config.mk b/board/freescale/m5272c3/config.mk deleted file mode 100644 index 1af25e158a..0000000000 --- a/board/freescale/m5272c3/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5275evb/config.mk b/board/freescale/m5275evb/config.mk deleted file mode 100644 index 1af25e158a..0000000000 --- a/board/freescale/m5275evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5282evb/config.mk b/board/freescale/m5282evb/config.mk deleted file mode 100644 index e2ac27e86f..0000000000 --- a/board/freescale/m5282evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFFE00000 diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk deleted file mode 100644 index c15a9cfba6..0000000000 --- a/board/freescale/m53017evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk deleted file mode 100644 index c15a9cfba6..0000000000 --- a/board/freescale/m5329evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m5373evb/config.mk b/board/freescale/m5373evb/config.mk deleted file mode 100644 index c15a9cfba6..0000000000 --- a/board/freescale/m5373evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0 diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk deleted file mode 100644 index 07f52e0255..0000000000 --- a/board/freescale/m54418twr/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2010-2012 Freescale Semiconductor, Inc. -# TsiChung Liew (Tsi-Chung.Liew@freescale.com) -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m547xevb/config.mk b/board/freescale/m547xevb/config.mk deleted file mode 100644 index 45474652a8..0000000000 --- a/board/freescale/m547xevb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/m548xevb/config.mk b/board/freescale/m548xevb/config.mk deleted file mode 100644 index 45474652a8..0000000000 --- a/board/freescale/m548xevb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xFF800000 diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index ebe3ba460c..f269feb08e 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 41d4cfe738..10fb2b3d60 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index d2ac6c4ad4..e438737065 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index aa30cabb03..93c7f4b8c9 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index b31ea3432e..0d5783ae04 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index d2ac6c4ad4..e438737065 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 41d4cfe738..10fb2b3d60 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 6db92ef2da..cb3b707a47 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index ef404b1d6f..89e9297262 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2009 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 2bfc1a170c..524ed60903 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index aa30cabb03..93c7f4b8c9 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 7cd0395651..00670bc5a7 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008,2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile index 0b288f2588..02085b6b7e 100644 --- a/board/freescale/mx25pdk/Makefile +++ b/board/freescale/mx25pdk/Makefile @@ -7,4 +7,3 @@ # obj-y := mx25pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx25pdk/lowlevel_init.S b/board/freescale/mx25pdk/lowlevel_init.S deleted file mode 100644 index 8c581b50c6..0000000000 --- a/board/freescale/mx25pdk/lowlevel_init.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2011 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.globl lowlevel_init -lowlevel_init: - - mov pc, lr diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 01dac72e85..788d3c3e35 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -186,3 +186,6 @@ int checkboard(void) return 0; } + +/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */ +void lowlevel_init(void) {} diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index f8ae9733fc..bbcc5bb0c6 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -47,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_PAD_CTRL \ (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ @@ -196,6 +199,38 @@ static void iox74lv_init(void) gpio_direction_output(IOX_STCP, 1); }; +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -503,6 +538,10 @@ int board_init(void) setup_fec(); #endif +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + #ifdef CONFIG_VIDEO_MXS setup_lcd(); #endif diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 946d5032e7..1f3793b853 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index b8bbcdf2a8..b2493e1f61 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index e600bdbc2a..c6a724217f 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -140,8 +139,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); - setup_portals(); board_config_lanes_mux(); return 0; diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c index 99c23f79f4..ca54e2a4f0 100644 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -148,7 +148,7 @@ static int t1024qds_mdio_init(char *realbusname, u8 muxval) bus->read = t1024qds_mdio_read; bus->write = t1024qds_mdio_write; bus->reset = t1024qds_mdio_reset; - sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index 708afcaebf..76793a1186 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -280,10 +279,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index fddd240f98..01dbf381bd 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" @@ -151,10 +150,6 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif #ifdef CONFIG_T1024RDB board_mux_lane(); #endif diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 8bf34fa79a..872e6e8228 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -162,7 +162,7 @@ static int t1040_qds_mdio_init(char *realbusname, u8 muxval) bus->read = t1040_qds_mdio_read; bus->write = t1040_qds_mdio_write; bus->reset = t1040_qds_mdio_reset; - sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index eaca57fc5d..d7d56b47c8 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -153,10 +152,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 322765288b..ec97677df8 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -16,7 +16,6 @@ #include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "../common/sleep.h" @@ -84,11 +83,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index 3348971b01..f1aff5481e 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 1c0ce2492c..f08cff2654 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -176,7 +176,7 @@ static int t208xqds_mdio_init(char *realbusname, u8 muxval) bus->read = t208xqds_mdio_read; bus->write = t208xqds_mdio_write; bus->reset = t208xqds_mdio_reset; - sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 7c89cd5ee9..bfea3a1556 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -356,11 +355,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 8a26276273..053f128e5b 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 0c2c1c565b..0cb05aa03f 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t208xrdb.h" @@ -81,11 +80,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7abd38def1..62d58c5b1f 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2012 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 2dfdcbbd39..83a3a9bba2 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -153,7 +153,7 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval) bus->read = t4240qds_mdio_read; bus->write = t4240qds_mdio_write; bus->reset = t4240qds_mdio_reset; - sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c index 54410943f2..f1393f25f9 100644 --- a/board/freescale/t4qds/t4240emu.c +++ b/board/freescale/t4qds/t4240emu.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,11 +55,6 @@ int board_early_init_r(void) MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 4f2cccd709..d6df144730 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -552,11 +551,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index fac442bfc8..406fb132ae 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -15,12 +15,12 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t4rdb.h" #include "cpld.h" +#include "../common/vid.h" DECLARE_GLOBAL_DATA_PTR; @@ -75,10 +75,12 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); return 0; } diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index 1d6eb7bd55..262ead5516 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -80,7 +80,7 @@ int ihs_mdio_init(struct ihs_mdio_info *info) bus->read = ihs_mdio_read; bus->write = ihs_mdio_write; bus->reset = ihs_mdio_reset; - sprintf(bus->name, info->name); + strcpy(bus->name, info->name); bus->priv = info; diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 11d075c385..2c6c698fb3 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -2,20 +2,7 @@ * (C) Copyright 2013 * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ /* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */ @@ -232,7 +219,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) ofs = src % blk_len; if (ofs) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, tmp_buf); if (!n) goto failure; @@ -243,7 +230,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) } cnt = size / blk_len; if (cnt) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt, dst); if (n != cnt) goto failure; @@ -253,7 +240,7 @@ static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size) block_no += cnt; } if (size) { - n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1, + n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1, tmp_buf); if (!n) goto failure; diff --git a/board/gdsys/p1022/controlcenterd-id.h b/board/gdsys/p1022/controlcenterd-id.h index de4770ac8d..b6f47028fd 100644 --- a/board/gdsys/p1022/controlcenterd-id.h +++ b/board/gdsys/p1022/controlcenterd-id.h @@ -2,20 +2,7 @@ * (C) Copyright 2013 * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONTROLCENTER_ID_H diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c index 7596736bfd..58f63f3ac3 100644 --- a/board/gdsys/p1022/ddr.c +++ b/board/gdsys/p1022/ddr.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/diu.c b/board/gdsys/p1022/diu.c index 52ac1e6ecc..af0608bdd2 100644 --- a/board/gdsys/p1022/diu.c +++ b/board/gdsys/p1022/diu.c @@ -4,10 +4,7 @@ * * FSL DIU Framebuffer driver * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/law.c b/board/gdsys/p1022/law.c index 96f38f7c6f..1438d9fb6f 100644 --- a/board/gdsys/p1022/law.c +++ b/board/gdsys/p1022/law.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c index fd0e910d7b..6a4a6ef6af 100644 --- a/board/gdsys/p1022/sdhc_boot.c +++ b/board/gdsys/p1022/sdhc_boot.c @@ -43,7 +43,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 1; /* read out the first block, get the config data information */ - n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); if (!n) { free(tmp_buf); return 1; diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c index 9cad692783..aee86a4356 100644 --- a/board/gdsys/p1022/tlb.c +++ b/board/gdsys/p1022/tlb.c @@ -3,10 +3,7 @@ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 6b139392b5..fa12f338de 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1b97a8fea8..d12d74202c 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -14,14 +14,6 @@ int arch_early_init_r(void) { - struct udevice *dev; - int ret; - - /* Make sure the platform controller hub is up and running */ - ret = uclass_get_device(UCLASS_PCH, 0, &dev); - if (ret) - return ret; - return 0; } diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index ae96d23d03..2af3aa9e74 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c index 00153232f6..1578a33fd1 100644 --- a/board/highbank/ahci.c +++ b/board/highbank/ahci.c @@ -1,18 +1,7 @@ /* * Copyright 2012 Calxeda, Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 79562f79a8..cae4a21c3d 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -53,8 +53,9 @@ static void malta_lcd_puts(const char *str) static enum core_card malta_core_card(void) { u32 corid, rev; + const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); - rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); + rev = __raw_readl(reg); corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; switch (corid) { diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 57b89e0ba6..e2fce50208 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -101,6 +101,19 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif #if defined(CONFIG_CMD_NET) + +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -110,8 +123,8 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -121,15 +134,7 @@ static void setup_net_chip(void) writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } + reset_net_chip(64); } #else static inline void setup_net_chip(void) {} @@ -200,10 +205,10 @@ void set_muxconf_regs(void) #if defined(CONFIG_CMD_NET) int board_eth_init(bd_t *bis) { - int rc = 0; #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; #endif - return rc; } #endif diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 8de129dc83..a42f3eca33 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -168,7 +168,7 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, printf("can't get the IVM_Boardid\n"); return 1; } - sprintf((char *)buf, "%s", p); + strcpy((char *)buf, p); setenv("boardid", (char *)buf); printf("set boardid=%s\n", buf); @@ -177,7 +177,7 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, printf("can't get the IVM_HWKey\n"); return 1; } - sprintf((char *)buf, "%s", p); + strcpy((char *)buf, p); setenv("hwkey", (char *)buf); printf("set hwkey=%s\n", buf); printf("Execute manually saveenv for persistent storage.\n"); diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/kylin/kylin_rk3036/kylin_rk3036.c index 40d6b521bc..2a258710ac 100644 --- a/board/kylin/kylin_rk3036/kylin_rk3036.c +++ b/board/kylin/kylin_rk3036/kylin_rk3036.c @@ -8,10 +8,14 @@ #include <dm.h> #include <asm/io.h> #include <asm/arch/uart.h> +#include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch/sdram_rk3036.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; +#define GRF_BASE 0x20008000 + void get_ddr_config(struct rk3036_ddr_config *config) { /* K4B4G1646Q config */ @@ -28,6 +32,34 @@ void get_ddr_config(struct rk3036_ddr_config *config) config->bw = 1; } +#define FASTBOOT_KEY_GPIO 93 + +int fastboot_key_pressed(void) +{ + gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key"); + gpio_direction_input(FASTBOOT_KEY_GPIO); + return !gpio_get_value(FASTBOOT_KEY_GPIO); +} + +#define ROCKCHIP_BOOT_MODE_FASTBOOT 0x5242C309 + +int board_late_init(void) +{ + struct rk3036_grf * const grf = (void *)GRF_BASE; + int boot_mode = readl(&grf->os_reg[4]); + + /* Clear boot mode */ + writel(0, &grf->os_reg[4]); + + if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT || + fastboot_key_pressed()) { + printf("enter fastboot!\n"); + setenv("preboot", "setenv preboot; fastboot usb0"); + } + + return 0; +} + int board_init(void) { return 0; diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h index b2a09b3cd0..e5d0774e78 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lge/sniper/sniper.h @@ -51,13 +51,13 @@ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \ /* GPMC */ \ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ - MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ + MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\ - MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ + MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\ MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\ MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\ @@ -129,7 +129,7 @@ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \ MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \ @@ -156,12 +156,12 @@ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \ /* MMC1 */ \ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \ + MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ @@ -183,15 +183,15 @@ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \ /* UART2 */ \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \ /* UART1 */ \ - MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \ - MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \ /* MCBSP4 */ \ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \ @@ -227,11 +227,11 @@ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \ /* I2C2 */ \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \ /* I2C3 */ \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \ /* I2C4 */ \ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \ @@ -242,13 +242,13 @@ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ - MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \ - MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ + MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \ /* SYS */ \ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \ @@ -262,25 +262,25 @@ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \ /* JTAG */ \ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \ /* ETK */ \ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \ @@ -330,7 +330,7 @@ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \ MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \ - MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \ + MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \ MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \ MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \ @@ -355,8 +355,8 @@ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \ diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig deleted file mode 100644 index 2edccfea53..0000000000 --- a/board/maxbcm/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MAXBCM - -config SYS_BOARD - default "maxbcm" - -config SYS_CONFIG_NAME - default "maxbcm" - -endif diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg index cc05792556..1f748db37c 100644 --- a/board/maxbcm/kwbimage.cfg +++ b/board/maxbcm/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl.bin 0000005b 00000068 +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index 119ba4c6c8..db6ad99efe 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -138,17 +138,15 @@ int checkboard(void) return 0; } -#ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E6185 switch */ -void reset_phy(void) +int board_phy_config(struct phy_device *phydev) { - char *name = "neta0"; - - if (miiphy_set_current_dev(name)) - return; - - /* todo: fill this with the real setup / config code */ - - printf("88E6185 Initialized on %s\n", name); + /* + * todo: + * Fill this with the real setup / config code. + * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c + * for details. + */ + printf("88E6185 Initialized\n"); + return 0; } -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk deleted file mode 100644 index 354d918474..0000000000 --- a/board/micronas/vct/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# vct_xxx boards with MIPS 4Kc CPU core -# - -ifndef CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE = 0x87000000 -endif diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h index 0a1c5fcb82..67da6a8e73 100644 --- a/board/micronas/vct/vct.h +++ b/board/micronas/vct/vct.h @@ -80,12 +80,14 @@ void vct_pin_mux_initialize(void); */ static inline void reg_write(u32 addr, u32 data) { - __raw_writel(data, addr + REG_GLOBAL_START_ADDR); + void *reg = (void *)(addr + REG_GLOBAL_START_ADDR); + __raw_writel(data, reg); } static inline u32 reg_read(u32 addr) { - return __raw_readl(addr + REG_GLOBAL_START_ADDR); + const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR); + return __raw_readl(reg); } #endif /* _VCT_H */ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 6b96bd526e..226217570c 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -698,12 +698,12 @@ void video_get_info_str (int line_number, char *info) s=getenv ("serial#"); #ifdef CONFIG_PIP405 if (!s || strncmp (s, "PIP405", 6)) { - sprintf(buf,"### No HW ID - assuming PIP405"); + strcpy(buf,"### No HW ID - assuming PIP405"); } #endif #ifdef CONFIG_MIP405 if (!s || strncmp (s, "MIP405", 6)) { - sprintf(buf,"### No HW ID - assuming MIP405"); + strcpy(buf,"### No HW ID - assuming MIP405"); } #endif else { @@ -718,7 +718,7 @@ void video_get_info_str (int line_number, char *info) } buf[i++] = *s; } - sprintf(&buf[i]," SN "); + strcpy(&buf[i]," SN "); i+=4; for (; s < e; ++s) { buf[i++] = *s; @@ -744,7 +744,7 @@ void video_get_info_str (int line_number, char *info) ctfb.modeIdent); return; case 1: - sprintf (buf, "%s",CONFIG_IDENT_STRING); + strcpy(buf, CONFIG_IDENT_STRING); sprintf (info, " %s", &buf[1]); return; } diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h index 255e4cd82b..c21c30c598 100644 --- a/board/nvidia/cardhu/pinmux-config-cardhu.h +++ b/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_CARDHU_H_ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index d7c1a695ff..e4c4bfbc68 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 891ac07dd9..294731e96c 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_DALMORE_H_ diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 6f189aa74e..14f0ce5455 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -57,19 +57,6 @@ int tegra_pcie_board_init(void) return err; } - err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | - AS3722_GPIO_INVERT); - if (err < 0) { - error("failed to configure GPIO#1 as output: %d\n", err); - return err; - } - - err = as3722_gpio_direction_output(pmic, 2, 1); - if (err < 0) { - error("failed to set GPIO#2 high: %d\n", err); - return err; - } - return 0; } #endif /* PCI */ diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk deleted file mode 100644 index 8f13301159..0000000000 --- a/board/pb1x00/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMD development board AMD Alchemy Pb1x00, MIPS32 core -# - -# ROM version -#CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# SDRAM version -CONFIG_SYS_TEXT_BASE = 0x83800000 diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index b145e438f0..98d9536a7d 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -1,8 +1,8 @@ /* Memory sub-system initialization code */ #include <config.h> +#include <mach/au1x00.h> #include <asm/regdef.h> -#include <asm/au1x00.h> #include <asm/mipsregs.h> #define AU1500_SYS_ADDR 0xB1900000 diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 34814c47cb..eb92914a79 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> -#include <asm/au1x00.h> +#include <mach/au1x00.h> #include <asm/mipsregs.h> #include <asm/io.h> diff --git a/board/radxa/rock2/Kconfig b/board/radxa/rock2/Kconfig new file mode 100644 index 0000000000..c2ff9e9963 --- /dev/null +++ b/board/radxa/rock2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK2 + +config SYS_BOARD + default "rock2" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock2" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS new file mode 100644 index 0000000000..a697e68281 --- /dev/null +++ b/board/radxa/rock2/MAINTAINERS @@ -0,0 +1,6 @@ +FIREFLY +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/radxa/rock2 +F: include/configs/rock2.h +F: configs/rock2_defconfig diff --git a/board/radxa/rock2/Makefile b/board/radxa/rock2/Makefile new file mode 100644 index 0000000000..caa305bbb5 --- /dev/null +++ b/board/radxa/rock2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rock2.o diff --git a/board/radxa/rock2/rock2.c b/board/radxa/rock2/rock2.c new file mode 100644 index 0000000000..5119e95455 --- /dev/null +++ b/board/radxa/rock2/rock2.c @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index 9f6494561c..52a1906c7f 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -113,6 +113,7 @@ static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) writel(val, ðer->malr); } +#if defined(CONFIG_SH_32BIT) /***************************************************************** * This PMB must be set on this timing. The lowlevel_init is run on * Area 0(phys 0x00000000), so we have to map it. @@ -154,13 +155,16 @@ static void set_pmb_on_board_init(void) writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); } +#endif int board_init(void) { struct gether_control_regs *gether = GETHER_CONTROL_BASE; init_gpio(); +#if defined(CONFIG_SH_32BIT) set_pmb_on_board_init(); +#endif /* Sets TXnDLY to B'010 */ writel(0x00000202, &gether->gbecont); diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index c25b486f4a..426ae14af2 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -355,10 +355,10 @@ int exynos_init(void) } /* Request soft I2C gpios */ - sprintf(buf, "soft_i2c_scl"); + strcpy(buf, "soft_i2c_scl"); gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf); - sprintf(buf, "soft_i2c_sda"); + strcpy(buf, "soft_i2c_sda"); gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf); check_hw_revision(); diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 592f7728c0..b41e9decb3 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -47,23 +47,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ -#ifdef CONFIG_VIDEO_SANDBOX_SDL - int ret; - - ret = sandbox_lcd_sdl_early_init(); - if (ret) { - puts("Could not init sandbox LCD emulation\n"); - return ret; - } -#endif - - return 0; -} -#endif - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 24cc776a25..2ffafa8582 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index b31ea3432e..0d5783ae04 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index f94e3e5736..b3c666c054 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -480,7 +480,7 @@ int board_late_init(void) sprintf(tmp, "%s_%s", factory_dat.asn, factory_dat.comp_version); else - sprintf(tmp, "QMX7.E38_4.0"); + strcpy(tmp, "QMX7.E38_4.0"); ret = setenv("boardid", tmp); if (ret) diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 6bad4da394..fe8a8bfb69 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS new file mode 100644 index 0000000000..298e5011c7 --- /dev/null +++ b/board/solidrun/clearfog/MAINTAINERS @@ -0,0 +1,6 @@ +CLEARFOG BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/soldrun/clearfog/ +F: include/configs/clearfog.h +F: configs/clearfog_defconfig diff --git a/board/solidrun/clearfog/Makefile b/board/solidrun/clearfog/Makefile new file mode 100644 index 0000000000..1920d6bf6d --- /dev/null +++ b/board/solidrun/clearfog/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := clearfog.o diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README new file mode 100644 index 0000000000..2cfa5bfc86 --- /dev/null +++ b/board/solidrun/clearfog/README @@ -0,0 +1,18 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +Generate the U-Boot image with these commands: + +$ make clearfog_defconfig +$ make + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +Now all you need to do is copy this image on a SD card. +For example with this command: + +$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 + +Please use the correct device node for your setup instead +of "/dev/sdX" here! diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c new file mode 100644 index 0000000000..2773f5957e --- /dev/null +++ b/board/solidrun/clearfog/clearfog.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-15t1-clearfog" + */ +#define BOARD_GPP_OUT_ENA_LOW 0xffffffff +#define BOARD_GPP_OUT_ENA_MID 0xffffffff + +#define BOARD_GPP_OUT_VAL_LOW 0x0 +#define BOARD_GPP_OUT_VAL_MID 0x0 +#define BOARD_GPP_POL_LOW 0x0 +#define BOARD_GPP_POL_MID 0x0 + +/* IO expander on Marvell GP board includes e.g. fan enabling */ +struct marvell_io_exp { + u8 chip; + u8 addr; + u8 val; +}; + +static struct marvell_io_exp io_exp[] = { + { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */ + { 0x20, 6, 0xf9 }, + { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */ + { 0x20, 6, 0xb9 }, + { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */ + { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */ +}; + +static struct serdes_map board_serdes_map[] = { + {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, +}; + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + *serdes_map_array = board_serdes_map; + *count = ARRAY_SIZE(board_serdes_map); + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map board_topology_map = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_LOW} }, /* temperature */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x10400011, MVEBU_MPP_BASE + 0x08); + writel(0x22043333, MVEBU_MPP_BASE + 0x0c); + writel(0x44400002, MVEBU_MPP_BASE + 0x10); + writel(0x41144004, MVEBU_MPP_BASE + 0x14); + writel(0x40333333, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + int i; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Toggle GPIO41 to reset onboard switch and phy */ + clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); + mdelay(1); + setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + mdelay(10); + + /* Init I2C IO expanders */ + for (i = 0; i < ARRAY_SIZE(io_exp); i++) + i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); + + return 0; +} + +int checkboard(void) +{ + puts("Board: SolidRun ClearFog\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} diff --git a/board/solidrun/clearfog/kwbimage.cfg b/board/solidrun/clearfog/kwbimage.cfg new file mode 100644 index 0000000000..c650c2c65e --- /dev/null +++ b/board/solidrun/clearfog/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM sdio + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 9d67847850..a334aa336d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -71,8 +71,11 @@ config MACH_SUN8I_A33 config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" @@ -92,6 +95,12 @@ config MACH_SUN8I bool default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T +config DRAM_TYPE + int "sunxi dram type" + depends on MACH_SUN8I_A83T + default 3 + ---help--- + Set the dram type, 3: DDR3, 7: LPDDR3 config DRAM_CLK int "sunxi dram clock speed" @@ -363,6 +372,12 @@ config I2C3_ENABLE See I2C0_ENABLE help text. endif +config R_I2C_ENABLE + bool "Enable the PRCM I2C/TWI controller" + default n + ---help--- + Set this to y to enable the I2C controller which is part of the PRCM. + if MACH_SUN7I config I2C4_ENABLE bool "Enable I2C/TWI controller 4" diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 131c3415aa..739b6fdc88 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -183,6 +183,11 @@ S: Maintained F: configs/Sinlinx_SinA33_defconfig W: http://linux-sunxi.org/Sinlinx_SinA33 +SINOVOIP BPI M3 A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/Sinovoip_BPI_M3_defconfig + WEXLER-TAB7200 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 386e2e04c2..420481a9fb 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -422,6 +422,12 @@ void i2c_init_board(void) clock_twi_onoff(4, 1); #endif #endif + +#ifdef CONFIG_R_I2C_ENABLE + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif } #ifdef CONFIG_SPL_BUILD @@ -446,24 +452,22 @@ void sunxi_board_init(void) power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif -#ifndef CONFIG_AXP818_POWER power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); -#endif -#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER) +#if !defined(CONFIG_AXP152_POWER) power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); #endif #ifdef CONFIG_AXP209_POWER power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif -#ifdef CONFIG_AXP221_POWER - power_failed |= axp_set_dldo1(CONFIG_AXP_DLDO1_VOLT); - power_failed |= axp_set_dldo2(CONFIG_AXP_DLDO2_VOLT); - power_failed |= axp_set_dldo3(CONFIG_AXP_DLDO3_VOLT); - power_failed |= axp_set_dldo4(CONFIG_AXP_DLDO4_VOLT); +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); + power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); + power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); + power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); diff --git a/board/sysam/amcore/config.mk b/board/sysam/amcore/config.mk deleted file mode 100644 index d01a8bb567..0000000000 --- a/board/sysam/amcore/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffc00000 diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS new file mode 100644 index 0000000000..5ae6b6487c --- /dev/null +++ b/board/theadorable/MAINTAINERS @@ -0,0 +1,7 @@ +THEADORABLE BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/theadorable/ +F: include/configs/theadorable.h +F: configs/theadorable_debug_defconfig +F: configs/theadorable_defconfig diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile new file mode 100644 index 0000000000..9d5b39e696 --- /dev/null +++ b/board/theadorable/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := theadorable.o diff --git a/board/theadorable/kwbimage.cfg b/board/theadorable/kwbimage.cfg new file mode 100644 index 0000000000..4f3b7b23f3 --- /dev/null +++ b/board/theadorable/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c new file mode 100644 index 0000000000..0e232656fc --- /dev/null +++ b/board/theadorable/theadorable.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_NET +#include <netdev.h> +#endif + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 +#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 +#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) + +#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f +#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c +#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 + +/* DDR3 static configuration */ +static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /* Dunit Control Low Register */ + {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ + {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ + {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ + {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ + {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ + {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ + + {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ + {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ + {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ + {0x000014A8, 0x00000101}, /* AXI Control Register */ + + /* + * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the + * training sequence + */ + {0x000200e8, 0x3fff0e01}, + {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ + + {0x0001504, 0x7fffffe1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x00020220, 0x00000007}, /* Reserved */ + + {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /* MR0 */ + {0x000015D4, 0x00000044}, /* MR1 */ + {0x000015D8, 0x00000010}, /* MR2 */ + {0x000015DC, 0x00000000}, /* MR3 */ + {0x000015E0, 0x00000001}, + {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ + {0x000015EC, 0xf800a225}, /* DDR PHY */ + + /* Recommended Settings from Marvell for 4 x 16 bit devices: */ + {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ + {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ + + {0x0, 0x0} +}; + +static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +/* + * Lane0 - PCIE0.0 X1 (to WIFI Module) + * Lane5 - SATA0 + * Lane6 - SATA1 + * Lane7 - SGMII0 (to Ethernet Phy) + * Lane8-11 - PCIE2.0 X4 (to PEX Switch) + * all other lanes are disabled + */ +MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, + { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, + PEX_BUS_DISABLED }, + 0x0060, serdes_change_m_phy + }, +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + /* Only one mode supported for this board */ + return &board_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &theadorable_serdes_cfg[0]; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x03300000, MVEBU_MPP_BASE + 0x04); + writel(0x00000033, MVEBU_MPP_BASE + 0x08); + writel(0x00000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11110000, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000000, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: theadorable\n"); + + return 0; +} + +#ifdef CONFIG_NET +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} +#endif + +int board_video_init(void) +{ + struct mvebu_lcd_info lcd_info; + + /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ + lcd_info.fb_base = gd->ram_size; + lcd_info.x_res = 240; + lcd_info.x_fp = 1; + lcd_info.x_bp = 45; + lcd_info.y_res = 320; + lcd_info.y_fp = 1; + lcd_info.y_bp = 3; + + return mvebu_lcd_register_init(&lcd_info); +} diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index c988d395c1..16d1a64dc2 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2014, Marcel Ziswiler * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_APALIS_T30_H_ diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index 4e73c0762e..407c6c36e1 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -1,17 +1,7 @@ /* * Copyright (c) 2013-2014, Stefan Agner * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _PINMUX_CONFIG_COLIBRI_T30_H_ diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index d891a3844c..eca218c9cf 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -43,7 +43,7 @@ ulong flash_get_size (ulong base, int banknum); /* Local functions */ static int detect_num_flash_banks(void); static long int get_ddr_bank_size(short cs, long *base); -static void set_cs_bounds(short cs, long base, long size); +static void set_cs_bounds(short cs, ulong base, ulong size); static void set_cs_config(short cs, long config); static void set_ddr_config(void); @@ -314,7 +314,7 @@ static long int get_ddr_bank_size(short cs, long *base) /************************************************************************** * Sets DDR bank CS bounds. */ -static void set_cs_bounds(short cs, long base, long size) +static void set_cs_bounds(short cs, ulong base, ulong size) { debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs); if(size == 0){ diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 638d14f6d0..ac44e32341 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -346,7 +346,7 @@ int board_late_init(void) /* get production data */ if (read_eeprom(&header)) { - sprintf(model, "211"); + strcpy(model, "211"); } else { sprintf(model, "%d", header.SystemId); if (header.SystemId == 215) { diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index 5c5eadc93f..b73dd8100b 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -1,9 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk index 36bdd96343..95ef9c0f06 100644 --- a/board/xilinx/microblaze-generic/config.mk +++ b/board/xilinx/microblaze-generic/config.mk @@ -11,8 +11,6 @@ # the generated file from your Xilinx design flow. # -CONFIG_SYS_TEXT_BASE = 0x29000000 - PLATFORM_CPPFLAGS += -mno-xl-soft-mul PLATFORM_CPPFLAGS += -mno-xl-soft-div PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index dfa6293222..ccd4ec955b 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,7 +12,6 @@ #include <common.h> #include <config.h> #include <fdtdec.h> -#include <netdev.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; static int reset_pin = -1; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) ulong ram_base; void dram_init_banksize(void) @@ -58,14 +56,6 @@ int dram_init(void) return 0; }; -#else -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} -#endif int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int gpio_init (void) +static int gpio_init(void) { #ifdef CONFIG_XILINX_GPIO reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); @@ -96,32 +86,9 @@ int gpio_init (void) return 0; } -void board_init(void) +int board_late_init(void) { gpio_init(); -} -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif - -#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - - return ret; + return 0; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 8ba146cb88..ccb528ed92 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -28,15 +28,6 @@ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 @@ -44,18 +35,6 @@ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig deleted file mode 100644 index d580a7beaf..0000000000 --- a/board/xilinx/ml507/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ML507 - -config SYS_BOARD - default "ml507" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "ml507" - -endif diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS deleted file mode 100644 index 8b40f44500..0000000000 --- a/board/xilinx/ml507/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ML507 BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/xilinx/ml507/ -F: include/configs/ml507.h -F: configs/ml507_defconfig -F: configs/ml507_flash_defconfig diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile deleted file mode 100644 index 9a3809f3c0..0000000000 --- a/board/xilinx/ml507/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ml507.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c deleted file mode 100644 index 83b764b733..0000000000 --- a/board/xilinx/ml507/ml507.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Xilinx ML507 Board\n"); - return 0; -} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h deleted file mode 100644 index e30e592bbe..0000000000 --- a/board/xilinx/ml507/xparameters.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS index 2b0c98dc8b..ba48f50c29 100644 --- a/board/xilinx/ppc405-generic/MAINTAINERS +++ b/board/xilinx/ppc405-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC405-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc405-generic/ F: include/configs/xilinx-ppc405-generic.h diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index c9da870657..2800f68626 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -3,10 +3,10 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o +obj-y += xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index e3dd468f1e..3729f07624 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -10,39 +10,32 @@ #include <common.h> #include <asm/processor.h> -ulong __get_PCI_freq(void) +ulong get_PCI_freq(void) { return 0; } -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC405 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index f0ff78fca5..c3df9e5109 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -14,12 +14,11 @@ #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 #define XPAR_INTC_0_BASEADDR 0x81800000 #define XPAR_SPI_0_BASEADDR 0x83400000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 #define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS index 2d0b11af91..0258c8204a 100644 --- a/board/xilinx/ppc440-generic/MAINTAINERS +++ b/board/xilinx/ppc440-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC440-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc440-generic/ F: include/configs/xilinx-ppc440-generic.h diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 0acd95d6e4..4d5f41029a 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -3,11 +3,11 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o -extra-y += ../../xilinx/ppc440-generic/init.o +obj-y += xilinx_ppc440_generic.o +extra-y += init.o diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S index 4598a37684..f9ff35f51b 100644 --- a/board/xilinx/ppc440-generic/init.S +++ b/board/xilinx/ppc440-generic/init.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 74df2f4ff7..d823352930 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -8,34 +8,51 @@ #include <config.h> #include <common.h> +#include <netdev.h> #include <asm/processor.h> -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC440 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + puts("Init xilinx temac\n"); +#ifdef XPAR_LLTEMAC_0_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); + +#endif + +#ifdef XPAR_LLTEMAC_1_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); +#endif + + return ret; +} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index e30e592bbe..b45a6a1d76 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -12,12 +12,15 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_INTC_0_BASEADDR 0x87000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80 +#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98 +#define XPAR_LLTEMAC_0_BASEADDR 0x83000000 +#define XPAR_LLTEMAC_1_BASEADDR 0x83000040 #endif diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c index ed758722bb..eb290023a1 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h index c61cf2abcc..bdea5a0443 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c index ac5e0bcb88..abfd91187d 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h index 584e1e1d90..16fa8104a4 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c index 98bad67813..77fd9499df 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h index 6c94c42ceb..8527eef447 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 414f5302a0..01bae5d67e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,7 +8,6 @@ #include <fdtdec.h> #include <fpga.h> #include <mmc.h> -#include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -94,34 +93,11 @@ int board_late_init(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - puts("Board:\tXilinx Zynq\n"); + puts("Board: Xilinx Zynq\n"); return 0; } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - return ret; -} - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c index 34485db9c7..f4f45becd6 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c @@ -1,18 +1,7 @@ /****************************************************************************** * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * ******************************************************************************/ diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h index cd8ead4c0a..9b41e28697 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h @@ -3,18 +3,7 @@ * * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see <http://www.gnu.org/licenses/> +* SPDX-License-Identifier: GPL-2.0+ * * *******************************************************************************/ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 2cf47125d4..44d347ed3b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include <netdev.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -28,10 +29,18 @@ int board_early_init_r(void) { u32 val; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - + if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } /* Program freq register in System counter and enable system counter */ writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | @@ -48,11 +57,6 @@ int dram_init(void) return 0; } -int timer_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { } @@ -73,11 +77,36 @@ int board_late_init(void) reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; + puts("Bootmode: "); switch (bootmode) { - case SD_MODE: + case JTAG_MODE: + puts("JTAG_MODE\n"); + setenv("modeboot", "jtagboot"); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + setenv("modeboot", "qspiboot"); + puts("QSPI_MODE\n"); + break; case EMMC_MODE: + puts("EMMC_MODE\n"); + setenv("modeboot", "sdboot"); + break; + case SD_MODE: + puts("SD_MODE\n"); setenv("modeboot", "sdboot"); break; + case SD_MODE1: + puts("SD_MODE1\n"); +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + setenv("sdbootdev", "1"); +#endif + setenv("modeboot", "sdboot"); + break; + case NAND_MODE: + puts("NAND_MODE\n"); + setenv("modeboot", "nandboot"); + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; @@ -88,7 +117,7 @@ int board_late_init(void) int checkboard(void) { - puts("Board:\tXilinx ZynqMP\n"); + puts("Board: Xilinx ZynqMP\n"); return 0; } |
