diff options
Diffstat (limited to 'board')
31 files changed, 2331 insertions, 307 deletions
diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig index feca03aeef..fe2c3be1b7 100644 --- a/board/Arcturus/ucp1020/Kconfig +++ b/board/Arcturus/ucp1020/Kconfig @@ -12,14 +12,6 @@ config SYS_CONFIG_NAME string default "UCP1020" -config SPI_FLASH - bool - default y - -config SPI_PCI - bool - default y - choice prompt "Target image select" diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 7830d1a200..441465c005 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -64,8 +64,7 @@ void lcdbacklight(int on) unsigned int pwmfrq = getenv_ulong("ds1_pwmfreq", 10, ~0UL); #endif unsigned int tmp; - - struct gptimer *const timerhw = (struct gptimer *)DM_TIMER6_BASE; + struct gptimer *timerhw; if (on) bright = bright != ~0UL ? bright : 50; @@ -73,6 +72,14 @@ void lcdbacklight(int on) bright = 0; switch (driver) { + case 2: + timerhw = (struct gptimer *)DM_TIMER5_BASE; + break; + default: + timerhw = (struct gptimer *)DM_TIMER6_BASE; + } + + switch (driver) { case 0: /* PMIC LED-Driver */ /* brightness level */ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, @@ -83,7 +90,8 @@ void lcdbacklight(int on) bright != 0 ? 0x0A : 0x02, 0xFF); break; - case 1: /* PWM using timer6 */ + case 1: + case 2: /* PWM using timer */ if (pwmfrq != ~0UL) { timerhw->tiocp_cfg = TCFG_RESET; udelay(10); diff --git a/board/highbank/Makefile b/board/highbank/Makefile index d3eb23220b..ce7ee68d4a 100644 --- a/board/highbank/Makefile +++ b/board/highbank/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := highbank.o +obj-y := highbank.o ahci.o diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c new file mode 100644 index 0000000000..00153232f6 --- /dev/null +++ b/board/highbank/ahci.c @@ -0,0 +1,218 @@ +/* + * Copyright 2012 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <ahci.h> +#include <asm/io.h> + +#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) +#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2)) +#define CPHY_BASE 0xfff58000 +#define CPHY_WIDTH 0x1000 +#define CPHY_DTE_XS 5 +#define CPHY_MII 31 +#define SERDES_CR_CTL 0x80a0 +#define SERDES_CR_ADDR 0x80a1 +#define SERDES_CR_DATA 0x80a2 +#define CR_BUSY 0x0001 +#define CR_START 0x0001 +#define CR_WR_RDN 0x0002 +#define CPHY_TX_INPUT_STS 0x2001 +#define CPHY_RX_INPUT_STS 0x2002 +#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000 +#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000 +#define CPHY_TX_INPUT_OVERRIDE 0x2004 +#define CPHY_RX_INPUT_OVERRIDE 0x2005 +#define SPHY_LANE 0x100 +#define SPHY_HALF_RATE 0x0001 +#define CPHY_SATA_DPLL_MODE 0x0700 +#define CPHY_SATA_DPLL_SHIFT 8 +#define CPHY_SATA_TX_ATTEN 0x1c00 +#define CPHY_SATA_TX_ATTEN_SHIFT 10 + +#define HB_SREG_SATA_ATTEN 0xfff3cf24 + +#define SATA_PORT_BASE 0xffe08000 +#define SATA_VERSIONR 0xf8 +#define SATA_HB_VERSION 0x3332302a + +static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr) +{ + u32 data; + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); + return data; +} + +static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data) +{ + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); +} + +static u32 combo_phy_read(u8 phy, u32 addr) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START); + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA); +} + +static void combo_phy_write(u8 phy, u32 addr, u32 data) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START); +} + +static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) +{ + u32 tmp; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp &= ~CPHY_SATA_DPLL_MODE; + tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_tx_attenuation_override(u8 phy, u8 lane) +{ + u32 val; + u32 tmp; + u8 shift; + + shift = ((phy == 5) ? 4 : lane) * 4; + + val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf; + + if (val & 0x8) + return; + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_disable_port_overrides(u8 port) +{ + u32 tmp; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +void cphy_disable_overrides(void) +{ + int i; + u32 port_map; + + port_map = readl(0xffe08000 + HOST_PORTS_IMPL); + for (i = 0; i < 5; i++) { + if (port_map & (1 << i)) + cphy_disable_port_overrides(i); + } +} + +static void cphy_override_lane(u8 port) +{ + u32 tmp, k = 0; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + + do { + tmp = combo_phy_read(0, CPHY_RX_INPUT_STS + + lane * SPHY_LANE); + } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); + cphy_spread_spectrum_override(phy, lane, 3); + cphy_tx_attenuation_override(phy, lane); +} + +#define WAIT_MS_LINKUP 4 + +int ahci_link_up(struct ahci_probe_ent *probe_ent, int port) +{ + u32 tmp; + int j = 0; + u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) == + SATA_HB_VERSION ? 1 : 0; + + /* Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + if (is_highbank && (j == 0)) { + cphy_disable_port_overrides(port); + writel(0x301, port_mmio + PORT_SCR_CTL); + udelay(1000); + writel(0x300, port_mmio + PORT_SCR_CTL); + udelay(1000); + cphy_override_lane(port); + } + + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + return 0; + udelay(1000); + j++; + + if ((j == WAIT_MS_LINKUP) && (tmp & 0xf)) + j = 0; /* retry phy reset */ + } + return 1; +} diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index ba1beb5bbc..469ee8e114 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -14,9 +14,11 @@ #define HB_AHCI_BASE 0xffe08000 +#define HB_SCU_A9_PWR_STATUS 0xfff10008 #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 #define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 +#define HB_SREG_A15_PWR_CTRL 0xfff3c200 #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 @@ -27,8 +29,14 @@ #define PWRDOM_STAT_PCI 0x40000000 #define PWRDOM_STAT_EMMC 0x20000000 +#define HB_SCU_A9_PWR_NORMAL 0 +#define HB_SCU_A9_PWR_DORMANT 2 +#define HB_SCU_A9_PWR_OFF 3 + DECLARE_GLOBAL_DATA_PTR; +void cphy_disable_overrides(void); + /* * Miscellaneous platform dependent initialisations */ @@ -56,6 +64,7 @@ void scsi_init(void) { u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + cphy_disable_overrides(); if (reg & PWRDOM_STAT_SATA) { ahci_init((void __iomem *)HB_AHCI_BASE); scsi_scan(1); @@ -111,9 +120,31 @@ int ft_board_setup(void *fdt, bd_t *bd) } #endif +static int is_highbank(void) +{ + uint32_t midr; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); + + return (midr & 0xfff0) == 0xc090; +} + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); + if (is_highbank()) + writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS); + else + writel(0x1, HB_SREG_A15_PWR_CTRL); wfi(); } + +/* + * turn off the override before transferring control to Linux, since Linux + * may not support spread spectrum. + */ +void arch_preboot_os(void) +{ + cphy_disable_overrides(); +} diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 20dd75c22e..1a4e8c9c99 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -24,8 +24,9 @@ #include <asm/arch/sromc.h> #include <lcd.h> #include <i2c.h> -#include <samsung/misc.h> #include <usb.h> +#include <dwc3-uboot.h> +#include <samsung/misc.h> DECLARE_GLOBAL_DATA_PTR; @@ -378,5 +379,8 @@ void reset_misc(void) int board_usb_cleanup(int index, enum usb_init_type init) { +#ifdef CONFIG_USB_DWC3 + dwc3_uboot_exit(index); +#endif return 0; } diff --git a/board/samsung/common/bootscripts/autoboot.cmd b/board/samsung/common/bootscripts/autoboot.cmd new file mode 100644 index 0000000000..1faed8ba0c --- /dev/null +++ b/board/samsung/common/bootscripts/autoboot.cmd @@ -0,0 +1,92 @@ +# This is an example file to generate boot.scr - a boot script for U-Boot +# Generate boot.scr: +# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr +# +# It requires a list of environment variables to be defined before load: +# platform dependent: boardname, fdtfile, console +# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype +# +setenv fdtaddr "40800000" +setenv initrdname "uInitrd" +setenv initrdaddr "42000000" +setenv loaddtb "load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} ${fdtfile}" +setenv loadinitrd "load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} ${initrdname}" +setenv loadkernel "load mmc ${mmcbootdev}:${mmcbootpart} '${kerneladdr}' '${kernelname}'" +setenv kernel_args "setenv bootargs ${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}" + +#### Routine: check_dtb - check that target.dtb exists on boot partition +setenv check_dtb " +if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${fdtfile}'; then + run loaddtb; + setenv fdt_addr ${fdtaddr}; +else + echo Warning! Booting without DTB: '${fdtfile}'!; + setenv fdt_addr; +fi;" + +#### Routine: check_ramdisk - check that uInitrd exists on boot partition +setenv check_ramdisk " +if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${initrdname}'; then + echo "Found ramdisk image."; + run loadinitrd; + setenv initrd_addr ${initrdaddr}; +else + echo Warning! Booting without RAMDISK: '${initrdname}'!; + setenv initrd_addr -; +fi;" + +#### Routine: boot_fit - check that env $boardname is set and boot proper config of ITB image +setenv setboot_fit " +if test -e '${boardname}'; then + setenv fdt_addr ; + setenv initrd_addr ; + setenv kerneladdr 0x42000000; + setenv kernelname Image.itb; + setenv itbcfg "\"#${boardname}\""; + setenv imgbootcmd bootm; +else + echo Warning! Variable: \$boardname is undefined!; +fi" + +#### Routine: setboot_uimg - prepare env to boot uImage +setenv setboot_uimg " + setenv kerneladdr 0x40007FC0; + setenv kernelname uImage; + setenv itbcfg ; + setenv imgbootcmd bootm; + run check_dtb; + run check_ramdisk;" + +#### Routine: setboot_zimg - prepare env to boot zImage +setenv setboot_zimg " + setenv kerneladdr 0x40007FC0; + setenv kernelname zImage; + setenv itbcfg ; + setenv imgbootcmd bootz; + run check_dtb; + run check_ramdisk;" + +#### Routine: boot_img - boot the kernel after env setup +setenv boot_img " + run loadkernel; + run kernel_args; + '${imgbootcmd}' '${kerneladdr}${itbcfg}' '${initrd_addr}' '${fdt_addr}';" + +#### Routine: autoboot - choose proper boot path +setenv autoboot " +if test -e mmc 0:${mmcbootpart} Image.itb; then + echo Found kernel image: Image.itb; + run setboot_fit; + run boot_img; +elif test -e mmc 0:${mmcbootpart} zImage; then + echo Found kernel image: zImage; + run setboot_zimg; + run boot_img; +elif test -e mmc 0:${mmcbootpart} uImage; then + echo Found kernel image: uImage; + run setboot_uimg; + run boot_img; +fi;" + +#### Execute the defined autoboot macro +run autoboot diff --git a/board/samsung/common/bootscripts/bootzimg.cmd b/board/samsung/common/bootscripts/bootzimg.cmd new file mode 100644 index 0000000000..2fb4c163a7 --- /dev/null +++ b/board/samsung/common/bootscripts/bootzimg.cmd @@ -0,0 +1,10 @@ +setenv kernelname zImage; +setenv boot_kernel "setenv bootargs \"${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}\"; +load mmc ${mmcbootdev}:${mmcbootpart} 0x40007FC0 '${kernelname}'; +if load mmc ${mmcbootdev}:${mmcbootpart} 40800000 ${fdtfile}; then + bootz 0x40007FC0 - 40800000; +else + echo Warning! Booting without DTB: '${fdtfile}'!; + bootz 0x40007FC0 -; +fi;" +run boot_kernel;
\ No newline at end of file diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 82f607b24d..88f4044d63 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -6,19 +6,25 @@ #include <common.h> #include <fdtdec.h> -#include <asm/io.h> -#include <i2c.h> -#include <lcd.h> -#include <parade.h> -#include <spi.h> #include <errno.h> +#include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/board.h> #include <asm/arch/cpu.h> -#include <asm/arch/pinmux.h> +#include <asm/arch/board.h> +#include <asm/arch/power.h> #include <asm/arch/system.h> +#include <asm/arch/pinmux.h> #include <asm/arch/dp_info.h> +#include <asm/arch/xhci-exynos.h> #include <power/tps65090_pmic.h> +#include <i2c.h> +#include <lcd.h> +#include <mmc.h> +#include <parade.h> +#include <spi.h> +#include <usb.h> +#include <dwc3-uboot.h> +#include <samsung-usb-phy-uboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -75,3 +81,63 @@ int board_get_revision(void) { return 0; } + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_SUPER, + .base = 0x12400000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *) + samsung_get_base_usb3_phy(); + + if (!phy) { + error("usb3 phy not supported"); + return -ENODEV; + } + + set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); + exynos5_usb3_phy_init(phy); + + return dwc3_uboot_init(&dwc3_device_data); +} +#endif +#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(char *interface, char *devstr) +{ + return getenv("dfu_alt_system"); +} + +char *get_dfu_alt_boot(char *interface, char *devstr) +{ + struct mmc *mmc; + char *alt_boot; + int dev_num; + + dev_num = simple_strtoul(devstr, NULL, 10); + + mmc = find_mmc_device(dev_num); + if (!mmc) + return NULL; + + if (mmc_init(mmc)) + return NULL; + + if (IS_SD(mmc)) + alt_boot = CONFIG_DFU_ALT_BOOT_SD; + else + alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; + + return alt_boot; +} +#endif diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index fb2de48fbc..c127f6ca27 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -75,8 +75,9 @@ int board_init(void) i2c_set_bus_num(0); if (read_eeprom() < 0) puts("Could not get board ID.\n"); - +#ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; +#endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FACTORYSET @@ -102,21 +103,29 @@ const struct dpll_params *get_dpll_ddr_params(void) } #ifndef CONFIG_SPL_BUILD + +#define MAX_NR_LEDS 10 +#define MAX_PIN_NUMBER 128 +#define STARTUP 0 + #if defined(BOARD_DFU_BUTTON_GPIO) -/* - * This command returns the status of the user button on - * Input - none - * Returns - 1 if button is held down - * 0 if button is not held down - */ -static int -do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +unsigned char get_button_state(char * const envname, unsigned char def) { int button = 0; int gpio; + char *ptr_env; - gpio = BOARD_DFU_BUTTON_GPIO; - gpio_request(gpio, "DFU"); + /* If button is not found we take default */ + ptr_env = getenv(envname); + if (NULL == ptr_env) { + gpio = def; + } else { + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0); + if (gpio > MAX_PIN_NUMBER) + gpio = def; + } + + gpio_request(gpio, ""); gpio_direction_input(gpio); if (gpio_get_value(gpio)) button = 1; @@ -127,53 +136,27 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return button; } - -U_BOOT_CMD( - dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, - "Return the status of the DFU button", - "" -); -#endif -/* - * This command sets led - * Input - name of led - * value of led - * Returns - 1 if input does not match - * 0 if led was set +/** + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down */ static int -do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int gpio = 0; - if (argc != 3) - goto exit; -#if defined(BOARD_STATUS_LED) - if (!strcmp(argv[1], "stat")) - gpio = BOARD_STATUS_LED; -#endif -#if defined(BOARD_DFU_BUTTON_LED) - if (!strcmp(argv[1], "dfu")) - gpio = BOARD_DFU_BUTTON_LED; -#endif - /* If argument does not mach exit */ - if (gpio == 0) - goto exit; - gpio_request(gpio, ""); - gpio_direction_output(gpio, 1); - if (!strcmp(argv[2], "1")) - gpio_set_value(gpio, 1); - else - gpio_set_value(gpio, 0); - return 0; -exit: - return 1; + int button = 0; + button = get_button_state("button_dfu0", BOARD_DFU_BUTTON_GPIO); + button |= get_button_state("button_dfu1", BOARD_DFU_BUTTON_GPIO); + return button; } U_BOOT_CMD( - led, CONFIG_SYS_MAXARGS, 2, do_setled, - "Set led on or off", - "dfu val - set dfu led\nled stat val - set status led" + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" ); +#endif static int do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -189,4 +172,95 @@ U_BOOT_CMD( "Sends U-Boot into infinite loop", "" ); + +/** + * Get led gpios from env and set them. + * The led define in environment need to need to be of the form ledN=NN,S0,S1 + * where N is an unsigned integer from 0 to 9 and S0 and S1 is 0 or 1. S0 + * defines the startup state of the led, S1 the special state of the led when + * it enters e.g. dfu mode. + */ +void set_env_gpios(unsigned char state) +{ + char *ptr_env; + char str_tmp[5]; /* must contain "ledX"*/ + char num[1]; + unsigned char i, idx, pos1, pos2, ccount; + unsigned char gpio_n, gpio_s0, gpio_s1; + + for (i = 0; i < MAX_NR_LEDS; i++) { + strcpy(str_tmp, "led"); + sprintf(num, "%d", i); + strcat(str_tmp, num); + + /* If env var is not found we stop */ + ptr_env = getenv(str_tmp); + if (NULL == ptr_env) + break; + + /* Find sperators position */ + pos1 = 0; + pos2 = 0; + ccount = 0; + for (idx = 0; ptr_env[idx] != '\0'; idx++) { + if (ptr_env[idx] == ',') { + if (ccount++ < 1) + pos1 = idx; + else + pos2 = idx; + } + } + /* Bad led description skip this definition */ + if (pos2 <= pos1 || ccount > 2) + continue; + + /* Get pin number and request gpio */ + memset(str_tmp, 0, sizeof(str_tmp)); + strncpy(str_tmp, ptr_env, pos1*sizeof(char)); + gpio_n = (unsigned char)simple_strtoul(str_tmp, NULL, 0); + + /* Invalid gpio number skip definition */ + if (gpio_n > MAX_PIN_NUMBER) + continue; + + gpio_request(gpio_n, ""); + + if (state == STARTUP) { + /* get pin state 0 and set */ + memset(str_tmp, 0, sizeof(str_tmp)); + strncpy(str_tmp, ptr_env+pos1+1, + (pos2-pos1-1)*sizeof(char)); + gpio_s0 = (unsigned char)simple_strtoul(str_tmp, NULL, + 0); + + gpio_direction_output(gpio_n, gpio_s0); + + } else { + /* get pin state 1 and set */ + memset(str_tmp, 0, sizeof(str_tmp)); + strcpy(str_tmp, ptr_env+pos2+1); + gpio_s1 = (unsigned char)simple_strtoul(str_tmp, NULL, + 0); + gpio_direction_output(gpio_n, gpio_s1); + } + } /* loop through defined led in environment */ +} + +static int do_board_led(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if ((unsigned char)simple_strtoul(argv[1], NULL, 0) == STARTUP) + set_env_gpios(0); + else + set_env_gpios(1); + return 0; +}; + +U_BOOT_CMD( + draco_led, CONFIG_SYS_MAXARGS, 2, do_board_led, + "Set LEDs defined in environment", + "<0|1>" +); #endif /* !CONFIG_SPL_BUILD */ diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index d138ecea9d..819d187087 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -14,7 +14,7 @@ config SYS_CONFIG_NAME endif -if TARGET_DXR2 +if TARGET_THUBAN config SYS_BOARD default "draco" @@ -26,6 +26,22 @@ config SYS_SOC default "am33xx" config SYS_CONFIG_NAME - default "dxr2" + default "thuban" + +endif + +if TARGET_RASTABAN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "rastaban" endif diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index f6b68ca400..484dd739c1 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -4,5 +4,7 @@ S: Maintained F: board/siemens/draco/ F: include/configs/draco.h F: configs/draco_defconfig -F: include/configs/dxr2.h -F: configs/dxr2_defconfig +F: include/configs/thuban.h +F: configs/thuban_defconfig +F: include/configs/rastaban.h +F: configs/rastaban_defconfig diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index ede73baf3e..2697762076 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -43,7 +43,7 @@ static struct draco_baseboard_id __attribute__((section(".data"))) settings; /* Default@303MHz-i0 */ const struct ddr3_data ddr3_default = { 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, - 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32, 0x0000093B, 0x0000014A, "default name @303MHz \0", "default marking \0", @@ -71,8 +71,8 @@ static void print_ddr3_timings(void) printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); printf("device:\t\t%s\n", settings.ddr3.manu_name); printf("marking:\t%s\n", settings.ddr3.manu_marking); - printf("timing parameters\n"); - printf("diff\teeprom\tdefault\n"); + printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom", + "default", "diff"); PRINTARGS(magic); PRINTARGS(version); PRINTARGS(ddr3_sratio); @@ -96,9 +96,12 @@ static void print_ddr3_timings(void) static void print_chip_data(void) { + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); printf("\nCPU BOARD\n"); printf("device: \t'%s'\n", settings.chip.sdevname); printf("hw version: \t'%s'\n", settings.chip.shwver); + printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m); } #endif /* CONFIG_SPL_BUILD */ @@ -193,6 +196,11 @@ struct ctrl_ioregs draco_ddr3_ioregs = { config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); + + /* For Samsung 2Gbit RAM we need this delay otherwise config fails after + * soft reset. + */ + udelay(2000); } static void spl_siemens_board_init(void) @@ -201,6 +209,26 @@ static void spl_siemens_board_init(void) } #endif /* if def CONFIG_SPL_BUILD */ +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); +#ifdef CONFIG_FACTORYSET + /* Set ASN in environment*/ + if (factory_dat.asn[0] != 0) { + setenv("dtb_name", (char *)factory_dat.asn); + } else { + /* dtb suffix gets added in load script */ + setenv("dtb_name", "am335x-draco"); + } +#else + setenv("dtb_name", "am335x-draco"); +#endif + + return 0; +} +#endif + #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) @@ -280,13 +308,4 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - omap_nand_switch_ecc(1, 8); - - return 0; -} -#endif - #include "../common/board.c" diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h index ff8ab764c5..8856fd0f86 100644 --- a/board/siemens/draco/board.h +++ b/board/siemens/draco/board.h @@ -16,9 +16,13 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ - settings.ddr3.x, ddr3_default.x -#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define PARGS(x) #x , /* Parameter Name */ \ + settings.ddr3.x, /* EEPROM Value */ \ + ddr3_default.x, /* Default Value */ \ + settings.ddr3.x-ddr3_default.x /* Difference */ + +#define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y)) + #define MAGIC_CHIP 0x50494843 /* Automatic generated definition */ @@ -69,4 +73,7 @@ void enable_uart4_pin_mux(void); void enable_uart5_pin_mux(void); void enable_i2c0_pin_mux(void); void enable_board_pin_mux(void); + +/* Forwared declaration, defined in common board.c */ +void set_env_gpios(unsigned char state); #endif diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c index eaa3c70798..dbcc80b61f 100644 --- a/board/siemens/draco/mux.c +++ b/board/siemens/draco/mux.c @@ -60,7 +60,7 @@ static struct module_pin_mux nand_pin_mux[] = { static struct module_pin_mux gpios_pin_mux[] = { /* DFU button GPIO0_27*/ - {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ /* Triacs in HW Rev 2 */ @@ -222,7 +222,7 @@ static struct module_pin_mux gpios_pin_mux[] = { {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, /* nRST for SMSC LAN9303 switch - GPIO2_24 */ - {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ + {OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */ {-1}, }; diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b2eca51ffb..2a1cd3cf3b 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -280,18 +280,6 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config SPL_NAND_SUPPORT - bool "SPL/NAND mode support" - depends on SPL - default n - ---help--- - This enables support for booting from NAND internal - memory. U-Boot SPL doesn't detect where is it load from, - therefore this option is needed to properly load image from - flash. Option also disables MMC functionality on U-Boot due to - initialization errors encountered, when both controllers are - enabled. - config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default "" @@ -566,25 +554,4 @@ config GMAC_TX_DELAY ---help--- Set the GMAC Transmit Clock Delay Chain value. -config SYS_MALLOC_CLEAR_ON_INIT - default n - -config NETDEVICES - default y - -config DM_ETH - default y - -config DM_SERIAL - default y - -config DM_USB - default y if !USB_MUSB_SUNXI - -config CMD_SETEXPR - default y - -config CMD_NET - default y - endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f27967bbf4..ed60e74808 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -22,9 +22,6 @@ #ifdef CONFIG_AXP221_POWER #include <axp221.h> #endif -#ifdef CONFIG_NAND_SUNXI -#include <nand.h> -#endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/display.h> @@ -318,21 +315,6 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_NAND -void board_nand_init(void) -{ - unsigned int pin; - static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS; - - /* Configure AHB muxes to connect output pins with NAND controller */ - for (pin = 0; pin < 16; pin++) - sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND); - - for (pin = 0; pin < ARRAY_SIZE(ports); pin++) - sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND); -} -#endif - void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE diff --git a/board/synopsys/axs101/MAINTAINERS b/board/synopsys/axs101/MAINTAINERS index 481bbcc207..79fff8eb3e 100644 --- a/board/synopsys/axs101/MAINTAINERS +++ b/board/synopsys/axs101/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/synopsys/axs101/ F: include/configs/axs101.h F: configs/axs101_defconfig +F: configs/axs103_defconfig diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c index 8c16410944..d4280f743a 100644 --- a/board/synopsys/axs101/axs101.c +++ b/board/synopsys/axs101/axs101.c @@ -56,3 +56,33 @@ int board_early_init_f(void) return 0; } + +#ifdef CONFIG_ISA_ARCV2 +#define RESET_VECTOR_ADDR 0x0 + +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* All cores have reset vector pointing to 0 */ + writel(addr, (void __iomem *)RESET_VECTOR_ADDR); + + /* Make sure other cores see written value in memory */ + flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int)); +} + +void smp_kick_all_cpus(void) +{ +/* CPU start CREG */ +#define AXC003_CREG_CPU_START 0xF0001400 + +/* Bits positions in CPU start CREG */ +#define BITS_START 0 +#define BITS_POLARITY 8 +#define BITS_CORE_SEL 9 +#define BITS_MULTICORE 12 + +#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \ + (1 << BITS_POLARITY) | (1 << BITS_START) + + writel(CMD, (void __iomem *)AXC003_CREG_CPU_START); +} +#endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4aae230608..d7b9e5af88 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = { 400, 23, 1, -1, 2, -1, -1 }; +static const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { .emif_cos_config = 0x00ffffff }; +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } + + return; +} + /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index ffcd53185b..c7f19c7924 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -14,7 +14,10 @@ #include <usb.h> #include <asm/omap_common.h> #include <asm/emif.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> #include <asm/arch/clock.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -29,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +/* GPIO 7_11 */ +#define GPIO_DDR_VTT_EN 203 + const struct omap_sysinfo sysinfo = { "Board: BeagleBoard x15\n" }; @@ -52,23 +58,29 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; +/* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00740074, + 0x00780078, + 0x007c007c, + 0x007b007b, 0x00800080, 0x00360036, 0x00340034, @@ -90,14 +102,19 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { @@ -109,23 +126,28 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00820082, + 0x008b008b, + 0x00800080, + 0x007e007e, 0x00800080, 0x00370037, 0x00390039, @@ -145,14 +167,19 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) @@ -240,23 +267,20 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) @@ -385,3 +409,21 @@ int board_eth_init(bd_t *bis) return ret; } #endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +/* VTT regulator enable */ +static inline void vtt_regulator_enable(void) +{ + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); +} + +int board_early_init_f(void) +{ + vtt_regulator_enable(); + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h index df658c5211..09d3650983 100644 --- a/board/ti/beagle_x15/mux_data.h +++ b/board/ti/beagle_x15/mux_data.h @@ -13,43 +13,318 @@ #include <asm/arch/mux_dra7xx.h> const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ - {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ - {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ - {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ - {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ - {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ - {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ - {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ - {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ - {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ - {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ - {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */ - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ - {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ - {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {USB1_DRVVBUS, (M0 | FSC) }, - {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ + {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */ + {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */ + {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */ + {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */ + {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */ + {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */ + {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */ + {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */ + {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */ + {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */ + {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */ + {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */ + {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */ + {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */ + {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */ + {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */ + {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */ + {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */ + {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */ + {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */ + {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */ + {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */ + {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */ + {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */ + {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */ + {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */ + {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */ + {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */ + {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ + {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */ + {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */ + {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */ + {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */ + {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */ + {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */ + {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */ + {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */ + {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ + {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ + {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ + {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ + {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ + {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */ + {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */ + {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ + {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ + {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ + {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */ + {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */ + {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */ + {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ + {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ + {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ + {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ + {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */ + {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */ + {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ + {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ + {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ + {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ + {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ + {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */ + {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */ + {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ + {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ + {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ + {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */ + {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ + {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */ + {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */ + {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */ + {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */ + {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */ + {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */ + {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */ + {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ + {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ + {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ + {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ + {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */ + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ + {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ }; + +const struct pad_conf_entry early_padconf[] = { + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */ + {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */ + {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */ + {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */ + {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */ + {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */ + {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */ + {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */ + {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */ + {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */ + {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */ + {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */ + {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */ + {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */ + {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */ + {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */ + {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */ + {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */ + {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */ + {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */ + {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */ + {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */ + {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */ + {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */ + {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ + {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ + {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif #endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d4648558ec..94a1a8c256 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -17,6 +17,7 @@ #include <usb.h> #include <linux/usb/gadget.h> #include <asm/arch/gpio.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -40,43 +41,6 @@ const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; -/* - * Adjust I/O delays on the Tx control and data lines of each MAC port. This - * is a workaround in order to work properly with the DP83865 PHYs on the EVM. - * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we - * essentially need to counteract the DRA7xx internal delay, and we do this - * by delaying the control and data lines. If not using this PHY, you probably - * don't need to do this stuff! - */ -static void dra7xx_adj_io_delay(const struct io_delay *io_dly) -{ - int i = 0; - u32 reg_val; - u32 delta; - u32 coarse; - u32 fine; - - writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); - - while(io_dly[i].addr) { - writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, - io_dly[i].addr); - delta = io_dly[i].dly; - reg_val = readl(io_dly[i].addr) & 0x3ff; - coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); - coarse = (coarse > 0x1F) ? (0x1F) : (coarse); - fine = (reg_val & 0x1F) + (delta & 0x1F); - fine = (fine > 0x1F) ? (0x1F) : (fine); - reg_val = CFG_IO_DELAY_ACCESS_PATTERN | - CFG_IO_DELAY_LOCK_MASK | - ((coarse << 5) | (fine)); - writel(reg_val, io_dly[i].addr); - i++; - } - - writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); -} - /** * @brief board_init * @@ -107,23 +71,28 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + if (is_dra72x()) { + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, + ARRAY_SIZE(iodelay_cfg_array)); + } else { + __recalibrate_iodelay(dra74x_core_padconf_array, + ARRAY_SIZE(dra74x_core_padconf_array), + dra742_iodelay_cfg_array, + ARRAY_SIZE(dra742_iodelay_cfg_array)); + } } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) @@ -257,19 +226,6 @@ int spl_start_uboot(void) #endif #ifdef CONFIG_DRIVER_TI_CPSW - -/* Delay value to add to calibrated value */ -#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) -#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) -#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) -#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) - extern u32 *const omap_si_rev; static void cpsw_control(int enabled) @@ -317,22 +273,6 @@ int board_eth_init(bd_t *bis) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; - const struct io_delay io_dly[] = { - {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, - {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, - {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, - {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, - {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, - {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, - {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, - {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, - {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, - {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, - {0} - }; - - /* Adjust IO delay for RGMII tx path */ - dra7xx_adj_io_delay(io_dly); /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 48240779c9..c9301a51c0 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -76,30 +76,30 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {VIN2A_D12, (M3) }, - {VIN2A_D13, (M3) }, - {VIN2A_D14, (M3) }, - {VIN2A_D15, (M3) }, - {VIN2A_D16, (M3) }, - {VIN2A_D17, (M3) }, - {VIN2A_D18, (IEN | M3)}, - {VIN2A_D19, (IEN | M3)}, - {VIN2A_D20, (IEN | M3)}, - {VIN2A_D21, (IEN | M3)}, - {VIN2A_D22, (IEN | M3)}, - {VIN2A_D23, (IEN | M3)}, + {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) }, + {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)}, #if defined(CONFIG_NAND) || defined(CONFIG_NOR) /* NAND / NOR pin-mux */ {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ @@ -141,4 +141,295 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USB2_DRVVBUS, (M0 | IEN | FSC) }, {SPI1_CS1, (PEN | IDIS | M14) }, }; + +const struct pad_conf_entry early_padconf[] = { +#if (CONFIG_CONS_INDEX == 1) + {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ + {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ +#elif (CONFIG_CONS_INDEX == 3) + {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ + {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ +#endif + {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */ + {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */ + {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */ + {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */ + {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */ + {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */ + {0x740, 531, 120}, /* RGMMI0_TXC_OUT */ + {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */ + {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */ + {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */ + {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */ + {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */ + {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ + {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ +}; +#endif + +const struct pad_conf_entry dra74x_core_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */ + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */ + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */ + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */ + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */ + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */ + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ + {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ + {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ + {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ + {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */ + {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */ + {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */ + {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */ + {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */ + {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */ + {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */ + {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */ + {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */ + {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */ + {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */ + {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */ + {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */ + {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */ + {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */ + {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */ + {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */ + {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */ + {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */ + {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */ + {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */ + {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */ + {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */ + {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */ + {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ + {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ + {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */ + {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */ + {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */ + {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */ + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ + {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ + {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ + {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */ + {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ + {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */ + {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */ + {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */ + {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */ + {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */ + {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */ + {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */ + {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */ + {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */ + {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */ + {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */ + {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */ + {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */ + {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */ + {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */ + {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */ + {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */ + {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */ + {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */ + {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */ + {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */ + {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */ + {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */ + {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */ + {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */ + {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */ + {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */ + {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */ + {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif + #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig new file mode 100644 index 0000000000..bc1edcf3a4 --- /dev/null +++ b/board/vscom/baltos/Kconfig @@ -0,0 +1,24 @@ +if TARGET_AM335X_BALTOS + +config SYS_BOARD + default "baltos" + +config SYS_VENDOR + default "vscom" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "baltos" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0. + +endif diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile new file mode 100644 index 0000000000..804ac379db --- /dev/null +++ b/board/vscom/baltos/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README new file mode 100644 index 0000000000..f744ace997 --- /dev/null +++ b/board/vscom/baltos/README @@ -0,0 +1 @@ +BSP for VScom OnRISC Balios family devices, like Balios iR 5221. diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c new file mode 100644 index 0000000000..99ca60e2ac --- /dev/null +++ b/board/vscom/baltos/board.c @@ -0,0 +1,474 @@ +/* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 +#define DIP_S1 44 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int baltos_set_console(void) +{ + int val, i, dips = 0; + char buf[7]; + + for (i = 0; i < 4; i++) { + sprintf(buf, "dip_s%d", i + 1); + + if (gpio_request(DIP_S1 + i, buf)) { + printf("failed to export GPIO %d\n", DIP_S1 + i); + return 0; + } + + if (gpio_direction_input(DIP_S1 + i)) { + printf("failed to set GPIO %d direction\n", DIP_S1 + i); + return 0; + } + + val = gpio_get_value(DIP_S1 + i); + dips |= val << i; + } + + printf("DIPs: 0x%1x\n", (~dips) & 0xf); + + if ((dips & 0xf) == 0xe) + setenv("console", "ttyUSB0,115200n8"); + + return 0; +} + +static int read_eeprom(BSP_VS_HWPARAM *header) +{ + i2c_set_bus_num(1); + + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(BSP_VS_HWPARAM))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header->Magic != 0xDEADBEEF) { + + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->Magic); + + /* fill default values */ + header->SystemId = 211; + header->MAC1[0] = 0x00; + header->MAC1[1] = 0x00; + header->MAC1[2] = 0x00; + header->MAC1[3] = 0x00; + header->MAC1[4] = 0x00; + header->MAC1[5] = 0x01; + + header->MAC2[0] = 0x00; + header->MAC2[1] = 0x00; + header->MAC2[2] = 0x00; + header->MAC2[3] = 0x00; + header->MAC2[4] = 0x00; + header->MAC2[5] = 0x02; + + header->MAC3[0] = 0x00; + header->MAC3[1] = 0x00; + header->MAC3[2] = 0x00; + header->MAC3[3] = 0x00; + header->MAC3[4] = 0x00; + header->MAC3[5] = 0x03; + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +static const struct ddr_data ddr3_baltos_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_baltos_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return (serial_tstc() && serial_getc() == 'c'); +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_baltos = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int sil_rev; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + i2c_set_bus_num(1); + + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { + puts("i2c: cannot access TPS65910\n"); + return; + } + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + + writel(0x000010ff, PRM_DEVICE_INST + 4); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); + + return &dpll_ddr_baltos; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_baltos = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + + config_ddr(400, &ioregs_baltos, + &ddr3_baltos_data, + &ddr3_baltos_cmd_ctrl_data, + &ddr3_baltos_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int node, ret; + unsigned char mac_addr[6]; + BSP_VS_HWPARAM header; + + /* get production data */ + if (read_eeprom(&header)) + return 0; + + /* setup MAC1 */ + mac_addr[0] = header.MAC1[0]; + mac_addr[1] = header.MAC1[1]; + mac_addr[2] = header.MAC1[2]; + mac_addr[3] = header.MAC1[3]; + mac_addr[4] = header.MAC1[4]; + mac_addr[5] = header.MAC1[5]; + + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + /* setup MAC2 */ + mac_addr[0] = header.MAC2[0]; + mac_addr[1] = header.MAC2[1]; + mac_addr[2] = header.MAC2[2]; + mac_addr[3] = header.MAC2[3]; + mac_addr[4] = header.MAC2[4]; + mac_addr[5] = header.MAC2[5]; + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + printf("\nFDT was successfully setup\n"); + + return 0; +} + +static struct module_pin_mux dip_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ + {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ + {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ + {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ + {-1}, +}; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + BSP_VS_HWPARAM header; + char model[4]; + + /* get production data */ + if (read_eeprom(&header)) { + sprintf(model, "211"); + } else { + sprintf(model, "%d", header.SystemId); + if (header.SystemId == 215) { + configure_module_pin_mux(dip_pin_mux); + baltos_set_console(); + } + } + setenv("board_name", model); +#endif + + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 7, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .active_slave = 1, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; + + /* + * Note here that we're using CPSW1 since that has a 1Gbit PHY while + * CSPW0 has a 100Mbit PHY. + * + * On product, CPSW1 maps to port labeled WAN. + */ + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the first instance. + */ +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + const char *devname; + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); +#endif + return n; +} +#endif diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h new file mode 100644 index 0000000000..bcdb6485d2 --- /dev/null +++ b/board/vscom/baltos/board.h @@ -0,0 +1,90 @@ +/* + * board.h + * + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * TI AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +typedef struct _BSP_VS_HWPARAM // v1.0 +{ + uint32_t Magic; + uint32_t HwRev; + uint32_t SerialNumber; + char PrdDate[11]; // as a string ie. "01.01.2006" + uint16_t SystemId; + uint8_t MAC1[6]; // internal EMAC + uint8_t MAC2[6]; // SMSC9514 + uint8_t MAC3[6]; // WL1271 WLAN +} __attribute__ ((packed)) BSP_VS_HWPARAM; + +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_i2c1_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c new file mode 100644 index 0000000000..8783b25b5f --- /dev/null +++ b/board/vscom/baltos/mux.c @@ -0,0 +1,194 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_i2c1_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); +} + +void enable_board_pin_mux() +{ + /* Baltos */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif +} diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds new file mode 100644 index 0000000000..315ba5b99a --- /dev/null +++ b/board/vscom/baltos/u-boot.lds @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/vscom/baltos/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} |
