diff options
Diffstat (limited to 'board')
86 files changed, 2248 insertions, 931 deletions
diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile deleted file mode 100644 index e66aeb8467..0000000000 --- a/board/Synology/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2015 Phil Sutter <phil@nwl.cc> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cmd_syno.o diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile index 0f4c32d57c..93be101575 100644 --- a/board/Synology/ds414/Makefile +++ b/board/Synology/ds414/Makefile @@ -4,4 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ds414.o +obj-y += ds414.o +ifndef CONFIG_SPL_BUILD +obj-y += cmd_syno.o +endif diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/ds414/cmd_syno.c index 20544e29c4..20544e29c4 100644 --- a/board/Synology/common/cmd_syno.c +++ b/board/Synology/ds414/cmd_syno.c diff --git a/board/amazon/kc1/Kconfig b/board/amazon/kc1/Kconfig new file mode 100644 index 0000000000..1b46a8f3c7 --- /dev/null +++ b/board/amazon/kc1/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KC1 + +config SYS_BOARD + default "kc1" + +config SYS_VENDOR + default "amazon" + +config SYS_CONFIG_NAME + default "kc1" + +endif diff --git a/board/amazon/kc1/MAINTAINERS b/board/amazon/kc1/MAINTAINERS new file mode 100644 index 0000000000..7e596d906e --- /dev/null +++ b/board/amazon/kc1/MAINTAINERS @@ -0,0 +1,6 @@ +KC1 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: board/amazon/kc1/ +F: include/configs/kc1.h +F: configs/kc1_defconfig diff --git a/board/amazon/kc1/Makefile b/board/amazon/kc1/Makefile new file mode 100644 index 0000000000..59c8347164 --- /dev/null +++ b/board/amazon/kc1/Makefile @@ -0,0 +1,9 @@ +# +# Amazon Kindle Fire (first generation) codename kc1 config +# +# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := kc1.o diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c new file mode 100644 index 0000000000..ca63af8be4 --- /dev/null +++ b/board/amazon/kc1/kc1.c @@ -0,0 +1,182 @@ +/* + * Amazon Kindle Fire (first generation) codename kc1 config + * + * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <linux/ctype.h> +#include <linux/usb/musb.h> +#include <asm/omap_musb.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/gpio.h> +#include <asm/emif.h> +#include <twl6030.h> +#include "kc1.h" + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + .board_string = "kc1" +}; + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12 +}; + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_UTMI, +}; + +static struct musb_hdrc_platform_data musb_platform_data = { + .mode = MUSB_PERIPHERAL, + .config = &musb_config, + .power = 100, + .platform_ops = &omap2430_ops, + .board_data = &musb_board_data, +}; + + +void set_muxconf_regs(void) +{ + do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array, + sizeof(core_padconf_array) / sizeof(struct pad_conf_entry)); +} + +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + if (cs == CS1) + return NULL; + + *lpddr2_dev_details = elpida_2G_S4_details; + + return lpddr2_dev_details; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + *cs0_device_timings = &elpida_2G_S4_timings; + *cs1_device_timings = NULL; +} + +int board_init(void) +{ + /* GPMC init */ + gpmc_init(); + + /* MACH number */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; + + /* ATAGs location */ + gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100; + + return 0; +} + +int misc_init_r(void) +{ + char reboot_mode[2] = { 0 }; + u32 data = 0; + u32 value; + + /* Reboot mode */ + + omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); + + /* USB ID pin pull-up indicates factory (fastboot) cable detection. */ + gpio_request(KC1_GPIO_USB_ID, "USB_ID"); + gpio_direction_input(KC1_GPIO_USB_ID); + value = gpio_get_value(KC1_GPIO_USB_ID); + + if (value) + reboot_mode[0] = 'b'; + + if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { + if (reboot_mode[0] == 'o') + twl6030_power_off(); + + if (!getenv("reboot-mode")) + setenv("reboot-mode", (char *)reboot_mode); + + omap_reboot_mode_clear(); + } else { + /* Reboot mode garbage may still be valid, so clear it. */ + omap_reboot_mode_clear(); + + /* + * When not rebooting, valid power on reasons are either the + * power button, charger plug or USB plug. + */ + + data |= twl6030_input_power_button(); + data |= twl6030_input_charger(); + data |= twl6030_input_usb(); + + if (!data) + twl6030_power_off(); + } + + /* Serial number */ + + omap_die_id_serial(); + + /* MUSB */ + + musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE); + + return 0; +} + +u32 get_board_rev(void) +{ + u32 value = 0; + + gpio_request(KC1_GPIO_MBID0, "MBID0"); + gpio_request(KC1_GPIO_MBID1, "MBID1"); + gpio_request(KC1_GPIO_MBID2, "MBID2"); + gpio_request(KC1_GPIO_MBID3, "MBID3"); + + gpio_direction_input(KC1_GPIO_MBID0); + gpio_direction_input(KC1_GPIO_MBID1); + gpio_direction_input(KC1_GPIO_MBID2); + gpio_direction_input(KC1_GPIO_MBID3); + + value |= (gpio_get_value(KC1_GPIO_MBID0) << 0); + value |= (gpio_get_value(KC1_GPIO_MBID1) << 1); + value |= (gpio_get_value(KC1_GPIO_MBID2) << 2); + value |= (gpio_get_value(KC1_GPIO_MBID3) << 3); + + return value; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + omap_die_id_get_board_serial(serialnr); +} + +int fb_set_reboot_flag(void) +{ + return omap_reboot_mode_store("b"); +} + +#ifndef CONFIG_SPL_BUILD +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(1, 0, 0, -1, -1); +} +#endif + +void board_mmc_power_init(void) +{ + twl6030_power_mmc_init(1); +} diff --git a/board/amazon/kc1/kc1.h b/board/amazon/kc1/kc1.h new file mode 100644 index 0000000000..14737d7403 --- /dev/null +++ b/board/amazon/kc1/kc1.h @@ -0,0 +1,98 @@ +/* + * Amazon Kindle Fire (first generation) codename kc1 config + * + * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KC1_H_ +#define _KC1_H_ + +#include <asm/arch/mux_omap4.h> + +#define KC1_GPIO_USB_ID 52 +#define KC1_GPIO_MBID1 173 +#define KC1_GPIO_MBID0 174 +#define KC1_GPIO_MBID3 177 +#define KC1_GPIO_MBID2 178 + +const struct pad_conf_entry core_padconf_array[] = { + /* GPMC */ + { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */ + { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */ + { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */ + { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */ + { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */ + { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */ + { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */ + { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */ + { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */ + { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */ + { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */ + /* CAM */ + { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ + { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ + { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */ + /* HDQ */ + { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ + /* I2C1 */ + { I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */ + { I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */ + /* I2C2 */ + { I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */ + { I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */ + /* I2C3 */ + { I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */ + { I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */ + /* I2C4 */ + { I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */ + { I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */ + /* MCSPI1 */ + { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ + { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ + /* UART3 */ + { UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */ + { UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */ + { UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */ + { UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */ + /* SDMMC5 */ + { SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */ + { SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */ + { SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */ + { SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */ + { SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */ + { SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */ + /* MCSPI4 */ + { MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */ + { MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */ + { MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */ + { MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */ + /* UART4 */ + { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ + { UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */ + /* UNIPRO */ + { UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */ + { UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */ + { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */ + { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */ + { UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */ + { UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */ + { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */ + { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */ + { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */ + { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */ + { UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */ + { UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */ + /* USBA0_OTG */ + { USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */ + { USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */ + { USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */ +}; + +#endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 6efc8c183a..973b57969f 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -14,6 +14,7 @@ #include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> #include "pcie.h" +#include <asm/armv8/mmu.h> DECLARE_GLOBAL_DATA_PTR; @@ -28,6 +29,26 @@ U_BOOT_DEVICE(vexpress_serials) = { .platdata = &serial_platdata, }; +static struct mm_region vexpress64_mem_map[] = { + { + .base = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .base = 0x80000000UL, + .size = 0xff80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = vexpress64_mem_map; + /* This function gets replaced by platforms supporting PCIe. * The replacement function, eg. on Juno, initialises the PCIe bus. */ diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index b9267676dc..9131a385fd 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -10,6 +10,7 @@ #include <linux/compiler.h> #include <cavium/atf.h> +#include <asm/armv8/mmu.h> #if !CONFIG_IS_ENABLED(OF_CONTROL) #include <dm/platdata.h> @@ -42,6 +43,29 @@ U_BOOT_DEVICE(thunderx_serial1) = { DECLARE_GLOBAL_DATA_PTR; +static struct mm_region thunderx_mem_map[] = { + { + .base = 0x000000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE, + }, { + .base = 0x800000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, { + .base = 0x840000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = thunderx_mem_map; + int board_init(void) { return 0; diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c index 2b923624ae..2ed90de9d5 100644 --- a/board/cm5200/fwupdate.c +++ b/board/cm5200/fwupdate.c @@ -81,7 +81,7 @@ static int load_rescue_image(ulong addr) char dev[7]; char addr_str[16]; char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; - block_dev_desc_t *stor_dev = NULL; + struct blk_desc *stor_dev = NULL; cmd_tbl_t *bcmd; /* Get name of firmware directory */ @@ -117,7 +117,7 @@ static int load_rescue_image(ulong addr) /* Detect partition */ for (partno = -1, i = 0; i < 6; i++) { - if (get_partition_info(stor_dev, i, &info) == 0) { + if (part_get_info(stor_dev, i, &info) == 0) { if (fat_register_device(stor_dev, i) == 0) { /* Check if rescue image is present */ FW_DEBUG("Looking for firmware directory '%s'" diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 6d3b18ac18..b4f5d40654 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #if !defined(CONFIG_SPL_BUILD) -inline void set_muxconf_regs_essential(void){}; +inline void set_muxconf_regs(void){}; #endif const struct omap_sysinfo sysinfo = { diff --git a/board/compulab/cm_t54/mux.c b/board/compulab/cm_t54/mux.c index da353831c0..45d868f0df 100644 --- a/board/compulab/cm_t54/mux.c +++ b/board/compulab/cm_t54/mux.c @@ -75,10 +75,10 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; /* - * Routine: set_muxconf_regs_essential + * Routine: set_muxconf_regs * Description: setup board pinmux configuration. */ -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_essential, diff --git a/board/congatec/Kconfig b/board/congatec/Kconfig new file mode 100644 index 0000000000..1dc306e351 --- /dev/null +++ b/board/congatec/Kconfig @@ -0,0 +1,29 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_CONGATEC + +choice + prompt "Mainboard model" + optional + +config TARGET_CONGA_QEVAL20_QA3_E3845 + bool "congatec QEVAL 2.0 & conga-QA3/E3845" + help + This is the congatec Qseven 2.0 evaluation carrier board + (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM. + It contains an Atom E3845 with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/congatec/conga-qeval20-qa3-e3845/Kconfig" + +endif diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig new file mode 100644 index 0000000000..9f31238930 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -0,0 +1,28 @@ +if TARGET_CONGA_QEVAL20_QA3_E3845 + +config SYS_BOARD + default "conga-qeval20-qa3-e3845" + +config SYS_VENDOR + default "congatec" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "conga-qeval20-qa3-e3845" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS new file mode 100644 index 0000000000..5a4d4dcdd3 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS @@ -0,0 +1,7 @@ +congatec EVAL20-QA3-E3845 +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/congatec/conga-qeval20-qa3-e3845 +F: include/configs/conga-qeval20-qa3-e3845.h +F: configs/conga-qeval20-qa3-e3845_defconfig +F: arch/x86/dts/conga-qeval20-qa3-e3845.dts diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile new file mode 100644 index 0000000000..23b8748c69 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += conga-qeval20-qa3.o start.o diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c new file mode 100644 index 0000000000..6a946d5758 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <winbond_w83627.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the Winbond one can be used. + */ + setup_internal_uart(0); + + /* Enable the legacy UART in the Winbond W83627 Super IO chip */ + winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), + UART0_BASE, UART0_IRQ); + + return 0; +} + +int arch_early_init_r(void) +{ + return 0; +} diff --git a/board/congatec/conga-qeval20-qa3-e3845/start.S b/board/congatec/conga-qeval20-qa3-e3845/start.S new file mode 100644 index 0000000000..2c941a4a51 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 7110f350d5..bb7f778a8f 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -12,8 +12,3 @@ int arch_early_init_r(void) { return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c index 08958f91f6..1fbe36a399 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86/efi.c @@ -11,8 +11,3 @@ int arch_early_init_r(void) { return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 88b10a0f2f..67b4afee68 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -7,9 +7,11 @@ #include <common.h> #include <asm/io.h> #include <netdev.h> +#include <fdt_support.h> #include <fm_eth.h> #include <fsl_mdio.h> #include <fsl_dtsec.h> +#include <libfdt.h> #include <malloc.h> #include <asm/arch/fsl_serdes.h> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 66d974a40b..ec5fdbfe27 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -10,6 +10,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include <fdt_support.h> #include <hwconfig.h> #include <ahci.h> #include <mmc.h> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 4f816c4c02..f440ce6196 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_FAST) -#define ETH_PHY_RESET IMX_GPIO_NR(4, 21) +#define ETH_PHY_POWER IMX_GPIO_NR(4, 21) int dram_init(void) { @@ -154,10 +154,9 @@ static void setup_iomux_fec(void) { imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - /* Reset LAN8720 PHY */ - gpio_direction_output(ETH_PHY_RESET , 0); - udelay(25000); - gpio_set_value(ETH_PHY_RESET, 1); + /* Power up LAN8720 PHY */ + gpio_direction_output(ETH_PHY_POWER , 1); + udelay(15000); } #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) diff --git a/board/google/Kconfig b/board/google/Kconfig index e9559c9080..7ba73a2461 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -36,9 +36,22 @@ config TARGET_CHROMEBOX_PANTHER video output and a 16GB SATA solid state drive. There is no Chrome OS EC on this model. +config TARGET_CHROMEBOOK_SAMUS + bool "Chromebook samus" + help + This is the Chromebook Pixel released in 2015. It uses an Intel + Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of + LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a + 720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type + C ports which can support charging and up to a 4K external display. + There is a solid state drive, either 32GB or 64GB. There is a + Chrome OS EC connected on LPC, and it provides a 2560x1700 high + resolution touch-enabled LCD display. + endchoice source "board/google/chromebook_link/Kconfig" source "board/google/chromebox_panther/Kconfig" +source "board/google/chromebook_samus/Kconfig" endif diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index d12d74202c..42615e1e23 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -17,145 +17,7 @@ int arch_early_init_r(void) return 0; } -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ - .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ - .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ - .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ - .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ - .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ - .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ - .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ - .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ - .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ - .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio1 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_OUTPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio36 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -static const struct pch_gpio_map link_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - int board_early_init_f(void) { - ich_gpio_set_gpio_map(&link_gpio_map); - return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig new file mode 100644 index 0000000000..f2b9481563 --- /dev/null +++ b/board/google/chromebook_samus/Kconfig @@ -0,0 +1,40 @@ +if TARGET_CHROMEBOOK_SAMUS + +config SYS_BOARD + default "chromebook_samus" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "broadwell" + +config SYS_CONFIG_NAME + default "chromebook_samus" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BROADWELL + select HAVE_INTEL_ME + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + +config SYS_CAR_ADDR + hex + default 0xff7c0000 + +config SYS_CAR_SIZE + hex + default 0x40000 + +endif diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS new file mode 100644 index 0000000000..5500e46b40 --- /dev/null +++ b/board/google/chromebook_samus/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK SAMUS BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_defconfig diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile new file mode 100644 index 0000000000..152228678b --- /dev/null +++ b/board/google/chromebook_samus/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += samus.o diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c new file mode 100644 index 0000000000..3c3f5d4833 --- /dev/null +++ b/board/google/chromebook_samus/samus.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/cpu.h> + +int arch_early_init_r(void) +{ + return cpu_run_reference_code(); +} + +int board_early_init_f(void) +{ + return 0; +} diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index d492a0383f..e3baf88783 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -16,7 +16,3 @@ int board_early_init_f(void) { return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ -} diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index 81d6c82219..9671c5aa54 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -87,7 +87,7 @@ int misc_init_r(void) return 0; } -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_essential, @@ -115,8 +115,12 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } -#endif +void board_mmc_power_init(void) +{ + twl6030_power_mmc_init(0); +} +#endif #if defined(CONFIG_CMD_NET) diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index c4ae40bfb4..1edc807bd3 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -19,6 +19,7 @@ #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> #include <asm/arch/hi6220.h> +#include <asm/armv8/mmu.h> /*TODO drop this table in favour of device tree */ static const struct hikey_gpio_platdata hi6220_gpio[] = { @@ -87,6 +88,26 @@ U_BOOT_DEVICE(hikey_seriala) = { .platdata = &serial_platdata, }; +static struct mm_region hikey_mem_map[] = { + { + .base = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .base = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = hikey_mem_map; + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_uart_init(void) { diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c index ccbe860b14..846b2f7271 100644 --- a/board/intel/bayleybay/bayleybay.c +++ b/board/intel/bayleybay/bayleybay.c @@ -6,8 +6,3 @@ #include <common.h> #include <asm/gpio.h> - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c index 31a480a615..c350237fca 100644 --- a/board/intel/cougarcanyon2/cougarcanyon2.c +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -10,6 +10,7 @@ #include <pci.h> #include <smsc_sio1007.h> #include <asm/ibmpc.h> +#include <asm/lpc_common.h> #include <asm/pci.h> #include <asm/arch/pch.h> @@ -51,8 +52,3 @@ int board_early_init_f(void) return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 3a79e69112..562d6d1b03 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -18,8 +18,3 @@ int board_early_init_f(void) return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 212c9702d3..568bd4db49 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -65,8 +65,3 @@ void board_deassert_perst(void) val |= (1 << 0); outl(val, port); } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 44e5bf4bed..94b22edd57 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -9,13 +9,5 @@ int arch_early_init_r(void) { - /* do the pin-muxing */ - gpio_ich6_pinctrl_init(); - return 0; } - -void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) -{ - return; -} diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index e2fce50208..d1a6a6f56f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -34,9 +34,9 @@ static const u32 gpmc_lan_config[] = { #endif static const struct ns16550_platdata igep_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(igep_uart) = { diff --git a/board/lego/ev3/Kconfig b/board/lego/ev3/Kconfig new file mode 100644 index 0000000000..14b3f0c1cf --- /dev/null +++ b/board/lego/ev3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LEGOEV3 + +config SYS_BOARD + default "ev3" + +config SYS_VENDOR + default "lego" + +config SYS_CONFIG_NAME + default "legoev3" + +endif diff --git a/board/lego/ev3/MAINTAINERS b/board/lego/ev3/MAINTAINERS new file mode 100644 index 0000000000..11b3261609 --- /dev/null +++ b/board/lego/ev3/MAINTAINERS @@ -0,0 +1,6 @@ +LEGOEV3 BOARD +M: David Lechner <david@lechnology.com> +S: Maintained +F: board/lego/ev3/ +F: include/configs/legoev3.h +F: configs/legoev3_defconfig diff --git a/board/lego/ev3/Makefile b/board/lego/ev3/Makefile new file mode 100644 index 0000000000..f3e717ab66 --- /dev/null +++ b/board/lego/ev3/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += legoev3.o diff --git a/board/lego/ev3/README b/board/lego/ev3/README new file mode 100644 index 0000000000..1a50ca9d03 --- /dev/null +++ b/board/lego/ev3/README @@ -0,0 +1,32 @@ +Summary +======= + +LEGO MINDSTORMS EV3 is a toy robot produced by the LEGO Group. It is based +on the davinci da850 evm. The EV3 has a 16MB spi flash and a SDHC microSD card +reader. + +Booting +======= + +The EV3 contains a bootloader in EEPROM that loads u-boot.bin from address 0x0 +of the spi flash memory. Using the default configuration, u-boot will check to +see if there is a boot.scr file on the first FAT partition of the mmc. If there +is, it will run the script and boot the kernel from the uImage file also in +the FAT partition. Otherwise, it will load a kernel and rootfs from the flash. +The kernel must be stored at address 0x50000 on the flash and have a maximum +size of 3MiB. The rootfs must be a squasfs image and stored at 0x350000 in the +flash and have a maximum size of 9.3MiB. The flash starting at 0xCB0000 is +reserved for user data. + +Writing image to flash +====================== + +The EEPROM contains a program for uploading an image file to the flash memory. +The program is started by holding down the right button on the EV3 when powering +it on. You can also `run fwupdateboot` in the u-boot shell to reboot into this +mode. The image can then be uploaded using the official LEGO MINDSTORMS EV3 +software or a 3rd party program capable of uploading a firmware file. + +If you are booting from the microSD card, it is enough to just write uboot.bin +to the flash. If you are not using a microSD card, you will need to create an +image file using the layout described above. diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c new file mode 100644 index 0000000000..a791b97f8f --- /dev/null +++ b/board/lego/ev3/legoev3.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2016 David Lechner <david@lechnology.com> + * + * Based on da850evm.c + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <spi_flash.h> +#include <asm/arch/hardware.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/io.h> +#include <asm/arch/davinci_misc.h> +#include <asm/errno.h> +#include <hwconfig.h> + +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +u8 board_rev; + +#define EEPROM_I2C_ADDR 0x50 +#define EEPROM_REV_OFFSET 0x3F00 +#define EEPROM_MAC_OFFSET 0x3F06 + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); + + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd0); +} +#endif + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(spi0_pins_base), + PINMUX_ITEM(spi0_pins_scs0), + PINMUX_ITEM(uart1_pins_txrx), + PINMUX_ITEM(i2c0_pins), + PINMUX_ITEM(mmc0_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_SPI0 }, /* Serial Flash */ + { DAVINCI_LPSC_UART1 }, /* console */ + { DAVINCI_LPSC_MMC_SD }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +u32 get_board_rev(void) +{ + u8 buf[2]; + + if (!board_rev) { + if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) { + printf("\nBoard revision read failed!\n"); + } else { + /* + * Board rev 3 has MAC address at EEPROM_REV_OFFSET. + * Other revisions have checksum at EEPROM_REV_OFFSET+1 + * to detect this. + */ + if ((buf[0] ^ buf[1]) == 0xFF) + board_rev = buf[0]; + else + board_rev = 3; + } + } + + return board_rev; +} + +/* + * The Bluetooth MAC address serves as the board serial number. + */ +void get_board_serial(struct tag_serialnr *serialnr) +{ + u32 offset; + u8 buf[6]; + + if (!board_rev) + board_rev = get_board_rev(); + + /* Board rev 3 has MAC address where rev should be */ + offset = (board_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_MAC_OFFSET; + + if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) { + printf("\nBoard serial read failed!\n"); + } else { + u8 *nr; + + nr = (u8 *)&serialnr->low; + nr[0] = buf[5]; + nr[1] = buf[4]; + nr[2] = buf[3]; + nr[3] = buf[2]; + nr = (u8 *)&serialnr->high; + nr[0] = buf[1]; + nr[1] = buf[0]; + nr[2] = 0; + nr[3] = 0; + } +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* arch number of the board */ + /* LEGO didn't register for a unique number and uses da850evm */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART1), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart1_ctrl_regs->pwremu_mgmt); + + return 0; +} diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index f093f97e2b..29a7045334 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -109,7 +109,7 @@ int misc_init_r(void) /* Reboot mode */ - reboot_mode[0] = omap_reboot_mode(); + omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); if (keys[0]) reboot_mode[0] = 'r'; @@ -122,6 +122,9 @@ int misc_init_r(void) omap_reboot_mode_clear(); } else { + /* Reboot mode garbage may still be valid, so clear it. */ + omap_reboot_mode_clear(); + /* * When not rebooting, valid power on reasons are either the * power button, charger plug or USB plug. @@ -157,14 +160,9 @@ void get_board_serial(struct tag_serialnr *serialnr) omap_die_id_get_board_serial(serialnr); } -void reset_misc(void) -{ - omap_reboot_mode_store('u'); -} - int fb_set_reboot_flag(void) { - return omap_reboot_mode_store('b'); + return omap_reboot_mode_store("b"); } #ifndef CONFIG_SPL_BUILD diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 668f68476e..51d2987566 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -47,9 +47,9 @@ DECLARE_GLOBAL_DATA_PTR; */ static const struct ns16550_platdata omap3logic_serial = { - OMAP34XX_UART1, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART1, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(omap3logic_uart) = { diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 4040114ce0..982619cd7b 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -44,9 +44,9 @@ static const u32 gpmc_lab_enet[] = { }; static const struct ns16550_platdata zoom1_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(zoom1_uart) = { diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README index 1b73dbe5ed..e900c56f15 100644 --- a/board/mpl/pip405/README +++ b/board/mpl/pip405/README @@ -217,8 +217,8 @@ Added files: Block device changes: --------------------- To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter -block_dev_desc will be used when accessing the functions in these files. The block -device descriptor (block_dev_desc) contains a pointer to the read routine of the +blk_desc will be used when accessing the functions in these files. The block +device descriptor (blk_desc) contains a pointer to the read routine of the device, which will be used to read blocks from the device. Renamed function ide_print to dev_print and moved it to the file disk/part.c to use it for IDE ATAPI and SCSI devices. diff --git a/board/overo/overo.c b/board/overo/overo.c index a38b959cb2..40f13e5876 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -68,9 +68,9 @@ static struct { } expansion_config = {0x0}; static const struct ns16550_platdata overo_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(overo_uart) = { diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index 21793e85c4..77e4482906 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -91,9 +91,9 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif static const struct ns16550_platdata cairo_serial = { - OMAP34XX_UART2, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART2, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(cairo_uart) = { diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 15b7af634c..80eae9cd48 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -337,8 +337,8 @@ int board_mmc_init(bd_t *bis) if (!sunxi_mmc_has_egon_boot_signature(mmc0) && sunxi_mmc_has_egon_boot_signature(mmc1)) { /* Booting from emmc / mmc2, swap */ - mmc0->block_dev.dev = 1; - mmc1->block_dev.dev = 0; + mmc0->block_dev.devnum = 1; + mmc1->block_dev.devnum = 0; } #endif diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index 49b73abc20..11ef3caf39 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -38,4 +38,6 @@ config NOR_BOOT as the ROM only partially sets up pinmux. We also default to using NOR for environment. +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f56d17ec58..4330be6499 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -31,6 +31,7 @@ #include <environment.h> #include <watchdog.h> #include <environment.h> +#include "../common/board_detect.h" #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -46,43 +47,9 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(struct am335x_baseboard_id *header) +static inline int __maybe_unused read_eeprom(void) { - /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { - puts("Could not probe the EEPROM; something fundamentally " - "wrong on the I2C bus.\n"); - return -ENODEV; - } - - /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, - sizeof(struct am335x_baseboard_id))) { - puts("Could not read the EEPROM; something fundamentally" - " wrong on the I2C bus.\n"); - return -EIO; - } - - if (header->magic != 0xEE3355AA) { - /* - * read the eeprom using i2c again, - * but use only a 1 byte address - */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, - sizeof(struct am335x_baseboard_id))) { - puts("Could not read the EEPROM; something " - "fundamentally wrong on the I2C bus.\n"); - return -EIO; - } - - if (header->magic != 0xEE3355AA) { - printf("Incorrect magic number (0x%x) in EEPROM\n", - header->magic); - return -EINVAL; - } - } - - return 0; + return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); } #ifndef CONFIG_SKIP_LOWLEVEL_INIT @@ -223,16 +190,15 @@ const struct dpll_params dpll_ddr_bone_black = { void am33xx_spl_board_init(void) { - struct am335x_baseboard_id header; int mpu_vdd; - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - if (board_is_bone(&header) || board_is_bone_lt(&header)) { + if (board_is_bone() || board_is_bone_lt()) { /* BeagleBone PMIC Code */ int usb_cur_lim; @@ -240,8 +206,7 @@ void am33xx_spl_board_init(void) * Only perform PMIC configurations if board rev > A1 * on Beaglebone White */ - if (board_is_bone(&header) && !strncmp(header.version, - "00A1", 4)) + if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) return; if (i2c_probe(TPS65217_CHIP_PM)) @@ -251,7 +216,7 @@ void am33xx_spl_board_init(void) * On Beaglebone White we need to ensure we have AC power * before increasing the frequency. */ - if (board_is_bone(&header)) { + if (board_is_bone()) { uchar pmic_status_reg; if (tps65217_reg_read(TPS65217_STATUS, &pmic_status_reg)) @@ -266,7 +231,7 @@ void am33xx_spl_board_init(void) * Override what we have detected since we know if we have * a Beaglebone Black it supports 1GHz. */ - if (board_is_bone_lt(&header)) + if (board_is_bone_lt()) dpll_mpu_opp100.m = MPUPLL_M_1000; /* @@ -307,7 +272,7 @@ void am33xx_spl_board_init(void) * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ - if (board_is_bone(&header)) { + if (board_is_bone()) { if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_3_3, @@ -367,18 +332,16 @@ void am33xx_spl_board_init(void) const struct dpll_params *get_dpll_ddr_params(void) { - struct am335x_baseboard_id header; - enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); - if (board_is_evm_sk(&header)) + if (board_is_evm_sk()) return &dpll_ddr_evm_sk; - else if (board_is_bone_lt(&header)) + else if (board_is_bone_lt()) return &dpll_ddr_bone_black; - else if (board_is_evm_15_or_later(&header)) + else if (board_is_evm_15_or_later()) return &dpll_ddr_evm_sk; else return &dpll_ddr; @@ -403,12 +366,10 @@ void set_uart_mux_conf(void) void set_mux_conf_regs(void) { - __maybe_unused struct am335x_baseboard_id header; - - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); - enable_board_pin_mux(&header); + enable_board_pin_mux(); } const struct ctrl_ioregs ioregs_evmsk = { @@ -445,12 +406,10 @@ const struct ctrl_ioregs ioregs = { void sdram_init(void) { - __maybe_unused struct am335x_baseboard_id header; - - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); - if (board_is_evm_sk(&header)) { + if (board_is_evm_sk()) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. @@ -459,15 +418,15 @@ void sdram_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk(&header)) + if (board_is_evm_sk()) config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); - else if (board_is_bone_lt(&header)) + else if (board_is_bone_lt()) config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); - else if (board_is_evm_15_or_later(&header)) + else if (board_is_evm_15_or_later()) config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else @@ -496,26 +455,16 @@ int board_init(void) int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - char safe_string[HDR_NAME_LEN + 1]; - struct am335x_baseboard_id header; + int rc; + char *name = NULL; - if (read_eeprom(&header) < 0) + rc = read_eeprom(); + if (rc) puts("Could not get board ID.\n"); - /* Now set variables based on the header. */ - strncpy(safe_string, (char *)header.name, sizeof(header.name)); - safe_string[sizeof(header.name)] = 0; - setenv("board_name", safe_string); - - /* BeagleBone Green eeprom, board_rev: 0x1a 0x00 0x00 0x00 */ - if ( (header.version[0] == 0x1a) && (header.version[1] == 0x00) && - (header.version[2] == 0x00) && (header.version[3] == 0x00) ) { - setenv("board_rev", "BBG1"); - } else { - strncpy(safe_string, (char *)header.version, sizeof(header.version)); - safe_string[sizeof(header.version)] = 0; - setenv("board_rev", safe_string); - } + if (board_is_bbg1()) + name = "BBG1"; + set_board_info_env(name); #endif return 0; @@ -587,7 +536,7 @@ int board_eth_init(bd_t *bis) int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; - __maybe_unused struct am335x_baseboard_id header; + __maybe_unused struct ti_am_eeprom *header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); @@ -624,11 +573,11 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("eth1addr", mac_addr); } - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); - if (board_is_bone(&header) || board_is_bone_lt(&header) || - board_is_idk(&header)) { + if (board_is_bone() || board_is_bone_lt() || + board_is_idk()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; @@ -657,7 +606,7 @@ int board_eth_init(bd_t *bis) #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 - if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { + if (board_is_evm_sk() || board_is_gp_evm()) { const char *devname; devname = miiphy_get_current_dev(); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index bc700d56fe..062c34512f 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -11,53 +11,40 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -/* - * TI AM335x parts define a system EEPROM that defines certain sub-fields. - * We use these fields to in turn see what board we are on, and what - * that might require us to set or not set. - */ -#define HDR_NO_OF_MAC_ADDR 3 -#define HDR_ETH_ALEN 6 -#define HDR_NAME_LEN 8 - -struct am335x_baseboard_id { - unsigned int magic; - char name[HDR_NAME_LEN]; - char version[4]; - char serial[12]; - char config[32]; - char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; -}; +static inline int board_is_bone(void) +{ + return board_ti_is("A335BONE"); +} -static inline int board_is_bone(struct am335x_baseboard_id *header) +static inline int board_is_bone_lt(void) { - return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); + return board_ti_is("A335BNLT"); } -static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +static inline int board_is_bbg1(void) { - return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); + return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4); } -static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +static inline int board_is_evm_sk(void) { - return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); + return board_ti_is("A335X_SK"); } -static inline int board_is_idk(struct am335x_baseboard_id *header) +static inline int board_is_idk(void) { - return !strncmp(header->config, "SKU#02", 6); + return !strncmp(board_ti_get_config(), "SKU#02", 6); } -static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +static inline int board_is_gp_evm(void) { - return !strncmp("A33515BB", header->name, HDR_NAME_LEN); + return board_ti_is("A33515BB"); } -static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +static inline int board_is_evm_15_or_later(void) { - return (board_is_gp_evm(header) && - strncmp("1.5", header->version, 3) <= 0); + return (board_is_gp_evm() && + strncmp("1.5", board_ti_get_rev(), 3) <= 0); } /* @@ -73,5 +60,5 @@ void enable_uart3_pin_mux(void); void enable_uart4_pin_mux(void); void enable_uart5_pin_mux(void); void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(struct am335x_baseboard_id *header); +void enable_board_pin_mux(void); #endif diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 79ed02f68f..fdf827fe54 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -19,6 +19,7 @@ #include <asm/arch/mux.h> #include <asm/io.h> #include <i2c.h> +#include "../common/board_detect.h" #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { @@ -312,10 +313,10 @@ static unsigned short detect_daughter_board_profile(void) return (1 << (val & PROFILE_MASK)); } -void enable_board_pin_mux(struct am335x_baseboard_id *header) +void enable_board_pin_mux(void) { /* Do board-specific muxes. */ - if (board_is_bone(header)) { + if (board_is_bone()) { /* Beaglebone pinmux */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); @@ -326,7 +327,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) #else configure_module_pin_mux(mmc1_pin_mux); #endif - } else if (board_is_gp_evm(header)) { + } else if (board_is_gp_evm()) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); @@ -343,17 +344,17 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } - } else if (board_is_idk(header)) { + } else if (board_is_idk()) { /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); - } else if (board_is_evm_sk(header)) { + } else if (board_is_evm_sk()) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); - } else if (board_is_bone_lt(header)) { + } else if (board_is_bone_lt()) { /* Beaglebone LT pinmux */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index 78f294af40..a56cc8216b 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -59,6 +59,36 @@ SECTIONS . = ALIGN(4); + .__efi_runtime_start : { + *(.__efi_runtime_start) + } + + .efi_runtime : { + *(efi_runtime_text) + *(efi_runtime_data) + } + + .__efi_runtime_stop : { + *(.__efi_runtime_stop) + } + + .efi_runtime_rel_start : + { + *(.__efi_runtime_rel_start) + } + + .efi_runtime_rel : { + *(.relefi_runtime_text) + *(.relefi_runtime_data) + } + + .efi_runtime_rel_stop : + { + *(.__efi_runtime_rel_stop) + } + + . = ALIGN(4); + .image_copy_end : { *(.__image_copy_end) diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig index 8d1c16883d..9cb80cc3f1 100644 --- a/board/ti/am43xx/Kconfig +++ b/board/ti/am43xx/Kconfig @@ -12,4 +12,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "am43xx_evm" +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 770726c3f7..d208d2fa89 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,6 +19,7 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/gpio.h> #include <asm/emif.h> +#include "../common/board_detect.h" #include "board.h" #include <power/pmic.h> #include <power/tps65218.h> @@ -37,48 +38,9 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(struct am43xx_board_id *header) +static inline int __maybe_unused read_eeprom(void) { - /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { - printf("Could not probe the EEPROM at 0x%x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return -ENODEV; - } - - /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, - sizeof(struct am43xx_board_id))) { - printf("Could not read the EEPROM\n"); - return -EIO; - } - - if (header->magic != 0xEE3355AA) { - /* - * read the eeprom using i2c again, - * but use only a 1 byte address - */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, - sizeof(struct am43xx_board_id))) { - printf("Could not read the EEPROM at 0x%x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return -EIO; - } - - if (header->magic != 0xEE3355AA) { - printf("Incorrect magic number (0x%x) in EEPROM\n", - header->magic); - return -EINVAL; - } - } - - strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); - am43xx_board_name[sizeof(header->name)] = 0; - - strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); - am43xx_board_rev[sizeof(header->version)] = 0; - - return 0; + return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); } #ifndef CONFIG_SKIP_LOWLEVEL_INIT @@ -374,6 +336,9 @@ const struct dpll_params *get_dpll_ddr_params(void) { int ind = get_sys_clk_index(); + if (read_eeprom() < 0) + return NULL; + if (board_is_eposevm()) return &epos_evm_dpll_ddr[ind]; else if (board_is_gpevm() || board_is_sk()) @@ -381,7 +346,7 @@ const struct dpll_params *get_dpll_ddr_params(void) else if (board_is_idk()) return &idk_dpll_ddr; - printf(" Board '%s' not supported\n", am43xx_board_name); + printf(" Board '%s' not supported\n", board_ti_get_name()); return NULL; } @@ -512,16 +477,29 @@ void scale_vcores_idk(u32 m) } } +void gpi2c_init(void) +{ + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (first_time) { + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + first_time = false; + } +} + void scale_vcores(void) { const struct dpll_params *mpu_params; - struct am43xx_board_id header; - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (read_eeprom(&header) < 0) + if (read_eeprom() < 0) puts("Could not get board ID.\n"); + /* Ensure I2C is initialized for PMIC configuration */ + gpi2c_init(); + /* Get the frequency */ mpu_params = get_dpll_mpu_params(); @@ -558,6 +536,8 @@ static void enable_vtt_regulator(void) void sdram_init(void) { + if (read_eeprom() < 0) + return; /* * EPOS EVM has 1GB LPDDR2 connected to EMIF. * GP EMV has 1GB DDR3 connected to EMIF @@ -655,20 +635,7 @@ int board_init(void) int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - char safe_string[HDR_NAME_LEN + 1]; - struct am43xx_board_id header; - - if (read_eeprom(&header) < 0) - puts("Could not get board ID.\n"); - - /* Now set variables based on the header. */ - strncpy(safe_string, (char *)header.name, sizeof(header.name)); - safe_string[sizeof(header.name)] = 0; - setenv("board_name", safe_string); - - strncpy(safe_string, (char *)header.version, sizeof(header.version)); - safe_string[sizeof(header.version)] = 0; - setenv("board_rev", safe_string); + set_board_info_env(NULL); #endif return 0; } diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index eb9493e191..2cf7a7751d 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -14,58 +14,37 @@ #include <asm/arch/omap.h> -static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; -static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START; - -/* - * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. - * We use these fields to in turn see what board we are on, and what - * that might require us to set or not set. - */ -#define HDR_NO_OF_MAC_ADDR 3 -#define HDR_ETH_ALEN 6 -#define HDR_NAME_LEN 8 - -#define DEV_ATTR_MAX_OFFSET 5 -#define DEV_ATTR_MIN_OFFSET 0 - -struct am43xx_board_id { - unsigned int magic; - char name[HDR_NAME_LEN]; - char version[4]; - char serial[12]; - char config[32]; - char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; -}; +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 static inline int board_is_eposevm(void) { - return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); + return board_ti_is("AM43EPOS"); } static inline int board_is_gpevm(void) { - return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); + return board_ti_is("AM43__GP"); } static inline int board_is_sk(void) { - return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN); + return board_ti_is("AM43__SK"); } static inline int board_is_idk(void) { - return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN); + return board_ti_is("AM43_IDK"); } static inline int board_is_evm_14_or_later(void) { - return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0); + return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0); } static inline int board_is_evm_12_or_later(void) { - return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0); + return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0); } void enable_uart0_pin_mux(void); diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 510477dad9..e03b1bcfaa 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> +#include "../common/board_detect.h" #include "board.h" static struct module_pin_mux rmii1_pin_mux[] = { diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig index bdb779511b..17745ff7ea 100644 --- a/board/ti/am57xx/Kconfig +++ b/board/ti/am57xx/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am57xx_evm" +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 042f9ab196..67191af405 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -30,8 +30,12 @@ #include <dwc3-omap-uboot.h> #include <ti-usb-phy-uboot.h> +#include "../common/board_detect.h" #include "mux_data.h" +#define board_is_x15() board_ti_is("BBRDX15_") +#define board_is_am572x_evm() board_ti_is("AM572PM_") + #ifdef CONFIG_DRIVER_TI_CPSW #include <cpsw.h> #endif @@ -41,8 +45,10 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO 7_11 */ #define GPIO_DDR_VTT_EN 203 +#define SYSINFO_BOARD_NAME_MAX_LEN 45 + const struct omap_sysinfo sysinfo = { - "Board: BeagleBoard x15\n" + "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" }; static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { @@ -58,22 +64,22 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, + .sdram_config2 = 0x08000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, + .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00740074, - .emif_ddr_ext_phy_ctrl_3 = 0x00780078, - .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, - .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -83,39 +89,35 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { /* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x10040100, - 0x00740074, - 0x00780078, - 0x007c007c, - 0x007b007b, - 0x00800080, - 0x00360036, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, 0x00340034, - 0x00360036, - 0x00350035, 0x00350035, - - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - - 0x00430043, - 0x003e003e, - 0x004a004a, - 0x00470047, - 0x00400040, - + 0x00340034, + 0x00310031, + 0x00340034, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, 0x00000000, 0x00600020, 0x40011080, 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0, 0x0, 0x0, @@ -126,22 +128,22 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, + .sdram_config2 = 0x08000000, .ref_ctrl = 0x000040F1, .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, + .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00820082, - .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, - .emif_ddr_ext_phy_ctrl_4 = 0x00800080, - .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -150,37 +152,35 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x10040100, - 0x00820082, - 0x008b008b, - 0x00800080, - 0x007e007e, - 0x00800080, - 0x00370037, - 0x00390039, - 0x00360036, - 0x00370037, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, + 0x00980098, + 0x00340034, 0x00350035, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x00540054, - 0x00540054, - 0x004e004e, - 0x004c004c, - 0x00400040, - + 0x00340034, + 0x00310031, + 0x00340034, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, 0x00000000, 0x00600020, 0x40011080, 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0, 0x0, 0x0, @@ -246,6 +246,66 @@ struct vcores_data beagle_x15_volts = { .iva.pmic = &tps659038, }; +#ifdef CONFIG_SPL_BUILD +/* No env to setup for SPL */ +static inline void setup_board_eeprom_env(void) { } + +/* Override function to read eeprom information */ +void do_board_detect(void) +{ + int rc; + + rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); +} + +#else /* CONFIG_SPL_BUILD */ + +/* Override function to read eeprom information: actual i2c read done by SPL*/ +void do_board_detect(void) +{ + char *bname = NULL; + int rc; + + rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); + + if (board_is_x15()) + bname = "BeagleBoard X15"; + else if (board_is_am572x_evm()) + bname = "AM572x EVM"; + + if (bname) + snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, + "Board: %s REV %s\n", bname, board_ti_get_rev()); +} + +static void setup_board_eeprom_env(void) +{ + char *name = "beagle_x15"; + int rc; + + rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + goto invalid_eeprom; + + if (board_is_am572x_evm()) + name = "am57xx_evm"; + else + printf("Unidentified board claims %s in eeprom header\n", + board_ti_get_name()); + +invalid_eeprom: + set_board_info_env(name); +} + +#endif /* CONFIG_SPL_BUILD */ + void hw_data_init(void) { *prcm = &dra7xx_prcm; @@ -265,6 +325,8 @@ int board_init(void) int board_late_init(void) { init_sata(0); + setup_board_eeprom_env(); + /* * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds * This is the POWERHOLD-in-Low behavior. @@ -273,7 +335,7 @@ int board_late_init(void) return 0; } -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux32((*ctrl)->control_padconf_core_base, early_padconf, ARRAY_SIZE(early_padconf)); diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ff317efc2c..0ed4f52771 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -73,9 +73,9 @@ static struct { } expansion_config; static const struct ns16550_platdata beagle_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(beagle_uart) = { diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig new file mode 100644 index 0000000000..adf73abc93 --- /dev/null +++ b/board/ti/common/Kconfig @@ -0,0 +1,5 @@ +config TI_I2C_BOARD_DETECT + bool "Support for Board detection for TI platforms" + help + Support for detection board information on Texas Instrument's + Evaluation Boards which have I2C based EEPROM detection diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile new file mode 100644 index 0000000000..7170eac81e --- /dev/null +++ b/board/ti/common/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c new file mode 100644 index 0000000000..e0ae1a51a6 --- /dev/null +++ b/board/ti/common/board_detect.c @@ -0,0 +1,318 @@ +/* + * Library to support early TI EVM EEPROM handling + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + * Steve Kipisz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/omap_common.h> +#include <i2c.h> + +#include "board_detect.h" + +/** + * ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device + * @i2c_bus: i2c bus number to initialize + * @dev_addr: Device address to probe for + * + * Return: 0 on success or corresponding error on failure. + */ +static int __maybe_unused ti_i2c_eeprom_init(int i2c_bus, int dev_addr) +{ + int rc; + + if (i2c_bus >= 0) { + rc = i2c_set_bus_num(i2c_bus); + if (rc) + return rc; + } + + return i2c_probe(dev_addr); +} + +/** + * ti_i2c_eeprom_read - Read data from an EEPROM + * @dev_addr: The device address of the EEPROM + * @offset: Offset to start reading in the EEPROM + * @ep: Pointer to a buffer to read into + * @epsize: Size of buffer + * + * Return: 0 on success or corresponding result of i2c_read + */ +static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset, + uchar *ep, int epsize) +{ + return i2c_read(dev_addr, offset, 2, ep, epsize); +} + +/** + * ti_eeprom_string_cleanup() - Handle eeprom programming errors + * @s: eeprom string (should be NULL terminated) + * + * Some Board manufacturers do not add a NULL termination at the + * end of string, instead some binary information is kludged in, hence + * convert the string to just printable characters of ASCII chart. + */ +static void __maybe_unused ti_eeprom_string_cleanup(char *s) +{ + int i, l; + + l = strlen(s); + for (i = 0; i < l; i++, s++) + if (*s < ' ' || *s > '~') { + *s = 0; + break; + } +} + +__weak void gpi2c_init(void) +{ +} + +static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, + u32 header, u32 size, uint8_t *ep) +{ + u32 byte, hdr_read; + int rc; + + gpi2c_init(); + rc = ti_i2c_eeprom_init(bus_addr, dev_addr); + if (rc) + return rc; + + /* + * Read the header first then only read the other contents. + */ + byte = 2; + rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); + if (rc) + return rc; + + /* Corrupted data??? */ + if (hdr_read != header) { + rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); + /* + * read the eeprom header using i2c again, but use only a + * 1 byte address (some legacy boards need this..) + */ + byte = 1; + if (rc) + rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, + 4); + if (rc) + return rc; + } + if (hdr_read != header) + return -1; + + rc = i2c_read(dev_addr, 0x0, byte, ep, size); + if (rc) + return rc; + + return 0; +} + +int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr) +{ + int rc; + struct ti_am_eeprom am_ep; + struct ti_common_eeprom *ep; + + ep = TI_EEPROM_DATA; + if (ep->header == TI_EEPROM_HEADER_MAGIC) + goto already_read; + + /* Initialize with a known bad marker for i2c fails.. */ + ep->header = TI_DEAD_EEPROM_MAGIC; + ep->name[0] = 0x0; + ep->version[0] = 0x0; + ep->serial[0] = 0x0; + + rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC, + sizeof(am_ep), (uint8_t *)&am_ep); + if (rc) + return rc; + + ep->header = am_ep.header; + strlcpy(ep->name, am_ep.name, TI_EEPROM_HDR_NAME_LEN + 1); + ti_eeprom_string_cleanup(ep->name); + + /* BeagleBone Green '1' eeprom, board_rev: 0x1a 0x00 0x00 0x00 */ + if (am_ep.version[0] == 0x1a && am_ep.version[1] == 0x00 && + am_ep.version[2] == 0x00 && am_ep.version[3] == 0x00) + strlcpy(ep->version, "BBG1", TI_EEPROM_HDR_REV_LEN + 1); + else + strlcpy(ep->version, am_ep.version, TI_EEPROM_HDR_REV_LEN + 1); + ti_eeprom_string_cleanup(ep->version); + strlcpy(ep->serial, am_ep.serial, TI_EEPROM_HDR_SERIAL_LEN + 1); + ti_eeprom_string_cleanup(ep->serial); + strlcpy(ep->config, am_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1); + ti_eeprom_string_cleanup(ep->config); + + memcpy(ep->mac_addr, am_ep.mac_addr, + TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN); + +already_read: + return 0; +} + +int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr) +{ + int rc, offset = 0; + struct dra7_eeprom dra7_ep; + struct ti_common_eeprom *ep; + + ep = TI_EEPROM_DATA; + if (ep->header == DRA7_EEPROM_HEADER_MAGIC) + goto already_read; + + /* Initialize with a known bad marker for i2c fails.. */ + ep->header = 0xADEAD12C; + ep->name[0] = 0x0; + ep->version[0] = 0x0; + ep->serial[0] = 0x0; + ep->emif1_size = 0; + ep->emif2_size = 0; + + rc = ti_i2c_eeprom_get(bus_addr, dev_addr, DRA7_EEPROM_HEADER_MAGIC, + sizeof(dra7_ep), (uint8_t *)&dra7_ep); + if (rc) + return rc; + + ep->header = dra7_ep.header; + strlcpy(ep->name, dra7_ep.name, TI_EEPROM_HDR_NAME_LEN + 1); + ti_eeprom_string_cleanup(ep->name); + + offset = dra7_ep.version_major - 1; + + /* Rev F is skipped */ + if (offset >= 5) + offset = offset + 1; + snprintf(ep->version, TI_EEPROM_HDR_REV_LEN + 1, "%c.%d", + 'A' + offset, dra7_ep.version_minor); + ti_eeprom_string_cleanup(ep->version); + ep->emif1_size = (u64)dra7_ep.emif1_size; + ep->emif2_size = (u64)dra7_ep.emif2_size; + strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1); + ti_eeprom_string_cleanup(ep->config); + +already_read: + return 0; +} + +bool __maybe_unused board_ti_is(char *name_tag) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + return false; + return !strncmp(ep->name, name_tag, TI_EEPROM_HDR_NAME_LEN); +} + +bool __maybe_unused board_ti_rev_is(char *rev_tag, int cmp_len) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + int l; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + return false; + + l = cmp_len > TI_EEPROM_HDR_REV_LEN ? TI_EEPROM_HDR_REV_LEN : cmp_len; + return !strncmp(ep->version, rev_tag, l); +} + +char * __maybe_unused board_ti_get_rev(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + return NULL; + + return ep->version; +} + +char * __maybe_unused board_ti_get_config(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + return NULL; + + return ep->config; +} + +char * __maybe_unused board_ti_get_name(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + return NULL; + + return ep->name; +} + +void __maybe_unused +board_ti_get_eth_mac_addr(int index, + u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header == TI_DEAD_EEPROM_MAGIC) + goto fail; + + if (index < 0 || index >= TI_EEPROM_HDR_NO_OF_MAC_ADDR) + goto fail; + + memcpy(mac_addr, ep->mac_addr[index], TI_EEPROM_HDR_ETH_ALEN); + return; + +fail: + memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN); +} + +u64 __maybe_unused board_ti_get_emif1_size(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header != DRA7_EEPROM_HEADER_MAGIC) + return 0; + + return ep->emif1_size; +} + +u64 __maybe_unused board_ti_get_emif2_size(void) +{ + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (ep->header != DRA7_EEPROM_HEADER_MAGIC) + return 0; + + return ep->emif2_size; +} + +void __maybe_unused set_board_info_env(char *name) +{ + char *unknown = "unknown"; + struct ti_common_eeprom *ep = TI_EEPROM_DATA; + + if (name) + setenv("board_name", name); + else if (ep->name) + setenv("board_name", ep->name); + else + setenv("board_name", unknown); + + if (ep->version) + setenv("board_rev", ep->version); + else + setenv("board_rev", unknown); + + if (ep->serial) + setenv("board_serial", ep->serial); + else + setenv("board_serial", unknown); +} diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h new file mode 100644 index 0000000000..eb17f6f52a --- /dev/null +++ b/board/ti/common/board_detect.h @@ -0,0 +1,196 @@ +/* + * Library to support early TI EVM EEPROM handling + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_DETECT_H +#define __BOARD_DETECT_H + +/* TI EEPROM MAGIC Header identifier */ +#define TI_EEPROM_HEADER_MAGIC 0xEE3355AA +#define TI_DEAD_EEPROM_MAGIC 0xADEAD12C + +#define TI_EEPROM_HDR_NAME_LEN 8 +#define TI_EEPROM_HDR_REV_LEN 4 +#define TI_EEPROM_HDR_SERIAL_LEN 12 +#define TI_EEPROM_HDR_CONFIG_LEN 32 +#define TI_EEPROM_HDR_NO_OF_MAC_ADDR 3 +#define TI_EEPROM_HDR_ETH_ALEN 6 + +/** + * struct ti_am_eeprom - This structure holds data read in from the + * AM335x, AM437x, AM57xx TI EVM EEPROMs. + * @header: This holds the magic number + * @name: The name of the board + * @version: Board revision + * @serial: Board serial number + * @config: Reserved + * @mac_addr: Any MAC addresses written in the EEPROM + * + * The data is this structure is read from the EEPROM on the board. + * It is used for board detection which is based on name. It is used + * to configure specific TI boards. This allows booting of multiple + * TI boards with a single MLO and u-boot. + */ +struct ti_am_eeprom { + unsigned int header; + char name[TI_EEPROM_HDR_NAME_LEN]; + char version[TI_EEPROM_HDR_REV_LEN]; + char serial[TI_EEPROM_HDR_SERIAL_LEN]; + char config[TI_EEPROM_HDR_CONFIG_LEN]; + char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; +} __attribute__ ((__packed__)); + +/* DRA7 EEPROM MAGIC Header identifier */ +#define DRA7_EEPROM_HEADER_MAGIC 0xAA5533EE +#define DRA7_EEPROM_HDR_NAME_LEN 16 +#define DRA7_EEPROM_HDR_CONFIG_LEN 4 + +/** + * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM + * EEPROMs. + * @header: This holds the magic number + * @name: The name of the board + * @version_major: Board major version + * @version_minor: Board minor version + * @config: Board specific config options + * @emif1_size: Size of DDR attached to EMIF1 + * @emif2_size: Size of DDR attached to EMIF2 + * + * The data is this structure is read from the EEPROM on the board. + * It is used for board detection which is based on name. It is used + * to configure specific DRA7 boards. This allows booting of multiple + * DRA7 boards with a single MLO and u-boot. + */ +struct dra7_eeprom { + u32 header; + char name[DRA7_EEPROM_HDR_NAME_LEN]; + u16 version_major; + u16 version_minor; + char config[DRA7_EEPROM_HDR_CONFIG_LEN]; + u32 emif1_size; + u32 emif2_size; +} __attribute__ ((__packed__)); + +/** + * struct ti_common_eeprom - Null terminated, usable EEPROM contents. + * header: Magic number + * @name: NULL terminated name + * @version: NULL terminated version + * @serial: NULL terminated serial number + * @config: NULL terminated Board specific config options + * @mac_addr: MAC addresses + * @emif1_size: Size of the ddr available on emif1 + * @emif2_size: Size of the ddr available on emif2 + */ +struct ti_common_eeprom { + u32 header; + char name[TI_EEPROM_HDR_NAME_LEN + 1]; + char version[TI_EEPROM_HDR_REV_LEN + 1]; + char serial[TI_EEPROM_HDR_SERIAL_LEN + 1]; + char config[TI_EEPROM_HDR_CONFIG_LEN + 1]; + char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; + u64 emif1_size; + u64 emif2_size; +}; + +#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\ + OMAP_SRAM_SCRATCH_BOARD_EEPROM_START) + +/** + * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs + * @bus_addr: I2C bus address + * @dev_addr: I2C slave address + * + * ep in SRAM is populated by the this AM generic function that consolidates + * the basic initialization logic common across all AM* platforms. + */ +int ti_i2c_eeprom_am_get(int bus_addr, int dev_addr); + +/** + * ti_i2c_eeprom_dra7_get() - Consolidated eeprom data for DRA7 TI EVMs + * @bus_addr: I2C bus address + * @dev_addr: I2C slave address + */ +int ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr); + +/** + * board_ti_is() - Board detection logic for TI EVMs + * @name_tag: Tag used in eeprom for the board + * + * Return: false if board information does not match OR eeprom wasn't read. + * true otherwise + */ +bool board_ti_is(char *name_tag); + +/** + * board_ti_rev_is() - Compare board revision for TI EVMs + * @rev_tag: Revision tag to check in eeprom + * @cmp_len: How many chars to compare? + * + * NOTE: revision information is often messed up (hence the str len match) :( + * + * Return: false if board information does not match OR eeprom was'nt read. + * true otherwise + */ +bool board_ti_rev_is(char *rev_tag, int cmp_len); + +/** + * board_ti_get_rev() - Get board revision for TI EVMs + * + * Return: NULL if eeprom was'nt read. + * Board revision otherwise + */ +char *board_ti_get_rev(void); + +/** + * board_ti_get_config() - Get board config for TI EVMs + * + * Return: NULL if eeprom was'nt read. + * Board config otherwise + */ +char *board_ti_get_config(void); + +/** + * board_ti_get_name() - Get board name for TI EVMs + * + * Return: NULL if eeprom was'nt read. + * Board name otherwise + */ +char *board_ti_get_name(void); + +/** + * board_ti_get_eth_mac_addr() - Get Ethernet MAC address from EEPROM MAC list + * @index: 0 based index within the list of MAC addresses + * @mac_addr: MAC address contained at the index is returned here + * + * Does not sanity check the mac_addr. Whatever is stored in EEPROM is returned. + */ +void board_ti_get_eth_mac_addr(int index, u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]); + +/** + * board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs + * + * Return: NULL if eeprom was'nt read or emif1_size is not available. + */ +u64 board_ti_get_emif1_size(void); + +/** + * board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs + * + * Return: NULL if eeprom was'nt read or emif2_size is not available. + */ +u64 board_ti_get_emif2_size(void); + +/** + * set_board_info_env() - Setup commonly used board information environment vars + * @name: Name of the board + * + * If name is NULL, default_name is used. + */ +void set_board_info_env(char *name); + +#endif /* __BOARD_DETECT_H */ diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig index 80341d9932..b642113b83 100644 --- a/board/ti/dra7xx/Kconfig +++ b/board/ti/dra7xx/Kconfig @@ -17,4 +17,7 @@ config CONS_INDEX The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it. Depending on your specific board you may want something other than UART1 here. + +source "board/ti/common/Kconfig" + endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index eebec881da..4e45abfff7 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -13,11 +13,13 @@ #include <common.h> #include <palmas.h> #include <sata.h> +#include <linux/string.h> #include <asm/gpio.h> #include <usb.h> #include <linux/usb/gadget.h> #include <asm/arch/gpio.h> #include <asm/arch/dra7xx_iodelay.h> +#include <asm/emif.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -27,6 +29,13 @@ #include <ti-usb-phy-uboot.h> #include "mux_data.h" +#include "../common/board_detect.h" + +#define board_is_dra74x_evm() board_ti_is("5777xCPU") +#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ + (strncmp("H", board_ti_get_rev(), 1) <= 0) +#define board_ti_get_emif_size() board_ti_get_emif1_size() + \ + board_ti_get_emif2_size() #ifdef CONFIG_DRIVER_TI_CPSW #include <cpsw.h> @@ -37,10 +46,215 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO 7_11 */ #define GPIO_DDR_VTT_EN 203 +#define SYSINFO_BOARD_NAME_MAX_LEN 37 + const struct omap_sysinfo sysinfo = { - "Board: DRA7xx\n" + "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" +}; + +static const struct emif_regs emif1_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const struct emif_regs emif2_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113781C, + .sdram_tim2 = 0x30717FE3, + .sdram_tim3 = 0x409F86A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, + .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x30BF7FDA, + .sdram_tim3 = 0x427F8BA8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x427F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + switch (emif_nr) { + case 1: + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif1_ddr3_532_mhz_1cs_2G; + else + *regs = &emif1_ddr3_532_mhz_1cs; + break; + case 2: + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *regs = &emif2_ddr3_532_mhz_1cs_2G; + else + *regs = &emif2_ddr3_532_mhz_1cs; + break; + } + break; + case DRA722_ES1_0: + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + break; + default: + *regs = &emif1_ddr3_532_mhz_1cs; + } +} + +static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x80640300, + .dmm_lisa_map_2 = 0xC0500220, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 }; +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + if (ram_size > CONFIG_MAX_MEM_MAPPED) + *dmm_lisa_regs = &lisa_map_dra7_2GB; + else + *dmm_lisa_regs = &lisa_map_dra7_1536MB; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; + } +} + /** * @brief board_init * @@ -54,20 +268,77 @@ int board_init(void) return 0; } +void dram_init_banksize(void) +{ + u64 ram_size; + + ram_size = board_ti_get_emif_size(); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_effective_memsize(); + if (ram_size > CONFIG_MAX_MEM_MAPPED) { + gd->bd->bi_dram[1].start = 0x200000000; + gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; + } +} + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (omap_revision() == DRA722_ES1_0) - setenv("board_name", "dra72x"); + char *name = "unknown"; + + if (is_dra72x()) + name = "dra72x"; else - setenv("board_name", "dra7xx"); + name = "dra7xx"; + + set_board_info_env(name); omap_die_id_serial(); #endif return 0; } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_SPL_BUILD +void do_board_detect(void) +{ + int rc; + + rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); +} + +#else + +void do_board_detect(void) +{ + char *bname = NULL; + int rc; + + rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (rc) + printf("ti_i2c_eeprom_init failed %d\n", rc); + + if (board_is_dra74x_evm()) { + bname = "DRA74x EVM"; + /* If EEPROM is not populated */ + } else { + if (is_dra72x()) + bname = "DRA72x EVM"; + else + bname = "DRA74x EVM"; + } + + if (bname) + snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, + "Board: %s REV %s\n", bname, board_ti_get_rev()); +} +#endif /* CONFIG_SPL_BUILD */ + +void set_muxconf_regs(void) { do_set_mux32((*ctrl)->control_padconf_core_base, early_padconf, ARRAY_SIZE(early_padconf)); @@ -82,10 +353,10 @@ void recalibrate_iodelay(void) switch (omap_revision()) { case DRA722_ES1_0: - pads = core_padconf_array_essential; - npads = ARRAY_SIZE(core_padconf_array_essential); - iodelay = iodelay_cfg_array; - niodelays = ARRAY_SIZE(iodelay_cfg_array); + pads = dra72x_core_padconf_array; + npads = ARRAY_SIZE(dra72x_core_padconf_array); + iodelay = dra72_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array); break; case DRA752_ES1_0: case DRA752_ES1_1: diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index bec3b553bc..6db11a2bbb 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -12,134 +12,180 @@ #include <asm/arch/mux_dra7xx.h> -const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ -#if defined(CONFIG_NOR) - /* NOR only pin-mux */ - {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ - {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ - {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ - {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ - {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ - {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ - {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ - {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ - {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ - {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ - {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ - {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ - {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ - {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ - {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ - {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ - {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ - {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ - {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ - {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ - {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ - {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ - {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ - {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ - {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ - {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ - {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ -#else - /* eMMC pinmux */ - {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ - {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ - {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ - {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ - {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ - {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ - {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ - {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ - {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ - {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ -#endif -#if (CONFIG_CONS_INDEX == 1) - {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ - {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ - {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ - {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ -#elif (CONFIG_CONS_INDEX == 3) - {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ - {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ -#endif - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ - {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ - {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) }, - {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) }, - {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) }, - {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) }, - {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) }, - {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) }, - {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) }, - {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) }, - {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)}, - {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)}, - {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)}, - {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)}, - {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)}, - {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)}, -#if defined(CONFIG_NAND) || defined(CONFIG_NOR) - /* NAND / NOR pin-mux */ - {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ - {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ - {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ - {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ - {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ - {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ - {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ - {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ - {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ - {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ - {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ - {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ - {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ - {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ - {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ - {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ - {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ - {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ - {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ - {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ - {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ - {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ - /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ -#else - /* QSPI pin-mux */ - {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ - {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ - {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ - {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ - {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ - {GPMC_A18, (M1)}, /* QSPI1_SCLK */ - {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ - {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ - {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ - {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ -#endif /* CONFIG_NAND || CONFIG_NOR */ - {USB2_DRVVBUS, (M0 | IEN | FSC) }, - {SPI1_CS1, (PEN | IDIS | M14) }, +const struct pad_conf_entry dra72x_core_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */ + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */ + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */ + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */ + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */ + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */ + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ + {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ + {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */ + {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */ + {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */ + {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */ + {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */ + {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */ + {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */ + {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */ + {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */ + {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */ + {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */ + {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */ + {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */ + {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */ + {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */ + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ + {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */ + {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */ + {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ + {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */ + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ + {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ + {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ }; const struct pad_conf_entry early_padconf[] = { @@ -155,7 +201,7 @@ const struct pad_conf_entry early_padconf[] = { }; #ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry iodelay_cfg_array[] = { +const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = { {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */ {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */ @@ -181,6 +227,14 @@ const struct iodelay_cfg_entry iodelay_cfg_array[] = { {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */ {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */ {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */ + {0x144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */ + {0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */ + {0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */ + {0x170, 0, 0 }, /* CFG_GPMC_A16_OUT */ + {0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */ + {0x188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */ }; #endif @@ -345,7 +399,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index d60496ef27..7ef2d2bff5 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -1,17 +1,17 @@ # # KS2-EVM: board Makefile -# (C) Copyright 2012-2014 +# (C) Copyright 2012-2015 # Texas Instruments Incorporated, <www.ti.com> # SPDX-License-Identifier: GPL-2.0+ # obj-y += board.o -obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o +obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o obj-$(CONFIG_K2G_EVM) += board_k2g.o obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 7d1709c880..ca668a7c69 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -146,9 +146,7 @@ int ft_board_setup(void *blob, bd_t *bd) ddr3a_size = 0; if (lpae) { - env = getenv("ddr3a_size"); - if (env) - ddr3a_size = simple_strtol(env, NULL, 10); + ddr3a_size = ddr3_get_size(); if ((ddr3a_size != 8) && (ddr3a_size != 4)) ddr3a_size = 0; } diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index f58f62358d..cbb3077bc3 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -61,7 +61,7 @@ struct pll_init_data *get_pll_init_data(int pll) switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case PASS_PLL: diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index cdeb056a76..b62c412250 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -23,22 +23,64 @@ unsigned int external_clk[ext_clk_count] = { [uart_clk] = SYS_CLK, }; -static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; -static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; +static int arm_speeds[DEVSPEED_NUMSPDS] = { + SPD400, + SPD600, + SPD800, + SPD900, + SPD1000, + SPD900, + SPD800, + SPD600, + SPD400, + SPD200, +}; + +static int dev_speeds[DEVSPEED_NUMSPDS] = { + SPD600, + SPD800, + SPD900, + SPD1000, + SPD900, + SPD800, + SPD600, + SPD400, +}; + +static struct pll_init_data main_pll_config[NUM_SPDS] = { + [SPD400] = {MAIN_PLL, 100, 3, 2}, + [SPD600] = {MAIN_PLL, 300, 6, 2}, + [SPD800] = {MAIN_PLL, 200, 3, 2}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +}; + +static struct pll_init_data tetris_pll_config[NUM_SPDS] = { + [SPD200] = {TETRIS_PLL, 250, 3, 10}, + [SPD400] = {TETRIS_PLL, 100, 1, 6}, + [SPD600] = {TETRIS_PLL, 100, 1, 4}, + [SPD800] = {TETRIS_PLL, 400, 3, 4}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +}; + static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; struct pll_init_data *get_pll_init_data(int pll) { + int speed; struct pll_init_data *data = NULL; switch (pll) { case MAIN_PLL: - data = &main_pll_config; + speed = get_max_dev_speed(dev_speeds); + data = &main_pll_config[speed]; break; case TETRIS_PLL: - data = &tetris_pll_config; + speed = get_max_arm_speed(arm_speeds); + data = &tetris_pll_config[speed]; break; case NSS_PLL: data = &nss_pll_config; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 0bd6b86e25..e217beaed5 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -51,11 +51,11 @@ struct pll_init_data *get_pll_init_data(int pll) switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case TETRIS_PLL: - speed = get_max_arm_speed(); + speed = get_max_arm_speed(speeds); data = &tetris_pll_config[speed]; break; case PASS_PLL: diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index d750ad3c0b..2a2e0057e2 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -50,11 +50,11 @@ struct pll_init_data *get_pll_init_data(int pll) switch (pll) { case MAIN_PLL: - speed = get_max_dev_speed(); + speed = get_max_dev_speed(speeds); data = &core_pll_config[speed]; break; case TETRIS_PLL: - speed = get_max_arm_speed(); + speed = get_max_arm_speed(speeds); data = &tetris_pll_config[speed]; break; case PASS_PLL: diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index ab44676793..b6b59a4dd5 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -9,129 +9,8 @@ #include <common.h> -#include <i2c.h> #include <asm/arch/ddr3.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* DDR3 PHY configuration data with 1600M rate, 8GB size */ -struct ddr3_phy_config ddr3phy_1600_8g = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ -struct ddr3_emif_config ddr3_1600_8g = { - .sdcfg = 0x6200CE6Aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -#ifdef CONFIG_K2HK_EVM -/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ -struct ddr3_phy_config ddr3phy_1333_2g = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ -struct ddr3_emif_config ddr3_1333_2g = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001457ul, -}; -#endif - -#ifdef CONFIG_K2E_EVM -/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ -struct ddr3_phy_config ddr3phy_1600_4g = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x08861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x9D9CBB66ul, - .dtpr1 = 0x12840300ul, - .dtpr2 = 0x5002D200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ -struct ddr3_emif_config ddr3_1600_4g = { - .sdcfg = 0x6200CE62ul, - .sdtim1 = 0x166C9855ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x421DFF53ul, - .sdtim4 = 0x543F07FFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; -#endif +#include "ddr3_cfg.h" struct ddr3_phy_config ddr3phy_1600_2g = { .pllcr = 0x0001C000ul, @@ -168,39 +47,3 @@ struct ddr3_emif_config ddr3_1600_2g = { .zqcfg = 0x70073200ul, .sdrfc = 0x00001869ul, }; - -int ddr3_get_dimm_params(char *dimm_name) -{ - int ret; - int old_bus; - u8 spd_params[256]; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index 5bd786cff8..f95eddec33 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -10,18 +10,11 @@ #ifndef __DDR3_CFG_H #define __DDR3_CFG_H -extern struct ddr3_phy_config ddr3phy_1600_8g; -extern struct ddr3_emif_config ddr3_1600_8g; - -extern struct ddr3_phy_config ddr3phy_1333_2g; -extern struct ddr3_emif_config ddr3_1333_2g; - -extern struct ddr3_phy_config ddr3phy_1600_4g; -extern struct ddr3_emif_config ddr3_1600_4g; +#include <asm/arch/ddr3.h> extern struct ddr3_phy_config ddr3phy_1600_2g; extern struct ddr3_emif_config ddr3_1600_2g; -int ddr3_get_dimm_params(char *dimm_name); +int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 35ffb42056..e82aa6699b 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -1,7 +1,7 @@ /* * Keystone2: DDR3 initialization * - * (C) Copyright 2014 + * (C) Copyright 2014-2015 * Texas Instruments Incorporated, <www.ti.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -12,42 +12,37 @@ #include <asm/arch/ddr3.h> static struct pll_init_data ddr3_400 = DDR3_PLL_400; +static struct pll_init_data ddr3_333 = DDR3_PLL_333; u32 ddr3_init(void) { - u32 ddr3_size; - char dimm_name[32]; + struct ddr3_spd_cb spd_cb; - if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) - init_pll(&ddr3_400); + if (ddr3_get_dimm_params_from_spd(&spd_cb)) { + printf("Sorry, I don't know how to configure DDR3A.\n" + "Bye :(\n"); + for (;;) + ; + } - ddr3_get_dimm_params(dimm_name); + printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); - printf("Detected SO-DIMM [%s]\n", dimm_name); + printf("DDR3 speed %d\n", spd_cb.ddrspdclock); + if (spd_cb.ddrspdclock == 1600) + init_pll(&ddr3_400); + else + init_pll(&ddr3_333); /* Reset DDR3 PHY after PLL enabled */ ddr3_reset_ddrphy(); - if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - /* 8G SO-DIMM */ - ddr3_size = 8; - printf("DRAM: 8 GiB\n"); - ddr3phy_1600_8g.zq0cr1 |= 0x10000; - ddr3phy_1600_8g.zq1cr1 |= 0x10000; - ddr3phy_1600_8g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); - } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { - /* 4G SO-DIMM */ - ddr3_size = 4; - printf("DRAM: 4 GiB\n"); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); - } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; - } + spd_cb.phy_cfg.zq0cr1 |= 0x10000; + spd_cb.phy_cfg.zq1cr1 |= 0x10000; + spd_cb.phy_cfg.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + + printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte); - return ddr3_size; + return (u32)spd_cb.ddr_size_gbyte; } diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index b36eb27bfa..f8484221fa 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -17,77 +17,48 @@ struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); u32 ddr3_init(void) { - char dimm_name[32]; u32 ddr3_size; + struct ddr3_spd_cb spd_cb; - ddr3_get_dimm_params(dimm_name); + if (ddr3_get_dimm_params_from_spd(&spd_cb)) { + printf("Sorry, I don't know how to configure DDR3A.\n" + "Bye :(\n"); + for (;;) + ; + } - printf("Detected SO-DIMM [%s]\n", dimm_name); + printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); - if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - init_pll(&ddr3a_400); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3phy_1600_8g.zq0cr1 |= 0x10000; - ddr3phy_1600_8g.zq1cr1 |= 0x10000; - ddr3phy_1600_8g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_8g); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_8g); - } + if ((cpu_revision() > 1) || + (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) { + printf("DDR3 speed %d\n", spd_cb.ddrspdclock); + if (spd_cb.ddrspdclock == 1600) + init_pll(&ddr3a_400); + else + init_pll(&ddr3a_333); + } - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_8g); - printf("DRAM: Capacity 8 GiB (includes reported below)\n"); - ddr3_size = 8; - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); - ddr3_1600_8g.sdcfg |= 0x1000; - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_8g); - printf("DRAM: Capacity 4 GiB (includes reported below)\n"); - ddr3_size = 4; - } - } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { - init_pll(&ddr3a_333); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3phy_1333_2g.zq0cr1 |= 0x10000; - ddr3phy_1333_2g.zq1cr1 |= 0x10000; - ddr3phy_1333_2g.zq2cr1 |= 0x10000; - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_2g); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_2g); - } - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_2g); - ddr3_size = 2; - printf("DRAM: 2 GiB"); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); - ddr3_1333_2g.sdcfg |= 0x1000; - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_2g); - ddr3_size = 1; - printf("DRAM: 1 GiB"); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + spd_cb.phy_cfg.zq0cr1 |= 0x10000; + spd_cb.phy_cfg.zq1cr1 |= 0x10000; + spd_cb.phy_cfg.zq2cr1 |= 0x10000; } + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + + ddr3_size = spd_cb.ddr_size_gbyte; } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); + spd_cb.emif_cfg.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); + ddr3_size = spd_cb.ddr_size_gbyte / 2; } + printf("DRAM: %d GiB (includes reported below)\n", ddr3_size); /* Apply the workaround for PG 1.0 and 1.1 Silicons */ if (cpu_revision() <= 1) diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 853f1969ef..50da4109bb 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -198,7 +198,7 @@ int misc_init_r(void) return 0; } -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_essential, diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index eb9ce630dc..13b5dafe82 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/gpio.h> +#include <twl6030.h> #include "panda_mux_data.h" @@ -267,7 +268,7 @@ int misc_init_r(void) return 0; } -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_essential, @@ -291,6 +292,11 @@ int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } + +void board_mmc_power_init(void) +{ + twl6030_power_mmc_init(0); +} #endif #ifdef CONFIG_USB_EHCI diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 1e9ef9e38b..6037cdd6c1 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -53,7 +53,7 @@ int misc_init_r(void) return 0; } -void set_muxconf_regs_essential(void) +void set_muxconf_regs(void) { do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array_essential, @@ -80,6 +80,12 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_power_init(void) +{ + twl6030_power_mmc_init(0); + twl6030_power_mmc_init(1); +} #endif /* diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 1a447c77df..965252f18d 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -46,9 +46,9 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { }; static const struct ns16550_platdata devkit8000_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(devkit8000_uart) = { diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index ac44e32341..27056e195a 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -10,6 +10,7 @@ #include <common.h> #include <errno.h> +#include <libfdt.h> #include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile index ba31c8e4f4..e26c6737ee 100644 --- a/board/work-microwave/work_92105/Makefile +++ b/board/work-microwave/work_92105/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := work_92105.o work_92105_display.o - -obj-$(CONFIG_SPL_BUILD) += work_92105_spl.o +ifdef CONFIG_SPL_BUILD +obj-y += work_92105_spl.o +else +obj-y += work_92105.o work_92105_display.o +endif |
