diff options
Diffstat (limited to 'board')
60 files changed, 1928 insertions, 1812 deletions
diff --git a/board/adder/adder.c b/board/adder/adder.c index aa7815848c..817c8649aa 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -26,6 +26,9 @@ #include <common.h> #include <mpc8xx.h> +#if defined(CONFIG_OF_LIBFDT) + #include <libfdt.h> +#endif /* * SDRAM is single Samsung K4S643232F-T70 chip (8MB) @@ -111,3 +114,11 @@ int checkboard( void ) return 0; } + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +} +#endif diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile new file mode 100644 index 0000000000..7a2eaa5163 --- /dev/null +++ b/board/amcc/canyonlands/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2008 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +COBJS += bootstrap.o +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c new file mode 100644 index 0000000000..37fa1c926c --- /dev/null +++ b/board/amcc/canyonlands/bootstrap.c @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/io.h> + +/* + * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The + * values are independent of the rest of the clock settings. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +#define I2C_EEPROM_ADDR 0x52 + +static char *config_labels[] = { + "CPU: 600 PLB: 200 OPB: 100 EBC: 100", + "CPU: 800 PLB: 200 OPB: 100 EBC: 100", + NULL +}; + +static u8 boot_configs[][17] = { + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } +}; + +/* + * Bytes 5,6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0x90, 0x01, 0xa0, 0x68, 0x58 +}; + +static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 *buf, b_nand; + int x, y, nbytes, selcfg; + extern char console_buffer[]; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); + return 1; + } + + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + b_nand = 1; + else + b_nand = 0; + + printf("Available configurations: \n\n"); + + if (b_nand) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } + } + } else { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } + } + } + + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (b_nand) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (b_nand) { + buf[5] = nand_boot[0]; + buf[6] = nand_boot[1]; + buf[8] = nand_boot[2]; + buf[9] = nand_boot[3]; + buf[11] = nand_boot[4]; + } + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + + printf("Done\n"); + printf("Please power-cycle the board for the changes to take effect\n"); + + return 0; +} + +U_BOOT_CMD( + bootstrap, 2, 0, do_bootstrap, + "bootstrap - program the I2C bootstrap EEPROM\n", + "<nand|nor> - strap to boot from NAND or NOR flash\n" + ); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c new file mode 100644 index 0000000000..36779f576f --- /dev/null +++ b/board/amcc/canyonlands/canyonlands.c @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc440.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/4xx_pcie.h> +#include <asm/gpio.h> + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + u32 sdr0_cust0; + + /*------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + *------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(uic3er, 0x00000000); /* disable all */ + mtdcr(uic3cr, 0x00000000); /* all non-critical */ + mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic3sr, 0xffffffff); /* clear all */ + + /* SDR Setting - enable NDFC */ + mfsdr(SDR0_CUST0, sdr0_cust0); + sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + SDR0_CUST0_NDFC_BAC_ENCODE(3) | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, sdr0_cust0); + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 4 pins + */ + mtsdr(SDR0_PFC1, 0x00040000); + + /* Enable PCI host functionality in SDR0_PCI0 */ + mtsdr(SDR0_PCI0, 0xe0000000); + + /* Enable ethernet and take out of reset */ + out_8((void *)CFG_BCSR_BASE + 6, 0); + + /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ + out_8((void *)CFG_BCSR_BASE + 5, 0); + + /* Enable USB host & USB-OTG */ + out_8((void *)CFG_BCSR_BASE + 7, 0); + + mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + u32 pvr = get_pvr(); + + if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) + printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); + else + printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +u32 ddr_wrdtr(u32 default_val) { + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); +} + +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_90_DEG_ADV); +} + +#if defined(CONFIG_NAND_U_BOOT) +/* + * NAND booting U-Boot version uses a fixed initialization, since the whole + * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot + * code. + */ +long int initdram(int board_type) +{ + return CFG_MBYTES_SDRAM << 20; +} +#endif + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + /*-------------------------------------------------------------------+ + * Disable everything + *-------------------------------------------------------------------*/ + out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ + + /*-------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 + * strapping options to not support sizes such as 128/256 MB. + *-------------------------------------------------------------------*/ + out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out_le32((void *)PCIX0_PIM0LAH, 0); + out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIX0_BAR0, 0); + + /*-------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *-------------------------------------------------------------------*/ + out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + + out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +#if defined(CONFIG_PCI) +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + */ +int is_pci_host(struct pci_controller *hose) +{ + /* Board is always configured as host. */ + return (1); +} + +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + char *env; + unsigned int delay; + + /* + * assume we're called after the PCIX hose is initialized, which takes + * bus ID 0 and therefore start numbering PCIe's from 1. + */ + bus = busno; + for (i = 0; i <= 1; i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif /* CONFIG_PCI */ + +int board_early_init_r (void) +{ + /* + * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + + /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#else + mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000); +#endif + + /* Remove TLB entry of boot EBC mapping */ + remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20); + + /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ + program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE, + TLB_WORD2_I_ENABLE); + + /* + * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address + * 0xfc00.0000 is possible + */ + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + u32 eth_cfg; + + /* + * Set EMAC mode/configuration (GMII, SGMII, RGMII...). + * This is board specific, so let's do it here. + */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + /* disable SGMII mode */ + eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | + SDR0_ETH_CFG_SGMII1_ENABLE | + SDR0_ETH_CFG_SGMII0_ENABLE); + /* Set the for 2 RGMII mode */ + /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ + eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; + eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + mtsdr(SDR0_ETH_CFG, eth_cfg); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk new file mode 100644 index 0000000000..1e4bbc47e6 --- /dev/null +++ b/board/amcc/canyonlands/config.mk @@ -0,0 +1,49 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 460EX/460GT Evaluation Board (Canyonlands) board +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +endif + +ifeq ($(CONFIG_PCIBOOT_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S new file mode 100644 index 0000000000..bd4cab56d8 --- /dev/null +++ b/board/amcc/canyonlands/init.S @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ +#else + tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) +#endif + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) +#endif + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + /* PCIe UTL register */ + tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry for NAND */ + tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB-entry for CPLD */ + tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry for OCM */ + tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* AHB: Internal USB Peripherals (USB, SATA) */ + tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbtab_end + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * For NAND booting the first TLB has to be reconfigured to full size + * and with caching disabled after running from RAM! + */ +#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) + + .globl reconfig_tlb0 +reconfig_tlb0: + sync + isync + addi r4,r0,0x0000 /* TLB entry #0 */ + lis r5,TLB00@h + ori r5,r5,TLB00@l + tlbwe r5,r4,0x0000 /* Save it out */ + lis r5,TLB01@h + ori r5,r5,TLB01@l + tlbwe r5,r4,0x0001 /* Save it out */ + lis r5,TLB02@h + ori r5,r5,TLB02@l + tlbwe r5,r4,0x0002 /* Save it out */ + sync + isync + blr +#endif diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds new file mode 100644 index 0000000000..12a5dcf85c --- /dev/null +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds new file mode 100644 index 0000000000..7496f485ea --- /dev/null +++ b/board/amcc/canyonlands/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2008 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/canyonlands/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S index 43387445b1..053fe19c07 100644 --- a/board/amcc/kilauea/init.S +++ b/board/amcc/kilauea/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on code provided from UDTech and AMCC @@ -64,7 +64,7 @@ ext_bus_cntlr_init: /* SET SDRAM_MB3CF - Not enabled */ mtsdram_as(SDRAM_MB3CF, 0x00000000); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR, 0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 57c1774e02..5e9a5e08d3 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on code provided from Senao and AMCC @@ -57,7 +57,7 @@ ext_bus_cntlr_init: /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); - /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + /* SDRAM_CLKTR: Adv Addr clock by 180 deg */ mtsdram_as(SDRAM_CLKTR,0x80000000); /* Refresh Time register (0x30) Refresh every 7.8125uS */ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 98ed6f81d2..738f69c781 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { -#if (BFIN_CPU == ADSP_BF531) - printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF532) - printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF533 EZ-Kit Lite board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index af035976ff..c4dde92c1a 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -43,13 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { -#if (BFIN_CPU == ADSP_BF531) - printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF532) - printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF533 Stamp board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index e4888441a9..5d22393371 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o +COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index d279817bba..6ca8e21f3a 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -31,7 +31,6 @@ #include <asm/blackfin.h> #include <asm/io.h> #include <net.h> -#include "ether_bf537.h" #include <asm/mach-common/bits/bootrom.h> /** @@ -54,60 +53,8 @@ DECLARE_GLOBAL_DATA_PTR; #define POST_WORD_ADDR 0xFF903FFC -/* - * the bootldr command loads an address, checks to see if there - * is a Boot stream that the on-chip BOOTROM can understand, - * and loads it via the BOOTROM Callback. It is possible - * to also add booting from SPI, or TWI, but this function does - * not currently support that. - */ -int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr, entry; - ulong *data; - - /* Get the address */ - if (argc < 2) { - addr = load_addr; - } else { - addr = simple_strtoul(argv[1], NULL, 16); - } - - /* Check if it is a LDR file */ - data = (ulong *) addr; - if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) { - /* We want to boot from FLASH or SDRAM */ - entry = _BOOTROM_BOOT_DXE_FLASH; - printf("## Booting ldr image at 0x%08lx ...\n", addr); - if (icache_status()) - icache_disable(); - if (dcache_status()) - dcache_disable(); - - __asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n": - :[a] "d"(addr),[b] "a"(entry) - :"R7", "P0"); - - } else { - printf("## No ldr image at address 0x%08lx\n", addr); - } - - return 0; -} - -U_BOOT_CMD(bootldr, 2, 0, do_bootldr, - "bootldr - boot ldr image from memory\n", - "[addr]\n - boot ldr image stored in memory\n"); - int checkboard(void) { -#if (BFIN_CPU == ADSP_BF534) - printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28); -#elif (BFIN_CPU == ADSP_BF536) - printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28); -#else - printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28); -#endif printf("Board: ADI BF537 stamp board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; @@ -187,9 +134,6 @@ int misc_init_r(void) pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]); setenv("ethaddr", nid); } - if (getenv("ethaddr")) { - SetupMacAddr(SrcAddr); - } #endif #endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */ diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c deleted file mode 100644 index 6c514c6609..0000000000 --- a/board/bf537-stamp/ether_bf537.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * ADI Blackfin 537 MAC Ethernet - * - * Copyright (c) 2005 Analog Device, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include <net.h> -#include <command.h> -#include <malloc.h> -#include "ether_bf537.h" - -#include <asm/mach-common/bits/dma.h> -#include <asm/mach-common/bits/emac.h> -#include <asm/mach-common/bits/pll.h> - -#ifdef CONFIG_POST -#include <post.h> -#endif - -#undef DEBUG_ETHERNET - -#ifdef DEBUG_ETHERNET -#define DEBUGF(fmt,args...) printf(fmt,##args) -#else -#define DEBUGF(fmt,args...) -#endif - -#if defined(CONFIG_CMD_NET) - -#define RXBUF_BASE_ADDR 0xFF900000 -#define TXBUF_BASE_ADDR 0xFF800000 -#define TX_BUF_CNT 1 - -#define TOUT_LOOP 1000000 - -ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; -ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; -static u16 txIdx; /* index of the current RX buffer */ -static u16 rxIdx; /* index of the current TX buffer */ - -u8 SrcAddr[6]; -u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */ - -/* DMAx_CONFIG values at DMA Restart */ -const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 }; - -#if 0 - rxdmacfg.b_DMA_EN = 1; /* enabled */ - rxdmacfg.b_WNR = 1; /* write to memory */ - rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */ - rxdmacfg.b_DMA2D = 0; /* N/A */ - rxdmacfg.b_RESTART= 0; /* N/A */ - rxdmacfg.b_DI_SEL = 0; /* N/A */ - rxdmacfg.b_DI_EN = 0; /* no interrupt */ - rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */ - rxdmacfg.b_FLOW = 7; /* large desc flow */ -#endif - -const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 }; - -#if 0 - txdmacfg.b_DMA_EN = 1; /* enabled */ - txdmacfg.b_WNR = 0; /* read from memory */ - txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */ - txdmacfg.b_DMA2D = 0; /* N/A */ - txdmacfg.b_RESTART= 0; /* N/A */ - txdmacfg.b_DI_SEL = 0; /* N/A */ - txdmacfg.b_DI_EN = 0; /* no interrupt */ - txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */ - txdmacfg.b_FLOW = 7; /* large desc flow */ -#endif - -ADI_ETHER_BUFFER *SetupRxBuffer(int no); -ADI_ETHER_BUFFER *SetupTxBuffer(int no); - -static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd); -static void bfin_EMAC_halt(struct eth_device *dev); -static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, - int length); -static int bfin_EMAC_recv(struct eth_device *dev); - -int bfin_EMAC_initialize(bd_t * bis) -{ - struct eth_device *dev; - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (dev == NULL) - hang(); - - memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "BF537 ETHERNET"); - - dev->iobase = 0; - dev->priv = 0; - dev->init = bfin_EMAC_init; - dev->halt = bfin_EMAC_halt; - dev->send = bfin_EMAC_send; - dev->recv = bfin_EMAC_recv; - - eth_register(dev); - - return 1; -} - -static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, - int length) -{ - int i; - int result = 0; - unsigned int *buf; - buf = (unsigned int *)packet; - - if (length <= 0) { - printf("Ethernet: bad packet size: %d\n", length); - goto out; - } - - if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) { - printf("Ethernet: tx DMA error\n"); - goto out; - } - - for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) { - if (i > TOUT_LOOP) { - puts("Ethernet: tx time out\n"); - goto out; - } - } - txbuf[txIdx]->FrmData->NoBytes = length; - memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length); - txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData; - *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0]; - *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg); - *pEMAC_OPMODE |= TE; - - for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) { - if (i > TOUT_LOOP) { - puts("Ethernet: tx error\n"); - goto out; - } - } - result = txbuf[txIdx]->StatusWord; - txbuf[txIdx]->StatusWord = 0; - if ((txIdx + 1) >= TX_BUF_CNT) - txIdx = 0; - else - txIdx++; - out: - DEBUGF("BFIN EMAC send: length = %d\n", length); - return result; -} - -static int bfin_EMAC_recv(struct eth_device *dev) -{ - int length = 0; - - for (;;) { - if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) { - length = -1; - break; - } - if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) { - printf("Ethernet: rx dma overrun\n"); - break; - } - if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) { - printf("Ethernet: rx error\n"); - break; - } - length = rxbuf[rxIdx]->StatusWord & 0x000007FF; - if (length <= 4) { - printf("Ethernet: bad frame\n"); - break; - } - NetRxPackets[rxIdx] = - (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest); - NetReceive(NetRxPackets[rxIdx], length - 4); - *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR; - rxbuf[rxIdx]->StatusWord = 0x00000000; - if ((rxIdx + 1) >= PKTBUFSRX) - rxIdx = 0; - else - rxIdx++; - } - - return length; -} - -/************************************************************** - * - * Ethernet Initialization Routine - * - *************************************************************/ - -static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd) -{ - u32 opmode; - int dat; - int i; - DEBUGF("Eth_init: ......\n"); - - txIdx = 0; - rxIdx = 0; - -/* Initialize System Register */ - if (SetupSystemRegs(&dat) < 0) - return -1; - -/* Initialize EMAC address */ - SetupMacAddr(SrcAddr); - -/* Initialize TX and RX buffer */ - for (i = 0; i < PKTBUFSRX; i++) { - rxbuf[i] = SetupRxBuffer(i); - if (i > 0) { - rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = - &(rxbuf[i]->Dma[0]); - if (i == (PKTBUFSRX - 1)) - rxbuf[i]->Dma[1].NEXT_DESC_PTR = - &(rxbuf[0]->Dma[0]); - } - } - for (i = 0; i < TX_BUF_CNT; i++) { - txbuf[i] = SetupTxBuffer(i); - if (i > 0) { - txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = - &(txbuf[i]->Dma[0]); - if (i == (TX_BUF_CNT - 1)) - txbuf[i]->Dma[1].NEXT_DESC_PTR = - &(txbuf[0]->Dma[0]); - } - } - - /* Set RX DMA */ - *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0]; - *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG); - - /* Wait MII done */ - PollMdcDone(); - - /* We enable only RX here */ - /* ASTP : Enable Automatic Pad Stripping - PR : Promiscuous Mode for test - PSF : Receive frames with total length less than 64 bytes. - FDMODE : Full Duplex Mode - LB : Internal Loopback for test - RE : Receiver Enable */ - if (dat == FDMODE) - opmode = ASTP | FDMODE | PSF; - else - opmode = ASTP | PSF; - opmode |= RE; -#ifdef CONFIG_BFIN_MAC_RMII - opmode |= TE | RMII; -#endif - /* Turn on the EMAC */ - *pEMAC_OPMODE = opmode; - return 0; -} - -static void bfin_EMAC_halt(struct eth_device *dev) -{ - DEBUGF("Eth_halt: ......\n"); - /* Turn off the EMAC */ - *pEMAC_OPMODE = 0x00000000; - /* Turn off the EMAC RX DMA */ - *pDMA1_CONFIG = 0x0000; - *pDMA2_CONFIG = 0x0000; - -} - -void SetupMacAddr(u8 * MACaddr) -{ - char *tmp, *end; - int i; - /* this depends on a little-endian machine */ - tmp = getenv("ethaddr"); - if (tmp) { - for (i = 0; i < 6; i++) { - MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - -#ifndef CONFIG_NETCONSOLE - printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", - MACaddr[0], MACaddr[1], - MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]); -#endif - *pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 | - MACaddr[2] << 16 | MACaddr[3] << 24; - *pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8; - } -} - -void PollMdcDone(void) -{ - /* poll the STABUSY bit */ - while (*pEMAC_STAADD & STABUSY) ; -} - -void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data) -{ - PollMdcDone(); - - *pEMAC_STADAT = Data; - - *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) | - STAOP | STAIE | STABUSY; -} - -/********************************************************************************* - * Read an off-chip register in a PHY through the MDC/MDIO port * - *********************************************************************************/ -u16 RdPHYReg(u16 PHYAddr, u16 RegAddr) -{ - u16 Data; - - PollMdcDone(); - - *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) | - STAIE | STABUSY; - - PollMdcDone(); - - Data = (u16) * pEMAC_STADAT; - - PHYregs[RegAddr] = Data; /* save shadow copy */ - - return Data; -} - -void SoftResetPHY(void) -{ - u16 phydat; - /* set the reset bit */ - WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET); - /* and clear it again */ - WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000); - do { - /* poll until reset is complete */ - phydat = RdPHYReg(PHYADDR, PHY_MODECTL); - } while ((phydat & PHY_RESET) != 0); -} - -int SetupSystemRegs(int *opmode) -{ - u16 sysctl, phydat; - int count = 0; - /* Enable PHY output */ - *pVR_CTL |= CLKBUFOE; - /* MDC = 2.5 MHz */ - sysctl = SET_MDCDIV(24); - /* Odd word alignment for Receive Frame DMA word */ - /* Configure checksum support and rcve frame word alignment */ - sysctl |= RXDWA | RXCKS; - *pEMAC_SYSCTL = sysctl; - /* auto negotiation on */ - /* full duplex */ - /* 100 Mbps */ - phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET; - WrPHYReg(PHYADDR, PHY_MODECTL, phydat); - do { - udelay(1000); - phydat = RdPHYReg(PHYADDR, PHY_MODESTAT); - if (count > 3000) { - printf - ("Link is down, please check your network connection\n"); - return -1; - } - count++; - } while (!(phydat & 0x0004)); - - phydat = RdPHYReg(PHYADDR, PHY_ANLPAR); - - if ((phydat & 0x0100) || (phydat & 0x0040)) - *opmode = FDMODE; - else - *opmode = 0; - - *pEMAC_MMC_CTL = RSTC | CROLL; - - /* Initialize the TX DMA channel registers */ - *pDMA2_X_COUNT = 0; - *pDMA2_X_MODIFY = 4; - *pDMA2_Y_COUNT = 0; - *pDMA2_Y_MODIFY = 0; - - /* Initialize the RX DMA channel registers */ - *pDMA1_X_COUNT = 0; - *pDMA1_X_MODIFY = 4; - *pDMA1_Y_COUNT = 0; - *pDMA1_Y_MODIFY = 0; - return 0; -} - -ADI_ETHER_BUFFER *SetupRxBuffer(int no) -{ - ADI_ETHER_FRAME_BUFFER *frmbuf; - ADI_ETHER_BUFFER *buf; - int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ - int total_size = nobytes_buffer + RECV_BUFSIZE; - - buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size); - frmbuf = - (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size + - nobytes_buffer); - - memset(buf, 0x00, nobytes_buffer); - buf->FrmData = frmbuf; - memset(frmbuf, 0xfe, RECV_BUFSIZE); - - /* set up first desc to point to receive frame buffer */ - buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); - buf->Dma[0].START_ADDR = (u32) buf->FrmData; - buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ - buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */ - buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ - buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ - buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ - - /* set up second desc to point to status word */ - buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]); - buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum; - buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ - buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ - buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ - buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ - buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */ - buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */ - - return buf; -} - -ADI_ETHER_BUFFER *SetupTxBuffer(int no) -{ - ADI_ETHER_FRAME_BUFFER *frmbuf; - ADI_ETHER_BUFFER *buf; - int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */ - int total_size = nobytes_buffer + RECV_BUFSIZE; - - buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size); - frmbuf = - (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size + - nobytes_buffer); - - memset(buf, 0x00, nobytes_buffer); - buf->FrmData = frmbuf; - memset(frmbuf, 0x00, RECV_BUFSIZE); - - /* set up first desc to point to receive frame buffer */ - buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]); - buf->Dma[0].START_ADDR = (u32) buf->FrmData; - buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */ - buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */ - buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ - buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */ - buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */ - - /* set up second desc to point to status word */ - buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]); - buf->Dma[1].START_ADDR = (u32) & buf->StatusWord; - buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */ - buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */ - buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */ - buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */ - buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */ - buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */ - - return buf; -} - -#if defined(CONFIG_POST) && defined(CFG_POST_ETHER) -int ether_post_test(int flags) -{ - uchar buf[64]; - int i, value = 0; - int length; - - printf("\n--------"); - bfin_EMAC_init(NULL, NULL); - /* construct the package */ - buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF); - buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8); - buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16); - buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24); - buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF); - buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8); - buf[12] = 0x08; /* Type: ARP */ - buf[13] = 0x06; - buf[14] = 0x00; /* Hardware type: Ethernet */ - buf[15] = 0x01; - buf[16] = 0x08; /* Protocal type: IP */ - buf[17] = 0x00; - buf[18] = 0x06; /* Hardware size */ - buf[19] = 0x04; /* Protocol size */ - buf[20] = 0x00; /* Opcode: request */ - buf[21] = 0x01; - - for (i = 0; i < 42; i++) - buf[i + 22] = i; - printf("--------Send 64 bytes......\n"); - bfin_EMAC_send(NULL, (volatile void *)buf, 64); - for (i = 0; i < 100; i++) { - udelay(10000); - if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) { - value = 1; - break; - } - } - if (value == 0) { - printf("--------EMAC can't receive any data\n"); - eth_halt(); - return -1; - } - length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4; - for (i = 0; i < length; i++) { - if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) { - printf("--------EMAC receive error data!\n"); - eth_halt(); - return -1; - } - } - printf("--------receive %d bytes, matched\n", length); - bfin_EMAC_halt(NULL); - return 0; -} -#endif -#endif diff --git a/board/bf537-stamp/ether_bf537.h b/board/bf537-stamp/ether_bf537.h deleted file mode 100644 index 22fc392ddc..0000000000 --- a/board/bf537-stamp/ether_bf537.h +++ /dev/null @@ -1,71 +0,0 @@ -#define PHYADDR 0x01 -#define NO_PHY_REGS 0x20 - -#define DEFAULT_PHY_PHYID1 0x0007 -#define DEFAULT_PHY_PHYID2 0xC0A3 -#define PHY_MODECTL 0x00 -#define PHY_MODESTAT 0x01 -#define PHY_PHYID1 0x02 -#define PHY_PHYID2 0x03 -#define PHY_ANAR 0x04 -#define PHY_ANLPAR 0x05 -#define PHY_ANER 0x06 - -#define PHY_RESET 0x8000 -#define PHY_ANEG_EN 0x1000 -#define PHY_DUPLEX 0x0100 -#define PHY_SPD_SET 0x2000 - -#define RECV_BUFSIZE (0x614) - -typedef volatile u32 reg32; -typedef volatile u16 reg16; - -typedef struct ADI_DMA_CONFIG_REG { - u16 b_DMA_EN:1; /* 0 Enabled */ - u16 b_WNR:1; /* 1 Direction */ - u16 b_WDSIZE:2; /* 2:3 Transfer word size */ - u16 b_DMA2D:1; /* 4 DMA mode */ - u16 b_RESTART:1; /* 5 Retain FIFO */ - u16 b_DI_SEL:1; /* 6 Data interrupt timing select */ - u16 b_DI_EN:1; /* 7 Data interrupt enabled */ - u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */ - u16 b_FLOW:3; /* 12:14Flow */ -} ADI_DMA_CONFIG_REG; - -typedef struct adi_ether_frame_buffer { - u16 NoBytes; /* the no. of following bytes */ - u8 Dest[6]; /* destination MAC address */ - u8 Srce[6]; /* source MAC address */ - u16 LTfield; /* length/type field */ - u8 Data[0]; /* payload bytes */ -} ADI_ETHER_FRAME_BUFFER; -/* 16 bytes/struct */ - -typedef struct dma_descriptor { - struct dma_descriptor *NEXT_DESC_PTR; - u32 START_ADDR; - ADI_DMA_CONFIG_REG CONFIG; -} DMA_DESCRIPTOR; -/* 10 bytes/struct in 12 bytes */ - -typedef struct adi_ether_buffer { - DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */ - ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */ - struct adi_ether_buffer *pNext; /* next buffer */ - struct adi_ether_buffer *pPrev; /* prev buffer */ - u16 IPHdrChksum; /* the IP header checksum */ - u16 IPPayloadChksum; /* the IP header and payload checksum */ - volatile u32 StatusWord; /* the frame status word */ -} ADI_ETHER_BUFFER; -/* 40 bytes/struct in 44 bytes */ - -void SetupMacAddr(u8 * MACaddr); - -void PollMdcDone(void); -void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data); -u16 RdPHYReg(u16 PHYAddr, u16 RegAddr); -void SoftResetPHY(void); -void DumpPHYRegs(void); - -int SetupSystemRegs(int *opmode); diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h deleted file mode 100644 index 1fa7a10bda..0000000000 --- a/board/bf537-stamp/flash-defines.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * U-boot - flash-defines.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __FLASHDEFINES_H__ -#define __FLASHDEFINES_H__ - -#include <common.h> - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) -#define TRUE 0x1 -#define FALSE 0x0 -#define BUFFER_SIZE 0x80000 -#define NO_COMMAND 0 -#define GET_CODES 1 -#define RESET 2 -#define WRITE 3 -#define FILL 4 -#define ERASE_ALL 5 -#define ERASE_SECT 6 -#define READ 7 -#define GET_SECTNUM 8 -#define FLASH_START_L 0x0000 -#define FLASH_START_H 0x2000 -#define FLASH_MAN_ST 2 -#define RESET_VAL 0xF0 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -int get_codes(void); -int poll_toggle_bit(long lOffset); -void reset_flash(void); -int erase_flash(void); -int erase_block_flash(int); -void unlock_flash(long lOffset); -int write_data(long lStart, long lCount, uchar * pnData); -int read_flash(long nOffset, int *pnValue); -int write_flash(long nOffset, int nValue); -void get_sector_number(long lOffset, int *pnSector); -int GetSectorProtectionStatus(flash_info_t * info, int nSector); -int GetOffset(int nBlock); -int AFP_NumSectors = 71; -long AFP_SectorSize2 = 0x10000; -int AFP_SectorSize1 = 0x2000; - -#define NUM_SECTORS 71 - -#define WRITESEQ1 0x0AAA -#define WRITESEQ2 0x0554 -#define WRITESEQ3 0x0AAA -#define WRITESEQ4 0x0AAA -#define WRITESEQ5 0x0554 -#define WRITESEQ6 0x0AAA -#define WRITEDATA1 0xaa -#define WRITEDATA2 0x55 -#define WRITEDATA3 0x80 -#define WRITEDATA4 0xaa -#define WRITEDATA5 0x55 -#define WRITEDATA6 0x10 -#define PriFlashABegin 0 -#define SecFlashABegin 8 -#define SecFlashBBegin 36 -#define PriFlashAOff 0x0 -#define PriFlashBOff 0x100000 -#define SecFlashAOff 0x10000 -#define SecFlashBOff 0x280000 -#define INVALIDLOCNSTART 0x20270000 -#define INVALIDLOCNEND 0x20280000 -#define BlockEraseVal 0x30 -#define UNLOCKDATA1 0xaa -#define UNLOCKDATA2 0x55 -#define UNLOCKDATA3 0xa0 -#define GETCODEDATA1 0xaa -#define GETCODEDATA2 0x55 -#define GETCODEDATA3 0x90 -#define SecFlashASec1Off 0x200000 -#define SecFlashASec2Off 0x204000 -#define SecFlashASec3Off 0x206000 -#define SecFlashASec4Off 0x208000 -#define SecFlashAEndOff 0x210000 -#define SecFlashBSec1Off 0x280000 -#define SecFlashBSec2Off 0x284000 -#define SecFlashBSec3Off 0x286000 -#define SecFlashBSec4Off 0x288000 -#define SecFlashBEndOff 0x290000 - -#define SECT32 32 -#define SECT33 33 -#define SECT34 34 -#define SECT35 35 -#define SECT36 36 -#define SECT37 37 -#define SECT38 38 -#define SECT39 39 - -#define FLASH_SUCCESS 0 -#define FLASH_FAIL -1 - -#endif diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c deleted file mode 100644 index 8252c42fd8..0000000000 --- a/board/bf537-stamp/flash.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * U-boot - flash.c Flash driver for PSD4256GV - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <malloc.h> -#include <config.h> -#include <asm/io.h> -#include "flash-defines.h" - -void flash_reset(void) -{ - reset_flash(); -} - -unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag) -{ - int id = 0, i = 0; - static int FlagDev = 1; - - id = get_codes(); - if (FlagDev) { - FlagDev = 0; - } - info->flash_id = id; - switch (bank_flag) { - case 0: - for (i = PriFlashABegin; i < SecFlashABegin; i++) - info->start[i] = (baseaddr + (i * AFP_SectorSize1)); - for (i = SecFlashABegin; i < NUM_SECTORS; i++) - info->start[i] = - (baseaddr + SecFlashAOff + - ((i - SecFlashABegin) * AFP_SectorSize2)); - info->size = 0x400000; - info->sector_count = NUM_SECTORS; - break; - case 1: - info->start[0] = baseaddr + SecFlashASec1Off; - info->start[1] = baseaddr + SecFlashASec2Off; - info->start[2] = baseaddr + SecFlashASec3Off; - info->start[3] = baseaddr + SecFlashASec4Off; - info->size = 0x10000; - info->sector_count = 4; - break; - case 2: - info->start[0] = baseaddr + SecFlashBSec1Off; - info->start[1] = baseaddr + SecFlashBSec2Off; - info->start[2] = baseaddr + SecFlashBSec3Off; - info->start[3] = baseaddr + SecFlashBSec4Off; - info->size = 0x10000; - info->sector_count = 4; - break; - } - return (info->size); -} - -unsigned long flash_init(void) -{ - unsigned long size_b; - int i; - - size_b = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0); - - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b, size_b >> 20); - } - - /* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, - (flash_info[0].start[2] - 1), &flash_info[0]); -#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) - (void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, - &flash_info[0]); -#endif - - return (size_b); -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id) { - case (STM_ID_29W320EB & 0xFFFF): - case (STM_ID_29W320DB & 0xFFFF): - printf("ST Microelectronics "); - break; - default: - printf("Unknown Vendor: (0x%08X) ", info->flash_id); - break; - } - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int cnt = 0, i; - int prot, sect; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - cnt = s_last - s_first + 1; - -#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) - printf("Erasing Flash locations, Please Wait\n"); - for (i = s_first; i <= s_last; i++) { - if (info->protect[i] == 0) { /* not protected */ - if (erase_block_flash(i) < 0) { - printf("Error Sector erasing \n"); - return FLASH_FAIL; - } - } - } -#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - if (cnt == FLASH_TOT_SECT) { - printf("Erasing flash, Please Wait \n"); - if (erase_flash() < 0) { - printf("Erasing flash failed \n"); - return FLASH_FAIL; - } - } else { - printf("Erasing Flash locations, Please Wait\n"); - for (i = s_first; i <= s_last; i++) { - if (info->protect[i] == 0) { /* not protected */ - if (erase_block_flash(i) < 0) { - printf("Error Sector erasing \n"); - return FLASH_FAIL; - } - } - } - } -#endif - printf("\n"); - return FLASH_SUCCESS; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int d; - if (addr % 2) { - read_flash(addr - 1 - CFG_FLASH_BASE, &d); - d = (int)((d & 0x00FF) | (*src++ << 8)); - write_data(addr - 1, 2, (uchar *) & d); - write_data(addr + 1, cnt - 1, src); - } else - write_data(addr, cnt, src); - return FLASH_SUCCESS; -} - -int write_data(long lStart, long lCount, uchar * pnData) -{ - long i = 0; - unsigned long ulOffset = lStart - CFG_FLASH_BASE; - int d; - int nSector = 0; - int flag = 0; - - if (lCount % 2) { - flag = 1; - lCount = lCount - 1; - } - - for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) { - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - d = (int)(pnData[i] | pnData[i + 1] << 8); - write_flash(ulOffset, d); - if (poll_toggle_bit(ulOffset) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - if ((i > 0) && (!(i % AFP_SectorSize2))) - printf("."); - } - if (flag) { - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - d = (int)(pnData[i] | (d & 0xFF00)); - write_flash(ulOffset, d); - if (poll_toggle_bit(ulOffset) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - } - return FLASH_SUCCESS; -} - -int write_flash(long nOffset, int nValue) -{ - long addr; - - addr = (CFG_FLASH_BASE + nOffset); - *(unsigned volatile short *)addr = nValue; - SSYNC(); -#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - if (icache_status()) - udelay(CONFIG_CCLK_HZ / 1000000); -#endif - return FLASH_SUCCESS; -} - -int read_flash(long nOffset, int *pnValue) -{ - unsigned short *pFlashAddr = - (unsigned short *)(CFG_FLASH_BASE + nOffset); - - *pnValue = *pFlashAddr; - - return TRUE; -} - -int poll_toggle_bit(long lOffset) -{ - unsigned int u1, u2; - volatile unsigned long *FB = - (volatile unsigned long *)(CFG_FLASH_BASE + lOffset); - while (1) { - u1 = *(volatile unsigned short *)FB; - u2 = *(volatile unsigned short *)FB; - u1 ^= u2; - if (!(u1 & 0x0040)) - break; - if (!(u2 & 0x0020)) - continue; - else { - u1 = *(volatile unsigned short *)FB; - u2 = *(volatile unsigned short *)FB; - u1 ^= u2; - if (!(u1 & 0x0040)) - break; - else { - reset_flash(); - return FLASH_FAIL; - } - } - } - return FLASH_SUCCESS; -} - -void reset_flash(void) -{ - write_flash(WRITESEQ1, RESET_VAL); - /* Wait for 10 micro seconds */ - udelay(10); -} - -int erase_flash(void) -{ - write_flash(WRITESEQ1, WRITEDATA1); - write_flash(WRITESEQ2, WRITEDATA2); - write_flash(WRITESEQ3, WRITEDATA3); - write_flash(WRITESEQ4, WRITEDATA4); - write_flash(WRITESEQ5, WRITEDATA5); - write_flash(WRITESEQ6, WRITEDATA6); - - if (poll_toggle_bit(0x0000) < 0) - return FLASH_FAIL; - - return FLASH_SUCCESS; -} - -int erase_block_flash(int nBlock) -{ - long ulSectorOff = 0x0; - - if ((nBlock < 0) || (nBlock > AFP_NumSectors)) - return FALSE; - - /* figure out the offset of the block in flash */ - if ((nBlock >= 0) && (nBlock < SecFlashABegin)) - ulSectorOff = nBlock * AFP_SectorSize1; - - else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS)) - ulSectorOff = - SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2; - /* no such sector */ - else - return FLASH_FAIL; - - write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); - write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); - write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); - write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); - write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); - - write_flash(ulSectorOff, BlockEraseVal); - - if (poll_toggle_bit(ulSectorOff) < 0) - return FLASH_FAIL; - printf("."); - - return FLASH_SUCCESS; -} - -void unlock_flash(long ulOffset) -{ - unsigned long ulOffsetAddr = ulOffset; - ulOffsetAddr &= 0xFFFF0000; - - write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); - write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); - write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); -} - -int get_codes() -{ - int dev_id = 0; - - write_flash(WRITESEQ1, GETCODEDATA1); - write_flash(WRITESEQ2, GETCODEDATA2); - write_flash(WRITESEQ3, GETCODEDATA3); - - read_flash(0x0402, &dev_id); - dev_id &= 0x0000FFFF; - - reset_flash(); - - return dev_id; -} - -void get_sector_number(long ulOffset, int *pnSector) -{ - int nSector = 0; - long lMainEnd = 0x400000; - long lBootEnd = 0x10000; - - /* sector numbers for the FLASH A boot sectors */ - if (ulOffset < lBootEnd) { - nSector = (int)ulOffset / AFP_SectorSize1; - } - /* sector numbers for the FLASH B boot sectors */ - else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) { - nSector = ((ulOffset / (AFP_SectorSize2)) + 7); - } - /* if it is a valid sector, set it */ - if ((nSector >= 0) && (nSector < AFP_NumSectors)) - *pnSector = nSector; - -} diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c index d72c861a13..a1a85d0fc9 100644 --- a/board/bmw/m48t59y.c +++ b/board/bmw/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -void +int rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,6 +295,8 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + + return 0; } void diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 77f7f48a6e..a72ba4620b 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -177,9 +177,9 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ /* stubs so we can print dates w/o any nvram RTC.*/ -void rtc_get (struct rtc_time *tmp) +int rtc_get (struct rtc_time *tmp) { - return; + return 0; } void rtc_set (struct rtc_time *tmp) { diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c index 18ab5005ef..263da6b7c9 100644 --- a/board/etin/debris/phantom.c +++ b/board/etin/debris/phantom.c @@ -182,7 +182,7 @@ static int get_century_flag(void) return flag; } -void rtc_get( struct rtc_time *tmp) +int rtc_get( struct rtc_time *tmp) { if (phantom_flag < 0) phantom_flag = get_phantom_flag(); @@ -250,6 +250,8 @@ void rtc_get( struct rtc_time *tmp) tmp->tm_yday = 0; tmp->tm_isdst= 0; } + + return 0; } void rtc_set( struct rtc_time *tmp ) diff --git a/board/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile index e3d757d5dd..e3d757d5dd 100644 --- a/board/mpc7448hpc2/Makefile +++ b/board/freescale/mpc7448hpc2/Makefile diff --git a/board/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S index a7a40a134c..a7a40a134c 100644 --- a/board/mpc7448hpc2/asm_init.S +++ b/board/freescale/mpc7448hpc2/asm_init.S diff --git a/board/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk index 2e58858c4f..2e58858c4f 100644 --- a/board/mpc7448hpc2/config.mk +++ b/board/freescale/mpc7448hpc2/config.mk diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c index 81846eba77..81846eba77 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c index 30ae17d872..30ae17d872 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/freescale/mpc7448hpc2/tsi108_init.c diff --git a/board/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds index 05f0269f40..05f0269f40 100644 --- a/board/mpc7448hpc2/u-boot.lds +++ b/board/freescale/mpc7448hpc2/u-boot.lds diff --git a/board/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile index de7d847a5f..de7d847a5f 100644 --- a/board/mpc8260ads/Makefile +++ b/board/freescale/mpc8260ads/Makefile diff --git a/board/mpc8260ads/config.mk b/board/freescale/mpc8260ads/config.mk index e99e181dda..e99e181dda 100644 --- a/board/mpc8260ads/config.mk +++ b/board/freescale/mpc8260ads/config.mk diff --git a/board/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c index 59997aac4f..59997aac4f 100644 --- a/board/mpc8260ads/flash.c +++ b/board/freescale/mpc8260ads/flash.c diff --git a/board/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index 93550e2ad0..93550e2ad0 100644 --- a/board/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c diff --git a/board/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile index 291a1c9566..291a1c9566 100644 --- a/board/mpc8266ads/Makefile +++ b/board/freescale/mpc8266ads/Makefile diff --git a/board/mpc8266ads/config.mk b/board/freescale/mpc8266ads/config.mk index ecc2a7db61..ecc2a7db61 100644 --- a/board/mpc8266ads/config.mk +++ b/board/freescale/mpc8266ads/config.mk diff --git a/board/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c index 9512c72a0b..9512c72a0b 100644 --- a/board/mpc8266ads/flash.c +++ b/board/freescale/mpc8266ads/flash.c diff --git a/board/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 8f7273c41d..8f7273c41d 100644 --- a/board/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 42019fb80c..7cbdb7bf31 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -28,6 +28,7 @@ #endif #include <pci.h> #include <mpc83xx.h> +#include <vsc7385.h> DECLARE_GLOBAL_DATA_PTR; @@ -98,6 +99,26 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 972361fd68..704f9636bc 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -25,6 +25,7 @@ #include <mpc83xx.h> #include <i2c.h> #include <miiphy.h> +#include <vsc7385.h> #ifdef CONFIG_PCI #include <asm/mpc8349_pci.h> #include <pci.h> @@ -177,7 +178,7 @@ int checkboard(void) */ int misc_init_f(void) { -#ifdef CONFIG_VSC7385 +#ifdef CONFIG_VSC7385_ENET volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -239,6 +240,8 @@ int misc_init_f(void) } /* + * Miscellaneous late-boot configurations + * * Make sure the EEPROM has the HRCW correctly programmed. * Make sure the RTC is correctly programmed. * @@ -250,6 +253,8 @@ int misc_init_f(void) * * This function makes sure that the I2C EEPROM is programmed * correctly. + * + * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { @@ -375,6 +380,14 @@ int misc_init_r(void) i2c_set_bus_num(orig_bus); #endif +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + return rc; } diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile index acc954488f..53e0c48276 100644 --- a/board/freescale/mpc8360erdk/Makefile +++ b/board/freescale/mpc8360erdk/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_CMD_NAND) += nand.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 8005a50531..3bcdda7334 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -186,6 +186,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + /* AD7843 ADC/Touchscreen controller */ + {4, 14, 1, 0, 0}, /* SPI_nCS0 */ + {4, 28, 3, 0, 3}, /* SPI_MOSI */ + {4, 29, 3, 0, 3}, /* SPI_MISO */ + {4, 30, 3, 0, 3}, /* SPI_CLK */ + + /* Freescale QUICC Engine USB Host Controller (FHCI) */ + {1, 2, 1, 0, 3}, /* USBOE */ + {1, 3, 1, 0, 3}, /* USBTP */ + {1, 8, 1, 0, 1}, /* USBTN */ + {1, 9, 2, 1, 3}, /* USBRP */ + {1, 10, 2, 0, 3}, /* USBRXD */ + {1, 11, 2, 1, 3}, /* USBRN */ + {2, 20, 2, 0, 1}, /* CLK21 */ + {4, 20, 1, 0, 0}, /* SPEED */ + {4, 21, 1, 0, 0}, /* SUSPND */ + /* END of table */ {0, 0, 0, 0, QE_IOP_TAB_END}, }; diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c new file mode 100644 index 0000000000..e1e790b34f --- /dev/null +++ b/board/freescale/mpc8360erdk/nand.c @@ -0,0 +1,72 @@ +/* + * MPC8360E-RDK support for the NAND on FSL UPM + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/fsl_upm.h> +#include <nand.h> + +static struct immap *im = (struct immap *)CFG_IMMR; + +static const u32 upm_array[] = { + 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ + 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ + 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ + 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ + 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ + 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ + 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ + 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ + 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ + 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ + 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ + 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ +}; + +static int dev_ready(void) +{ + if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { + debug("nand ready\n"); + return 1; + } + + debug("nand busy\n"); + return 0; +} + +static struct fsl_upm_nand fun = { + .upm = { + .array = upm_array, + .io_addr = (void *)CFG_NAND_BASE, + }, + .width = 1, + .upm_cmd_offset = 8, + .upm_addr_offset = 16, + .dev_ready = dev_ready, + .wait_pattern = 1, + .chip_delay = 50, +}; + +int board_nand_init(struct nand_chip *nand) +{ + fun.upm.mxmr = &im->lbus.mamr; + fun.upm.mdr = &im->lbus.mdr; + fun.upm.mar = &im->lbus.mar; + return fsl_upm_nand_init(nand, &fun); +} diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index bed0fc37ea..83fb60da00 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -15,7 +15,10 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> +#include <vsc7385.h> + #if defined(CFG_DRAM_TEST) int @@ -56,11 +59,6 @@ testdram(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) void ddr_enable_ecc(unsigned int dram_size); #endif @@ -135,6 +133,62 @@ int checkboard(void) return 0; } +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CFG_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (spridr >> 16) { + case SPR_8379E_REV10 >> 16: + case SPR_8379_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378E_REV10 >> 16: + case SPR_8378_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8377E_REV10 >> 16: + case SPR_8377_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) @@ -143,5 +197,6 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_setup(blob, bd); #endif ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 9fa0e747b9..8bdfe78e41 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2004 + * (C) Copyright 2003-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004 @@ -30,6 +30,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> #include <malloc.h> #ifndef CFG_RAMBOOT @@ -84,6 +85,7 @@ long int initdram (int board_type) ulong dramsize = 0; #ifndef CFG_RAMBOOT ulong test1, test2; + uint svr, pvr; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -147,6 +149,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + /* return dramsize + dramsize2; */ return dramsize; } diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index dbf0ecc5af..c624b3d82e 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -26,9 +26,15 @@ #include <asm/addrspace.h> #include <asm/inca-ip.h> #include <asm/io.h> +#include <asm/reboot.h> extern uint incaip_get_cpuclk(void); +void _machine_restart(void) +{ + *INCA_IP_WDT_RST_REQ = 0x3f; +} + static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index 14d738aa1a..b39f93d43f 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -276,6 +276,12 @@ __sdram_init: .ent lowlevel_init lowlevel_init: + /* Disable Watchdog. + */ + la t9, disable_incaip_wdt + jalr t9 + nop + /* EBU, CGU and SDRAM Initialization. */ li a0, CPU_CLOCK_RATE diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 815c01f4e4..e5fa25937b 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,25 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); +#if CONFIG_POST & CFG_POST_BSPEC1 + gpio_write_bit(CFG_GPIO_HIGHSIDE, 1); + + reg = 0; /* reuse as counter */ + out_be32((void *)CFG_DSPIC_TEST_ADDR, + in_be32((void *)CFG_DSPIC_TEST_ADDR) + & ~CFG_DSPIC_TEST_MASK); + while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) { + udelay(1000); + } + gpio_write_bit(CFG_GPIO_HIGHSIDE, 0); + if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) { + /* set "boot error" flag */ + out_be32((void *)CFG_DSPIC_TEST_ADDR, + in_be32((void *)CFG_DSPIC_TEST_ADDR) | + CFG_DSPIC_TEST_MASK); + } +#endif + /* * Reset PHY's: * The PHY's need a 2nd reset pulse, since the MDIO address is latched @@ -548,11 +567,13 @@ unsigned int board_video_init (void) return CFG_LIME_BASE_0; } -void board_backlight_switch (int flag) +#define DEFAULT_BRIGHTNESS 0x64 + +static void board_backlight_brightness(int brightness) { - if (flag) { + if (brightness > 0) { /* pwm duty, lamp on */ - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x64); + out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness); out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701); } else { /* lamp off */ @@ -561,6 +582,22 @@ void board_backlight_switch (int flag) } } +void board_backlight_switch (int flag) +{ + char * param; + int rc; + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + #if defined(CONFIG_CONSOLE_EXTRA_INFO) /* * Return text to be printed besides the logo. @@ -575,3 +612,8 @@ void video_get_info_str (int line_number, char *info) } #endif #endif /* CONFIG_VIDEO */ + +void board_reset(void) +{ + gpio_write_bit(CFG_GPIO_BOARD_RESET, 1); +} diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c index 37a6244198..2c1e6cf8b7 100644 --- a/board/mousse/m48t59y.c +++ b/board/mousse/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -void +int rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,6 +295,8 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif + + return 0; } void diff --git a/board/netstal/common/hcu_flash.c b/board/netstal/common/hcu_flash.c deleted file mode 100644 index d0322f20da..0000000000 --- a/board/netstal/common/hcu_flash.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*-----------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*-----------------------------------------------------------------------*/ -/* - * This implementation assumes that the flash chips are uniform sector - * devices. This is true for all likely flash devices on a HCUx. - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - unsigned idx; - unsigned long sector_size = info->size / info->sector_count; - - for (idx = 0; idx < info->sector_count; idx += 1) { - info->start[idx] = base + (idx * sector_size); - } -} - -/*-----------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("ST Micro "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* (Reduced table of only parts expected in HCUx boards.) */ - switch (info->flash_id) { - case FLASH_MAN_AMD | FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_MAN_STM | FLASH_AM040: - printf ("MM29W040W (512 Kbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*-----------------------------------------------------------------------*/ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - asm("isync"); - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - asm("isync"); - - value = addr2[0]; - asm("isync"); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - printf("Unknown flash manufacturer code: 0x%x at %p\n", - value, addr); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* Calculate the sector offsets (Use HCUx Optimized code). */ - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, - *(A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors not erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* block erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; - for (i = 0; i < 50; i++) udelay (1000); - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* sector erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index 3d1d65d35e..53df61edbb 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a # NOBJS : Netstal common objects -NOBJS = fixed_sdram.o hcu_flash.o nm_bsp.o +NOBJS = fixed_sdram.o nm_bsp.o COBJS = $(BOARD).o SOBJS = diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index bb610e2d53..dc526fcd7a 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -201,3 +201,18 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 349c653e7f..5ffae65ea1 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -24,7 +24,7 @@ LIB = $(obj)lib$(BOARD).a # NOBJS : Netstal common objects -NOBJS = hcu_flash.o nm_bsp.o +NOBJS = nm_bsp.o COBJS = $(BOARD).o sdram.o SOBJS = init.o diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index c494e93ada..55e4cc69c6 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -499,3 +499,18 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index d3c2233606..0b16b50502 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -70,8 +70,6 @@ void dflush(void); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); - void board_add_ram_info(int use_default) { PPC4xx_SYS_INFO board_cfg; diff --git a/board/netstal/mcu25/Makefile b/board/netstal/mcu25/Makefile new file mode 100644 index 0000000000..53df61edbb --- /dev/null +++ b/board/netstal/mcu25/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007-2008 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +# NOBJS : Netstal common objects +NOBJS = fixed_sdram.o nm_bsp.o +COBJS = $(BOARD).o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj)../common/,$(NOBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/mcu25/README.txt b/board/netstal/mcu25/README.txt new file mode 100644 index 0000000000..d25fddd9ce --- /dev/null +++ b/board/netstal/mcu25/README.txt @@ -0,0 +1,59 @@ +MCU25 Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +0x70000000 + +Chip-Select 3: CAN Interface +---------------------------- +0x7800000 + + +Chip-Select 4: IMC-bus standard +------------------------------- + +Our IO-Bus (slow version) + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +Our IO-Bus (fast, but not yet use) + + +Memory Bank 1 -- SDRAM +------------------------------------- + +0x00000000 - 0x2ffffff # Default 64 MB diff --git a/board/netstal/mcu25/config.mk b/board/netstal/mcu25/config.mk new file mode 100644 index 0000000000..f0f2ea176e --- /dev/null +++ b/board/netstal/mcu25/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: MCU25 board +# +TEXT_BASE = 0xFFFB0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c new file mode 100644 index 0000000000..2b21444e2d --- /dev/null +++ b/board/netstal/mcu25/mcu25.c @@ -0,0 +1,217 @@ +/* + *(C) Copyright 2005-2008 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm-ppc/u-boot.h> +#include "../common/nm.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A) +#define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0) + +#define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10) +#define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C) +#define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e) +#define MCU_SW_INSTALL_REQUESTED 0x08 + +#define SDRAM_LEN (32 << 20) /* 32 MB - RAM */ + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +/* Attention: If you want 1 microsecs times from the external oscillator + * 0x00004051 is okay for u-boot/linux, but different from old vxworks values + * 0x00804051 causes problems with u-boot and linux! + */ +#define CPC0_CR0_VALUE 0x0007F03C +#define CPC0_CR1_VALUE 0x00004051 + +int board_early_init_f (void) +{ + /* Documented in A-1171 + * + * Interrupt controller setup for the MCU25 board. + * Note: IRQ 0-15 405GP internally generated; high; level sensitive + * IRQ 16 405GP internally generated; low; level sensitive + * IRQ 17-24 RESERVED/UNUSED + * IRQ 31 (EXT IRQ 6) (unused) + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr(cntrl1, CPC0_CR1_VALUE); + mtdcr(ecr, 0x60606000); + mtdcr(CPC0_EIRR, 0x7C000000); + out32(GPIO0_OR, CFG_GPIO0_OR ); + out32(GPIO0_TCR, CFG_GPIO0_TCR); + out32(GPIO0_ODR, CFG_GPIO0_ODR); + mtspr(ccr0, 0x00700000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} +#endif + +int sys_install_requested(void) +{ + u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER); + return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0; +} + +int checkboard (void) +{ + u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER); + u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION); + u16 generation = boardVersReg & 0x0f; + u16 index = boardVersReg & 0xf0; + + /* Cannot be done in board_early_init */ + mtdcr(cntrl0, CPC0_CR0_VALUE); + + /* Force /RTS to active. The board it not wired quite + * correctly to use cts/rtc flow control, so just force the + * /RST active and forget about it. + */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + nm_show_print(generation, index, hwConfig); + return 0; +} + +u32 hcu_led_get(void) +{ + return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff; +} + +/* + * hcu_led_set value to be placed into the LEDs (max 6 bit) + */ +void hcu_led_set(u32 value) +{ + out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram or initdram + * used for HCUx + */ +void sdram_init(void) +{ + return; +} + +/* + * hcu_get_slot + */ +u32 hcu_get_slot(void) +{ + u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS); + return slot & 0x7f; +} + +/* + * get_serial_number + */ +u32 get_serial_number(void) +{ + u32 serial = in_be32((u32 *)CFG_FLASH_BASE); + + if (serial == 0xffffffff) + return 0; + + return serial; +} + + +/* + * misc_init_r. + */ + +int misc_init_r(void) +{ + common_misc_init_r(); + set_params_for_sw_install( sys_install_requested(), "mcu25" ); + return 0; +} + +long int initdram(int board_type) +{ + unsigned int dram_size = 64*1024*1024; + init_ppc405_sdram(dram_size); + +#ifdef DEBUG + show_sdram_registers(); +#endif + + return dram_size; +} + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/netstal/mcu25/u-boot.lds b/board/netstal/mcu25/u-boot.lds new file mode 100644 index 0000000000..b6e28f839d --- /dev/null +++ b/board/netstal/mcu25/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/purple/purple.c b/board/purple/purple.c index 74718afb48..13a14556ba 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/addrspace.h> #include <asm/cacheops.h> +#include <asm/reboot.h> #include "sconsole.h" @@ -52,6 +53,13 @@ extern int asc_serial_getc (void); extern int asc_serial_tstc (void); extern void asc_serial_setbrg (void); +void _machine_restart(void) +{ + void (*f)(void) = (void *) 0xbfc00000; + + f(); +} + static void sdram_timing_init (ulong size) { register uint pass; diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index 61c2e9bd36..d08b422451 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -12,10 +12,17 @@ #include <common.h> #include <command.h> #include <asm/addrspace.h> -#include <asm/inca-ip.h> #include <asm/io.h> +#include <asm/reboot.h> #include <pci.h> +void _machine_restart(void) +{ + void (*f)(void) = (void *) 0xbfc00000; + + f(); +} + #if defined(CONFIG_PCI) static struct pci_controller hose; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 33ad2a32a5..e67145eb5b 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int initdram (int board_type) { ulong dramsize = 0; @@ -230,57 +229,6 @@ long int initdram (int board_type) #endif /* CONFIG_TQM5200_B */ } -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined(CONFIG_AEVFIFO) @@ -323,10 +271,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } |
