diff options
Diffstat (limited to 'board')
66 files changed, 1955 insertions, 1336 deletions
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig index f94a444cf2..98aa10ade0 100644 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -1,23 +1,15 @@ if TARGET_DB_MV784MP_GP -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "db-mv784mp-gp" config SYS_VENDOR - string default "Marvell" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "db-mv784mp-gp" endif diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d899a6..ce625e54d0 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -8,6 +8,10 @@ #include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <usb_mass_storage.h> + #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,3 +43,20 @@ int board_init(void) return 0; } + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 2ed8cf75d6..007c1ef37d 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -159,8 +159,8 @@ int board_mmc_getcd(struct mmc *mmc) gpio_direction_input(IMX_GPIO_NR(4, 5)); ret = gpio_get_value(IMX_GPIO_NR(4, 5)); } else { - gpio_direction_input(IMX_GPIO_NR(1, 4)); - ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); + gpio_direction_input(IMX_GPIO_NR(1, 5)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); } return ret; diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c index 8e90f9853a..05ffc4d1ac 100644 --- a/board/cogent/lcd.c +++ b/board/cogent/lcd.c @@ -234,7 +234,7 @@ lcd_heartbeat(void) void board_show_activity (ulong timestamp) { #ifdef CONFIG_STATUS_LED - if ((timestamp % (CONFIG_SYS_HZ / 2) == 0) + if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0) lcd_heartbeat (); #endif } diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index d0b0930f42..886c723900 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,12 +19,11 @@ #include <i2c.h> #include <usb.h> #include <mmc.h> -#include <nand.h> #include <twl4030.h> -#include <bmp_layout.h> #include <linux/compiler.h> #include <asm/io.h> +#include <asm/errno.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/mmc_host_def.h> @@ -33,6 +32,7 @@ #include <asm/ehci-omap.h> #include <asm/gpio.h> +#include "../common/common.h" #include "../common/eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,58 +43,6 @@ const omap3_sysinfo sysinfo = { "NAND", }; -static u32 gpmc_net_config[GPMC_MAX_REG] = { - NET_GPMC_CONFIG1, - NET_GPMC_CONFIG2, - NET_GPMC_CONFIG3, - NET_GPMC_CONFIG4, - NET_GPMC_CONFIG5, - NET_GPMC_CONFIG6, - 0 -}; - -#ifdef CONFIG_LCD -#ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res, splash_screen_nand_offset = 0x100000; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -1; -} -#else -static inline int splash_load_from_nand(void) -{ - return -1; -} -#endif /* CONFIG_CMD_NAND */ - #ifdef CONFIG_SPL_BUILD /* * Routine: get_board_mem_timings @@ -111,24 +59,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif +#define CM_T35_SPLASH_NAND_OFFSET 0x100000 + int splash_screen_prepare(void) { - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -1; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -1; - } - - return splash_load_from_nand(bmp_load_addr); + return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); } -#endif /* CONFIG_LCD */ /* * Routine: board_init @@ -154,34 +90,18 @@ int board_init(void) return 0; } -static u32 cm_t3x_rev; - /* * Routine: get_board_rev * Description: read system revision */ u32 get_board_rev(void) { - if (!cm_t3x_rev) - cm_t3x_rev = cl_eeprom_get_board_rev(); - - return cm_t3x_rev; + return cl_eeprom_get_board_rev(); }; -/* - * Routine: misc_init_r - * Description: display die ID - */ int misc_init_r(void) { - u32 board_rev = get_board_rev(); - u32 rev_major = board_rev / 100; - u32 rev_minor = board_rev - (rev_major * 100); - - if ((rev_minor / 10) * 10 == rev_minor) - rev_minor = rev_minor / 10; - - printf("PCB: %u.%u\n", rev_major, rev_minor); + cl_print_pcb_info(); dieid_num_r(); return 0; @@ -462,37 +382,12 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Routine: setup_net_chip_gmpc - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip_gmpc(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], - SB_T35_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); -} - #ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip * Description: reset the Ethernet controller via TPS65930 GPIO */ -static void reset_net_chip(void) +static int cm_t3x_reset_net_chip(int gpio) { /* Set GPIO1 of TPS65930 as output */ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, @@ -507,9 +402,10 @@ static void reset_net_chip(void) twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 0x02); mdelay(1); + return 0; } #else -static inline void reset_net_chip(void) {} +static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } #endif #ifdef CONFIG_SMC911X @@ -536,7 +432,6 @@ static int handle_mac_address(void) return eth_setenv_enetaddr("ethaddr", enetaddr); } - /* * Routine: board_eth_init * Description: initialize module and base-board Ethernet chips @@ -545,18 +440,16 @@ int board_eth_init(bd_t *bis) { int rc = 0, rc1 = 0; - setup_net_chip_gmpc(); - reset_net_chip(); - rc1 = handle_mac_address(); if (rc1) printf("No MAC address found! "); - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, + cm_t3x_reset_net_chip, -EINVAL); if (rc1 > 0) rc++; - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); if (rc1 > 0) rc++; @@ -564,16 +457,6 @@ int board_eth_init(bd_t *bis) } #endif -void __weak get_board_serial(struct tag_serialnr *serialnr) -{ - /* - * This corresponds to what happens when we can communicate with the - * eeprom but don't get a valid board serial value. - */ - serialnr->low = 0; - serialnr->high = 0; -}; - #ifdef CONFIG_USB_EHCI_OMAP struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, @@ -583,21 +466,12 @@ struct omap_usbhs_board_data usbhs_bdata = { #define SB_T35_USB_HUB_RESET_GPIO 167 int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { u8 val; int offset; - if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { - printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", - SB_T35_USB_HUB_RESET_GPIO); - return -1; - } - - gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); - udelay(1000); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); @@ -614,6 +488,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, int ehci_hcd_stop(void) { + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); return omap_ehci_hcd_stop(); } #endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig new file mode 100644 index 0000000000..2f5473d76a --- /dev/null +++ b/board/compulab/cm_t3517/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_T3517 + +config SYS_BOARD + default "cm_t3517" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_t3517" + +endif diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS new file mode 100644 index 0000000000..fbb6882138 --- /dev/null +++ b/board/compulab/cm_t3517/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T3517 BOARD +M: Igor Grinberg <grinberg@compulab.co.il> +S: Maintained +F: board/compulab/cm_t3517/ +F: include/configs/cm_t3517.h +F: configs/cm_t3517_defconfig diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile new file mode 100644 index 0000000000..4f0db01e37 --- /dev/null +++ b/board/compulab/cm_t3517/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> +# +# Authors: Igor Grinberg <grinberg@compulab.co.il> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t3517.o mux.o diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c new file mode 100644 index 0000000000..cac1ad9ef1 --- /dev/null +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <status_led.h> +#include <net.h> +#include <netdev.h> +#include <usb.h> +#include <mmc.h> +#include <linux/compiler.h> +#include <linux/usb/musb.h> + +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/am35x_def.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/musb.h> +#include <asm/omap_musb.h> +#include <asm/ehci-omap.h> + +#include "../common/common.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CM-T3517 board", + "NAND 128/512M", +}; + +#ifdef CONFIG_USB_MUSB_AM35X +static struct musb_hdrc_config cm_t3517_musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data cm_t3517_musb_board_data = { + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .reset = am35x_musb_reset, +}; + +static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" +#endif + .config = &cm_t3517_musb_config, + .power = 250, + .platform_ops = &am35x_ops, + .board_data = &cm_t3517_musb_board_data, +}; + +static void cm_t3517_musb_init(void) +{ + /* + * Set up USB clock/mode in the DEVCONF2 register. + * USB2.0 PHY reference clock is 13 MHz + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, + CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | + CONF2_VBDTCTEN | CONF2_DATPOL); + + if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, + (void *)AM35XX_IPSS_USBOTGSS_BASE)) + printf("Failed initializing AM35x MUSB!\n"); +} +#else +static inline void am3517_evm_musb_init(void) {} +#endif + +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + + cm_t3517_musb_init(); + + return 0; +} + +int misc_init_r(void) +{ + cl_print_pcb_info(); + dieid_num_r(); + + return 0; +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T35_CD_GPIO 144 +#define SB_T35_WP_GPIO 59 + +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); +} +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONTROL_EFUSE_EMAC_LSB 0x48002380 +#define CONTROL_EFUSE_EMAC_MSB 0x48002384 + +static int am3517_get_efuse_enetaddr(u8 *enetaddr) +{ + u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); + u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); + + enetaddr[0] = (u8)((msb >> 16) & 0xff); + enetaddr[1] = (u8)((msb >> 8) & 0xff); + enetaddr[2] = (u8)(msb & 0xff); + enetaddr[3] = (u8)((lsb >> 16) & 0xff); + enetaddr[4] = (u8)((lsb >> 8) & 0xff); + enetaddr[5] = (u8)(lsb & 0xff); + + return is_valid_ether_addr(enetaddr); +} + +static inline int cm_t3517_init_emac(bd_t *bis) +{ + int ret = cpu_eth_init(bis); + + if (ret > 0) + return ret; + + printf("Failed initializing EMAC! "); + return 0; +} +#else /* !CONFIG_DRIVER_TI_EMAC */ +static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } +static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } +#endif /* CONFIG_DRIVER_TI_EMAC */ + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int cm_t3517_handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr("ethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr); + if (ret) { + ret = am3517_get_efuse_enetaddr(enetaddr); + if (ret) + return ret; + } + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + +#define SB_T35_ETH_RST_GPIO 164 + +/* + * Routine: board_eth_init + * Description: initialize module and base-board Ethernet chips + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0, rc1 = 0; + + rc1 = cm_t3517_handle_mac_address(); + if (rc1) + printf("No MAC address found! "); + + rc1 = cm_t3517_init_emac(bis); + if (rc1 > 0) + rc++; + + rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, + NULL, SB_T35_ETH_RST_GPIO); + if (rc1 > 0) + rc++; + + return rc; +} + +#ifdef CONFIG_USB_EHCI_OMAP +static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define CM_T3517_USB_HUB_RESET_GPIO 152 +#define SB_T35_USB_HUB_RESET_GPIO 98 + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); + + return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); + + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c new file mode 100644 index 0000000000..88ce2cc2e6 --- /dev/null +++ b/board/compulab/cm_t3517/mux.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include <asm/io.h> + +void set_muxconf_regs(void) +{ + /* SDRC */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + + /* SB-T35 Ethernet */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ + /* DataImage backlight */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ + + /* SB-T35 SD/MMC WP GPIO59 */ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + /* SB-T35 Audio Enable GPIO61 */ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + /* SB-T35 Ethernet IRQ GPIO65 */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ + + /* UART3 Console */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + /* RTC V3020 nCS GPIO163 */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ + /* SB-T35 Ethernet nRESET GPIO164 */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ + + /* SB-T35 SD/MMC CD GPIO144 */ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ + /* WIFI nRESET GPIO145 */ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ + /* USB1 PHY Reset GPIO 146 */ + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ + /* USB2 PHY Reset GPIO 147 */ + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); + + /* I2C */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); + + /* SB-T35 USB HUB Reset GPIO98 */ + MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ + /* CM-T3517 USB HUB Reset GPIO152 */ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ + + /* RMII */ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(RMII_MDIO_CLK), (M0)); + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); + MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); + MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); + + /* Green LED GPIO186 */ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ + + /* SPI */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ + /* LCD reset GPIO157 */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ + + /* RTC V3020 CS Enable GPIO160 */ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ + /* SB-T35 LVDS Transmitter SHDN GPIO162 */ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ + + /* USB0 - mUSB */ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); + /* USB1 EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + /* USB2 EHCI */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SYS_BOOT */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ +} diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 944b7234d6..b1a067d881 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -100,16 +100,11 @@ uint mmc_get_env_part(struct mmc *mmc) #define SB_T54_CD_GPIO 228 #define SB_T54_WP_GPIO 229 -int board_mmc_getcd(struct mmc *mmc) -{ - return !gpio_get_value(SB_T54_CD_GPIO); -} - int board_mmc_init(bd_t *bis) { int ret0, ret1; - ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO); + ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO); if (ret0) printf("cm_t54: failed to initialize mmc0\n"); diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 4044ac9d62..dbf0009652 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -6,5 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SYS_I2C) += eeprom.o -obj-$(CONFIG_LCD) += omap3_display.o +obj-y += common.o +obj-$(CONFIG_SYS_I2C) += eeprom.o +obj-$(CONFIG_LCD) += omap3_display.o +obj-$(CONFIG_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c new file mode 100644 index 0000000000..b25d9a20b4 --- /dev/null +++ b/board/compulab/common/common.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/bootm.h> +#include <asm/gpio.h> + +#include "common.h" +#include "eeprom.h" + +void cl_print_pcb_info(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); +} + +#ifdef CONFIG_SERIAL_TAG +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; +#endif + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label) +{ + if (gpio_request(gpio, label)) { + printf("Error: can't obtain GPIO%d for %s", gpio, label); + return -1; + } + + gpio_direction_output(gpio, 0); + udelay(10); + gpio_set_value(gpio, 1); + udelay(1000); + return 0; +} + +void cl_usb_hub_deinit(int gpio) +{ + gpio_free(gpio); +} +#endif diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h new file mode 100644 index 0000000000..68ffb111dc --- /dev/null +++ b/board/compulab/common/common.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CL_COMMON_ +#define _CL_COMMON_ + +#include <asm/errno.h> + +void cl_print_pcb_info(void); + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label); +void cl_usb_hub_deinit(int gpio); +#else /* !CONFIG_CMD_USB */ +static inline int cl_usb_hub_init(int gpio, const char *label) +{ + return -ENOSYS; +} +static inline void cl_usb_hub_deinit(int gpio) {} +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_SPLASH_SCREEN +int cl_splash_screen_prepare(int nand_offset); +#else /* !CONFIG_SPLASH_SCREEN */ +static inline int cl_splash_screen_prepare(int nand_offset) +{ + return -ENOSYS; +} +#endif /* CONFIG_SPLASH_SCREEN */ + +#ifdef CONFIG_SMC911X +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio); +#else /* !CONFIG_SMC911X */ +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + return -ENOSYS; +} +#endif /* CONFIG_SMC911X */ + +#endif /* _CL_COMMON_ */ diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 2df3adabf8..a45e7be11f 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -109,23 +109,27 @@ int cl_eeprom_read_mac_addr(uchar *buf) return cl_eeprom_read(offset, buf, 6); } +static u32 board_rev; + /* * Routine: cl_eeprom_get_board_rev * Description: read system revision from eeprom */ u32 cl_eeprom_get_board_rev(void) { - u32 rev = 0; char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; + if (board_rev) + return board_rev; + if (cl_eeprom_setup_layout()) return 0; if (cl_eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) + if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE)) return 0; /* @@ -133,9 +137,9 @@ u32 cl_eeprom_get_board_rev(void) * representation. i.e. for rev 1.00: 0x100 --> 0x64 */ if (cl_eeprom_layout == LAYOUT_LEGACY) { - sprintf(str, "%x", rev); - rev = simple_strtoul(str, NULL, 10); + sprintf(str, "%x", board_rev); + board_rev = simple_strtoul(str, NULL, 10); } - return rev; + return board_rev; }; diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c new file mode 100644 index 0000000000..4561661987 --- /dev/null +++ b/board/compulab/common/omap3_smc911x.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +#include "common.h" + +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_OMAP_GPIO +static int cl_omap3_smc911x_reset_net_chip(int gpio) +{ + int err; + + if (!gpio_is_valid(gpio)) + return -EINVAL; + + err = gpio_request(gpio, "eth rst"); + if (err) + return err; + + /* Set gpio as output and send a pulse */ + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(1); + + return 0; +} +#else /* !CONFIG_OMAP_GPIO */ +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } +#endif /* CONFIG_OMAP_GPIO */ + +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + int ret; + + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); + + if (reset) + reset(rst_gpio); + else + cl_omap3_smc911x_reset_net_chip(rst_gpio); + + ret = smc911x_initialize(id, base_addr); + if (ret > 0) + return ret; + + printf("Failed initializing SMC911x! "); + return 0; +} diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c new file mode 100644 index 0000000000..49ed49b81e --- /dev/null +++ b/board/compulab/common/splash.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> +#include <bmp_layout.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + struct bmp_header *bmp_hdr; + int res; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_header_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot " + "and/or placed beyond DRAM boundaries.\n"); + + return -1; +} +#else +static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + return -1; +} +#endif /* CONFIG_CMD_NAND */ + +int cl_splash_screen_prepare(int nand_offset) +{ + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -1; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -1; + } + + return splash_load_from_nand(bmp_load_addr, nand_offset); +} diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 85c3567b0b..b1680741e1 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -377,7 +377,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev = NULL; long sz; - int i, res, cnt, old_ctrlc; + int i, res, old_ctrlc; char buffer[32]; char str[80]; int n; @@ -455,7 +455,6 @@ int do_auto_update(void) clear_ctrlc (); break; } - cnt++; } while (res < 0); } diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 55c20d02d3..29c688a787 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -23,7 +23,7 @@ */ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int *ptr = 0; + unsigned int *ptr; int count = 0; int count2 = 0; int i; @@ -35,12 +35,14 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Mark sync address */ ptr = 0; + /* cppcheck-suppress nullPointer */ *ptr = 0xffffffff; puts("\nWaiting for image from pci host -"); /* * Wait for host to write the start address */ + /* cppcheck-suppress nullPointer */ while (*ptr == 0xffffffff) { count++; if (!(count % 100)) { diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 7fe4ae74ea..9146f49262 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -15,6 +15,9 @@ #include <fdt_support.h> #include <fsl_mdio.h> #include <tsec.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <flash.h> #include <netdev.h> @@ -50,6 +53,11 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -61,6 +69,9 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif fdt_fixup_dr_usb(blob, bd); } diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 10580bcecc..c88838b3df 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -21,6 +21,9 @@ #include <hwconfig.h> #include <i2c.h> #include <fsl_ddr_sdram.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <flash.h> #ifdef CONFIG_PCI #include <pci.h> @@ -354,6 +357,12 @@ void fdt_del_node_compat(void *blob, const char *compatible) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "cfi-flash", MTD_DEV_TYPE_NOR, }, + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -369,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 porbmsr = in_be32(&gur->porbmsr); diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index 958ebc6791..f9d6324114 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -1,7 +1,7 @@ FREESCALE MX28EVK ================== -Supported hardware: only MX28EVK rev D is supported in U-boot. +Supported hardware: MX28EVK rev C and D are supported in U-boot. Files of the MX28EVK port -------------------------- diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b32a97ff1a..7569ded8d8 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -242,6 +242,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsb.dtb"); + /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); @@ -283,6 +285,8 @@ static int power_init(void) if (!p) return -ENODEV; + setenv("fdt_file", "imx53-qsrb.dtb"); + /* Set VDDGP to 1.25V for 1GHz on SW1 */ pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 42ae6fac5e..c35dcaf3cf 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) int dram_init(void) @@ -200,6 +205,63 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -336,6 +398,10 @@ int board_early_init_f(void) #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3d81fffea5..1142e8a27e 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -27,8 +27,12 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <asm/arch/mx6-ddr.h> + DECLARE_GLOBAL_DATA_PTR; +#define BOOT_CFG 0x020D8004 + #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -55,17 +59,16 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; } -iomux_v3_cfg_t const uart1_pads[] = { +static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -95,7 +98,7 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 25), 1); } -iomux_v3_cfg_t const usdhc2_pads[] = { +static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -109,7 +112,7 @@ iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -123,7 +126,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const usdhc4_pads[] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -136,7 +139,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -iomux_v3_cfg_t const ecspi1_pads[] = { +static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -253,7 +256,8 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; +#ifndef CONFIG_SPL_BUILD + int ret; int i; /* @@ -286,13 +290,52 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; } - return status; + return 0; +#else + unsigned reg = readl(BOOT_CFG) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #endif @@ -607,3 +650,144 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * This section require the differentiation + * between iMX6 Sabre Families. + * But for now, it will configure only for + * SabreSD. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 0000000000..2bf48175ef --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index 7b9e9b05f7..b83b9b7a45 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index f7f7fc0177..3886e3ded1 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,6 +5,7 @@ # obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c new file mode 100644 index 0000000000..d5f3812872 --- /dev/null +++ b/board/freescale/t4rdb/cpld.c @@ -0,0 +1,136 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK0; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h new file mode 100644 index 0000000000..0180082ca3 --- /dev/null +++ b/board/freescale/t4rdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan <Chunhe.Lan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 1f5876885c..39818fc4f1 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -16,6 +16,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index afef7e93d0..2ff77b8487 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -20,14 +20,26 @@ #include <fm_eth.h> #include "t4rdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); puts("SERDES Reference Clocks:\n"); printf(" SERDES1=100MHz SERDES2=156.25MHz\n" diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 4b50bcd09b..474301e2a7 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -106,6 +106,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 2ddb3da38f..b9aff1a84d 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -360,6 +360,7 @@ static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, testboot = (testpin != 0) && (s); if (verbose) { printf("testpin = %d\n", testpin); + /* cppcheck-suppress nullPointer */ printf("test_bank = %s\n", s ? s : "not set"); printf("boot test app : %s\n", (testboot) ? "yes" : "no"); } diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig index 4ba63999ae..94f1754a47 100644 --- a/board/kosagi/novena/Kconfig +++ b/board/kosagi/novena/Kconfig @@ -1,8 +1,5 @@ if TARGET_KOSAGI_NOVENA -config SYS_CPU - default "armv7" - config SYS_BOARD default "novena" diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c index 1a2ac8d6c8..db42987010 100644 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -348,7 +348,7 @@ int mac_read_from_eeprom(void) if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[9]; + char ethaddr[18]; sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", e.mac[0], diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig index d34e2abf36..d833ca0e25 100644 --- a/board/maxbcm/Kconfig +++ b/board/maxbcm/Kconfig @@ -1,19 +1,12 @@ if TARGET_MAXBCM -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "maxbcm" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "maxbcm" endif diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig deleted file mode 100644 index 3b27eeb1de..0000000000 --- a/board/mcc200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MCC200 - -config SYS_BOARD - default "mcc200" - -config SYS_CONFIG_NAME - default "mcc200" - -endif diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS deleted file mode 100644 index a59a498795..0000000000 --- a/board/mcc200/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -MCC200 BOARD -#M: - -S: Maintained -F: board/mcc200/ -F: include/configs/mcc200.h -F: configs/mcc200_defconfig -F: configs/mcc200_COM12_defconfig -F: configs/mcc200_COM12_highboot_defconfig -F: configs/mcc200_COM12_highboot_SDRAM_defconfig -F: configs/mcc200_COM12_SDRAM_defconfig -F: configs/mcc200_highboot_defconfig -F: configs/mcc200_highboot_SDRAM_defconfig -F: configs/mcc200_SDRAM_defconfig -F: configs/prs200_defconfig -F: configs/prs200_DDR_defconfig -F: configs/prs200_highboot_defconfig -F: configs/prs200_highboot_DDR_defconfig diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile deleted file mode 100644 index db3b39646a..0000000000 --- a/board/mcc200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mcc200.o lcd.o auto_update.o diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c deleted file mode 100644 index 43173ce060..0000000000 --- a/board/mcc200/auto_update.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <image.h> -#include <asm/byteorder.h> -#include <usb.h> -#include <part.h> - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CONFIG_SYS_HUSH_PARSER -#error "must define CONFIG_SYS_HUSH_PARSER" -#endif - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_FIRMWARE "u-boot.img" -#define AU_KERNEL "kernel.img" -#define AU_ROOTFS "rootfs.img" - -struct flash_layout { - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#define AU_FL_FIRMWARE_ST 0xfC000000 -#define AU_FL_FIRMWARE_ND 0xfC03FFFF -#define AU_FL_KERNEL_ST 0xfC0C0000 -#define AU_FL_KERNEL_ND 0xfC1BFFFF -#define AU_FL_ROOTFS_ST 0xFC1C0000 -#define AU_FL_ROOTFS_ND 0xFCFBFFFF - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_FIRMWARE 0 -#define IDX_KERNEL 1 -#define IDX_ROOTFS 2 - -/* max. number of files which could interest us */ -#define AU_MAXFILES 3 - -/* pointers to file names */ -char *aufile[AU_MAXFILES] = { - AU_FIRMWARE, - AU_KERNEL, - AU_ROOTFS -}; - -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES] = { - (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST, - (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST, - (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST, -}; - -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES] = { - { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, }, - { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, }, - { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, }, -}; - -ulong totsize; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x00200000) - -/* the root file system is the largest image */ -#define MAX_LOADSZ ausize[IDX_ROOTFS] - -/*i2c address of the keypad status*/ -#define I2C_PSOC_KEYPAD_ADDR 0x53 - -/* keypad mask */ -#define KEYPAD_ROW 2 -#define KEYPAD_COL 2 -#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) -#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -extern int u_boot_hush_start(void); -#ifdef CONFIG_PROGRESSBAR -extern void show_progress(int, int); -extern void lcd_puts (char *); -extern void lcd_enable(void); -#endif - -int au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (nbytes != image_get_image_size (hdr)) { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum, fsize; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_ROOTFS) && - (!image_check_type (hdr, IH_TYPE_RAMDISK) && - !image_check_type (hdr, IH_TYPE_FILESYSTEM))) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - - fsize = checksum + image_get_header_size (); - /* for kernel and ramdisk the image header must also fit into flash */ - if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK)) - checksum += image_get_header_size (); - - /* check the size does not exceed space in flash. HUSH scripts */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* Update with the real filesize */ - ausize[idx] = fsize; - - return checksum; /* return size to be written to flash */ -} - -int au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - run_command_list(addr, -1, 0); - return 0; - } - - start = aufl_layout[idx].start; - end = aufl_layout[idx].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - mdelay(100); -#ifdef CONFIG_PROGRESSBAR - show_progress(end - start, totsize); -#endif - - /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - -#ifdef CONFIG_PROGRESSBAR - show_progress(nbytes, totsize); -#endif - - /* check the data CRC of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res = 0, cnt, old_ctrlc; - char *env; - long start, end; - -#if 0 /* disable key-press detection to speed up boot-up time */ - uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; - - /* - * Read keypad status - */ - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); - mdelay(500); - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); - - /* - * Check keypad - */ - if ( !(keypad_status1[1] & KEYPAD_MASK_LO) || - (keypad_status1[1] != keypad_status2[1])) { - return 0; - } - -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - res = -1; - goto xit; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - res = -1; - goto xit; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[IDX_FIRMWARE].start = start; - aufl_layout[IDX_FIRMWARE].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[IDX_KERNEL].start = start; - aufl_layout[IDX_KERNEL].end = end; - } - start = -1; - end = 0; - env = getenv("rootfs_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("rootfs_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_ROOTFS] = (end + 1) - start; - aufl_layout[IDX_ROOTFS].start = start; - aufl_layout[IDX_ROOTFS].end = end; - } - - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - /* validate the images first */ - for (i = 0; i < AU_MAXFILES; i++) { - ulong imsize; - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - ausize[i] = 0; - continue; - } - /* au_check_header_valid() updates ausize[] */ - if ((imsize = au_check_header_valid(i, sz)) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - /* totsize accounts for image size and flash erase size */ - totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start)); - } - -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - lcd_puts(" Update in progress\n"); - lcd_enable(); - } -#endif - - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES && totsize; i++) { - if (!ausize[i]) { - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]); - - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - - if (sz != ausize[i]) { - printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz); - continue; - } - - if (sz <= 0 || sz <= image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < (AU_MAXFILES + 1)); - if (cnt < (AU_MAXFILES + 1)) -#else - } while (res < 0); -#endif - } - - /* restore the old state */ - disable_ctrlc(old_ctrlc); -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - if (!res) { - lcd_puts("\n Update completed\n"); - } else { - lcd_puts("\n Update error\n"); - } - lcd_enable(); - } -#endif - xit: - usb_stop(); - return res; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c deleted file mode 100644 index c911445d97..0000000000 --- a/board/mcc200/lcd.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <mpc5xxx.h> -#include <malloc.h> - -#ifdef CONFIG_LCD - -#undef SWAPPED_LCD /* For the previous h/w version */ -/* - * The name of the device used for communication - * with the PSoC. - */ -#define PSOC_PSC MPC5XXX_PSC2 -#define PSOC_BAUD 230400UL - -#define RTS_ASSERT 1 -#define RTS_NEGATE 0 -#define CTS_ASSERT 1 -#define CTS_NEGATE 0 - -/* - * Dimensions in pixels - */ -#define LCD_WIDTH 160 -#define LCD_HEIGHT 100 - -/* - * Dimensions in bytes - */ -#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) - -#if LCD_BPP != LCD_MONOCHROME -#error "MCC200 support only monochrome displays (1 bpp)!" -#endif - -#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ -#define PSOC_WAIT_TIME 10 /* usec */ - -#include <video_font.h> -#define FONT_WIDTH VIDEO_FONT_WIDTH - -DECLARE_GLOBAL_DATA_PTR; - -/* - * LCD information - */ -vidinfo_t panel_info = { - LCD_WIDTH, LCD_HEIGHT, LCD_BPP -}; - - -/* - * The device we use to communicate with PSoC - */ -int serial_inited = 0; - -/* - * Imported functions to support the PSoC protocol - */ -extern int serial_init_dev (unsigned long dev_base); -extern void serial_setrts_dev (unsigned long dev_base, int s); -extern int serial_getcts_dev (unsigned long dev_base); -extern void serial_putc_raw_dev(unsigned long dev_base, const char c); - -/* - * Just stubs for our driver, needed for compiling compabilty with - * the common LCD driver code. - */ -void lcd_initcolregs (void) -{ -} - -void lcd_ctrl_init (void *lcdbase) -{ -} - -/* - * Function sends the contents of the frame-buffer to the LCD - */ -void lcd_enable (void) -{ - int i, retries, fb_size; - - if (!serial_inited) { - unsigned long baud; - - baud = gd->baudrate; - gd->baudrate = PSOC_BAUD; - serial_init_dev(PSOC_PSC); - gd->baudrate = baud; - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - serial_inited = 1; - } - - /* - * Implement PSoC communication protocol: - * 1. Assert RTS, wait CTS assertion - * 2. Transmit data - * 3. Negate RTS, wait CTS negation - */ - - /* 1 */ - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) - break; - udelay (PSOC_WAIT_TIME); - } - if (!retries) { - printf ("%s Error: PSoC doesn't respond on " - "RTS ASSERT\n", __FUNCTION__); - } - - /* 2 */ - fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); - -#if !defined(SWAPPED_LCD) - for (i=0; i<fb_size; i++) { - serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]); - } -#else - { - int x, y, pwidth; - char *p = (char *)gd->fb_base; - - pwidth = ((panel_info.vl_col+7) >> 3); - for (y=0; y<panel_info.vl_row; y++) { - i = y * pwidth; - for (x=0; x<pwidth; x+=5) { - serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); - } - } - } -#endif - - /* 3 */ - serial_setrts_dev (PSOC_PSC, RTS_NEGATE); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) - break; - udelay (PSOC_WAIT_TIME); - } - - return; -} -#ifdef CONFIG_PROGRESSBAR - -void show_progress (int size, int tot) -{ - int cnt; - int i; - static int rc = 0; - - rc += size; - - cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot; - - rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH); - - for (i = 0; i < cnt; i++) { - lcd_putc(0xdc); - } - - if (cnt) { - lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */ - } -} - -#endif - -int bmp_display(ulong addr, int x, int y) -{ - int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - - ret = lcd_display_bitmap((ulong)bmp, x, y); - - if ((unsigned long)bmp != addr) - free(bmp); - - return ret; -} - -#endif /* CONFIG_LCD */ diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c deleted file mode 100644 index 706886b84a..0000000000 --- a/board/mcc200/mcc200.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> - -/* Two MT48LC8M32B2 for 32 MB */ -/* #include "mt48lc8m32b2-6-7.h" */ - -/* One MT48LC16M32S2 for 64 MB */ -/* #include "mt48lc16m32s2-75.h" */ -#if defined (CONFIG_MCC200_SDRAM) -#include "mt48lc16m16a2-75.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -extern int do_auto_update(void); -ulong flash_get_size (ulong base, int banknum); - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); - - udelay(10); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ -#if defined(CONFIG_PRS200) - puts ("Board: PRS200\n"); -#else - puts ("Board: MCC200\n"); -#endif - return 0; -} - -int misc_init_r (void) -{ - ulong flash_sup_end, snum; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(gd->bd->bi_flashstart); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - if (gd->bd->bi_flashsize > (32 << 20)) { - /* Unprotect the upper bank of the Flash */ - *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); - flash_protect (FLAG_PROTECT_CLEAR, - flash_info[0].start[0] + flash_info[0].size / 2, - (flash_info[0].start[0] - 1) + flash_info[0].size, - &flash_info[0]); - *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); - printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); - flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; - snum++); - flash_info[0].sector_count = snum; - } - -#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); -#endif - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h deleted file mode 100644 index 9068fbf36f..0000000000 --- a/board/mcc200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h deleted file mode 100644 index 13aebbd8af..0000000000 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ -#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ -#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ -#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index e3a582f3dc..73bfa00eed 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -72,8 +72,10 @@ static FLASH_BUS_RET flash_status_reg (void) FLASH_BUS *addr = (FLASH_BUS *) 0; + /* cppcheck-suppress nullPointer */ *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + /* cppcheck-suppress nullPointer */ return *addr; } diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 64e69dc93d..559af0e0e5 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -229,7 +229,7 @@ int board_eth_init(bd_t *bis) #endif /* #ifdef CONFIG_FACTORYSET */ /* Set rgmii mode and enable rmii clock to be sourced from chip */ - writel(RGMII_MODE_ENABLE , &cdev->miisel); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5b2d091122..c3f865d298 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -16,6 +16,7 @@ config MACH_SUN5I config MACH_SUN6I bool "sun6i (Allwinner A31)" select CPU_V7 + select SUPPORT_SPL config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -111,6 +112,10 @@ config TARGET_MELE_M3 bool "MELE_M3" depends on MACH_SUN7I +config TARGET_MELE_M9 + bool "MELE_M9" + depends on MACH_SUN6I + config TARGET_MINI_X_1GB bool "MINI_X_1GB" depends on MACH_SUN4I @@ -192,4 +197,20 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config USB1_VBUS_PIN + string "Vbus enable pin for usb1 (ehci0)" + default "PH6" if MACH_SUN4I || MACH_SUN7I + default "PH27" if MACH_SUN6I + ---help--- + Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes + a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config USB2_VBUS_PIN + string "Vbus enable pin for usb2 (ehci1)" + default "PH3" if MACH_SUN4I || MACH_SUN7I + default "PH24" if MACH_SUN6I + ---help--- + See USB1_VBUS_PIN help text. + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index b3c77a83cb..ca0300272e 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -9,6 +9,7 @@ F: configs/Cubieboard_defconfig F: configs/Mele_A1000_defconfig F: configs/Mele_A1000G_defconfig F: configs/Mele_M3_defconfig +F: configs/Mele_M9_defconfig F: configs/Mini-X_defconfig F: configs/Mini-X-1Gb_defconfig F: include/configs/sun5i.h diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 03890c8c9c..e6ec5b8fc1 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -19,6 +19,9 @@ #ifdef CONFIG_AXP209_POWER #include <axp209.h> #endif +#ifdef CONFIG_AXP221_POWER +#include <axp221.h> +#endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/dram.h> @@ -169,6 +172,29 @@ void sunxi_board_init(void) power_failed |= axp209_set_ldo3(2800); power_failed |= axp209_set_ldo4(2800); #endif +#ifdef CONFIG_AXP221_POWER + power_failed = axp221_init(); + power_failed |= axp221_set_dcdc1(3000); + power_failed |= axp221_set_dcdc2(1200); + power_failed |= axp221_set_dcdc3(1200); + power_failed |= axp221_set_dcdc4(1200); + power_failed |= axp221_set_dcdc5(1500); +#if CONFIG_AXP221_DLDO1_VOLT != -1 + power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); +#endif +#if CONFIG_AXP221_DLDO4_VOLT != -1 + power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); +#endif +#if CONFIG_AXP221_ALDO1_VOLT != -1 + power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); +#endif +#if CONFIG_AXP221_ALDO2_VOLT != -1 + power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); +#endif +#if CONFIG_AXP221_ALDO3_VOLT != -1 + power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); +#endif +#endif printf("DRAM:"); ramsize = sunxi_dram_init(); diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 6348d27282..051aca01a8 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -29,7 +29,7 @@ int sunxi_gmac_initialize(bd_t *bis) * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" * of the GMAC clk register to 3. */ -#ifdef CONFIG_BANANAPI +#ifdef CONFIG_TARGET_BANANAPI setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); #endif diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig new file mode 100644 index 0000000000..c514e24fa1 --- /dev/null +++ b/board/tbs/tbs2910/Kconfig @@ -0,0 +1,23 @@ +if TARGET_TBS2910 + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "tbs2910" + +config SYS_VENDOR + string + default "tbs" + +config SYS_SOC + string + default "mx6" + +config SYS_CONFIG_NAME + string + default "tbs2910" + +endif diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS new file mode 100644 index 0000000000..bf176553d2 --- /dev/null +++ b/board/tbs/tbs2910/MAINTAINERS @@ -0,0 +1,6 @@ +TBS2910 BOARD +M: Soeren Moch <smoch@web.de> +S: Maintained +F: board/tbs/tbs2910/ +F: configs/tbs2910_defconfig +F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile new file mode 100644 index 0000000000..9d9eb8722d --- /dev/null +++ b/board/tbs/tbs2910/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Soeren Moch <smoch@web.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tbs2910.o diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c new file mode 100644 index 0000000000..daf8ff4e62 --- /dev/null +++ b/board/tbs/tbs2910/tbs2910.c @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2014 Soeren Moch <smoch@web.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/sata.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + +#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#ifdef CONFIG_SYS_I2C +/* I2C1, SGTL5000 */ +static struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +/* I2C2 HDMI */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, CON11, DS1307, PCIe_SMB */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 6) + } +}; +#endif /* CONFIG_SYS_I2C */ + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 PHY Reset */ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pcie_pads[] = { + /* W_DISABLE# */ + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + /* PERST# */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int dram_init(void) +{ + gd->ram_size = 2048ul * 1024 * 1024; + return 0; +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8035 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); +} + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + int i; + + /* + * (U-boot device node) (Physical Port) + * mmc0 SD2 + * mmc1 SD3 + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + } + return status; +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_VIDEO_IPUV3 +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + /* 1024x768@60Hz (VESA)*/ + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* select video pll for ldb_di0_clk */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); + writel(reg, &ccm->cs2cdr); + + /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */ + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + setup_pcie(); + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif +#ifdef CONFIG_DWC_AHSATA + setup_sata(); +#endif +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: TBS2910 Matrix ARM mini PC\n"); + return 0; +} diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index b9f6bd7122..1ddbb2c67c 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -22,4 +22,19 @@ config CONS_INDEX board you may want something other than UART0 as for example the IDK uses UART3 so enter 4 here. +config NOR + bool "Support for NOR flash" + help + The AM335x SoC supports having a NOR flash connected to the GPMC. + In practice this is seen as a NOR flash module connected to the + "memory cape" for the BeagleBone family. + +config NOR_BOOT + bool "Support for booting from NOR flash" + depends on NOR + help + Enabling this will make a U-Boot binary that is capable of being + booted via NOR. In this case we will enable certain pinmux early + as the ROM only partially sets up pinmux. We also default to using + NOR for environment. endif diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 96c5f22ead..384b175e9c 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -27,15 +27,12 @@ endif if TARGET_K2L_EVM config SYS_BOARD - string default "ks2_evm" config SYS_VENDOR - string default "ti" config SYS_CONFIG_NAME - string default "k2l_evm" endif diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index a551e2869a..9ee90a4f9d 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -3,10 +3,11 @@ U-Boot port for Texas Instruments Keystone II EVM boards Author: Murali Karicheri <m-karicheri2@ti.com> -This README has information on the u-boot port for K2HK, K2E boards. +This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards. Documentation for this board can be found at http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. More details on these SoCs are available at company websites @@ -14,7 +15,10 @@ More details on these SoCs are available at company websites K2H: http://www.ti.com/product/tci6638k2h The K2E SoC details are available at - K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + +The K2L SoC details are available at + http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf Board configuration: ==================== @@ -25,6 +29,7 @@ Some of the peripherals that are configured by u-boot +------+-------+-------+-----------+-----------+-------+-------+----+ |K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | |K2E |4 |512MB |2MB |8(2) |2 |3 |3 | +|K2L |2 |512MB |2MB |4(2) |4 |3 |3 | +------+-------+-------+-----------+-----------+-------+-------+----+ There are only 2 eth port installed on the boards. @@ -41,10 +46,13 @@ The port related files can be found at following folders Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h +include/configs/k2l_evm.h +include/configs/k2l_evm.h As u-boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig configs/k2hk_evm_defconfig +configs/k2l_evm_defconfig Supported boot modes: - SPI NOR boot @@ -58,7 +66,7 @@ Supported image formats: Build instructions: =================== -Examples for k2hk, for k2e just replace k2hk prefix accordingly. +Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin @@ -84,6 +92,8 @@ Use u-boot.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup +K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup + to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" and Power ON the EVM. Follow instructions to connect serial port of EVM to PC and start TeraTerm or Hyper Terminal. @@ -128,8 +138,8 @@ instructions: 2. Suspend Target. Select Run -> Suspend from top level menu CortexA15_1 (Free Running)" 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM - using CCS", but using address 0x87000000. + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L + EVM using CCS", but using address 0x87000000. 4. Free Run the target as described earlier (step 4) to get u-boot prompt 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x87000000 diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 4029493452..ff7bc4bb18 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd) int nbanks; u64 size[2]; u64 start[2]; - char name[32]; int nodeoffset; u32 ddr3a_size; int unitrd_fixup = 0; @@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd) } /* reserve memory at start of bank */ - sprintf(name, "mem_reserve_head"); - env = getenv(name); + env = getenv("mem_reserve_head"); if (env) { start[0] += ustrtoul(env, &endp, 0); size[0] -= ustrtoul(env, &endp, 0); } - sprintf(name, "mem_reserve"); - env = getenv(name); + env = getenv("mem_reserve"); if (env) size[0] -= ustrtoul(env, &endp, 0); diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 559d20ca88..729a193239 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h> -#include <asm/ti-common/ti-aemif.h> +#include <asm/ti-common/keystone_net.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +42,44 @@ static struct pll_init_data tetris_pll_config[] = { static struct pll_init_data pa_pll_config = PASS_PLL_983; +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2L_EMAC", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2L_EMAC3", + .rx_flow = 32, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore index 68b8edd260..7c36bc963f 100644 --- a/board/xilinx/zynq/.gitignore +++ b/board/xilinx/zynq/.gitignore @@ -1 +1,2 @@ ps7_init.[ch] +ps7_init_gpl.[ch] diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 71c0c351f9..3b1eb4f74a 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -7,9 +7,11 @@ obj-y := board.o -# Please copy ps7_init.c/h from hw project to this directory +# Please copy ps7_init_gpl.c/h from hw project to this directory obj-$(CONFIG_SPL_BUILD) += \ - $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o) + $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \ + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o)) # Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c new file mode 100644 index 0000000000..4ae913eefe --- /dev/null +++ b/board/xilinx/zynq/legacy.c @@ -0,0 +1,2 @@ + +#warning usage of ps7_init files is deprecated please use ps7_init_gpl diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h index e59a977eb1..1eccf8d91d 100644 --- a/board/xilinx/zynq/xil_io.h +++ b/board/xilinx/zynq/xil_io.h @@ -6,7 +6,7 @@ #define XIL_IO_H /* - * This empty file is here because ps7_init.c exported by hw project + * This empty file is here because ps7_init_gpl.c exported by hw project * has #include "xil_io.h" line. */ |
