diff options
Diffstat (limited to 'board')
46 files changed, 2322 insertions, 1008 deletions
diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig index 6d4151453f..b4fa9a2b38 100644 --- a/board/atmel/atstk1000/Kconfig +++ b/board/atmel/atstk1000/Kconfig @@ -13,51 +13,3 @@ config SYS_CONFIG_NAME default "atstk1002" endif - -if TARGET_ATSTK1003 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1003" - -endif - -if TARGET_ATSTK1004 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1004" - -endif - -if TARGET_ATSTK1006 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1006" - -endif diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS index 378e1b3dbc..1070f98e53 100644 --- a/board/atmel/atstk1000/MAINTAINERS +++ b/board/atmel/atstk1000/MAINTAINERS @@ -1,12 +1,6 @@ ATSTK1000 BOARD -#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> -S: Orphan (since 2014-06) +M: Andreas Bießmann <andreas.biessmann@corscience.de> +S: Maintained F: board/atmel/atstk1000/ F: include/configs/atstk1002.h F: configs/atstk1002_defconfig -F: include/configs/atstk1003.h -F: configs/atstk1003_defconfig -F: include/configs/atstk1004.h -F: configs/atstk1004_defconfig -F: include/configs/atstk1006.h -F: configs/atstk1006_defconfig diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index fd4363bece..679b67432c 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { }; static const struct sdram_config sdram_config = { -#if defined(CONFIG_ATSTK1006) - /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */ .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 2, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 4, - .txsr = 7, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -#else - /* MT48LC2M32B2P-5 (8 MB) on motherboard */ -#ifdef CONFIG_ATSTK1004 - .data_bits = SDRAM_DATA_16BIT, -#else - .data_bits = SDRAM_DATA_32BIT, -#endif #ifdef CONFIG_ATSTK1000_16MB_SDRAM /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */ .row_bits = 12, #else + /* MT48LC2M32B2P-5 (8 MB) on motherboard */ .row_bits = 11, #endif .col_bits = 8, @@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = { .txsr = 5, /* 15.6 us */ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -#endif }; int board_early_init_f(void) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index e434ed9b87..2237b7aa1f 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -120,6 +120,42 @@ static void setup_iomux_features(void) ARRAY_SIZE(feature_pads)); } +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C2 - EEPROM */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* I2C3 - IO expander */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void setup_iomux_i2c(void) +{ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +} + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -151,6 +187,7 @@ int board_early_init_f(void) setup_iomux_uart(); setup_iomux_spi(); + setup_iomux_i2c(); setup_iomux_features(); return 0; @@ -236,22 +273,6 @@ int board_mmc_init(bd_t *bis) return 0; } -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C3 - IO expander */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - static iomux_v3_cfg_t const pwm_pad[] = { MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), }; @@ -315,8 +336,6 @@ int board_init(void) backlight_lcd_off(); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - leds_on(); #ifdef CONFIG_CMD_SATA diff --git a/board/earthlcd/favr-32-ezkit/Kconfig b/board/earthlcd/favr-32-ezkit/Kconfig deleted file mode 100644 index 50e29ec241..0000000000 --- a/board/earthlcd/favr-32-ezkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FAVR_32_EZKIT - -config SYS_BOARD - default "favr-32-ezkit" - -config SYS_VENDOR - default "earthlcd" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "favr-32-ezkit" - -endif diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS deleted file mode 100644 index 89ba862149..0000000000 --- a/board/earthlcd/favr-32-ezkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FAVR-32-EZKIT BOARD -#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> -S: Orphan (since 2014-06) -F: board/earthlcd/favr-32-ezkit/ -F: include/configs/favr-32-ezkit.h -F: configs/favr-32-ezkit_defconfig diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile deleted file mode 100644 index f712ab9c7a..0000000000 --- a/board/earthlcd/favr-32-ezkit/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2008 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := favr-32-ezkit.o flash.o diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c deleted file mode 100644 index f9ac330c33..0000000000 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - /* MT48LC4M32B2P-6 (16 MB) */ - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 12, - .col_bits = 8, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 15.6 us */ - .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); - - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart3(PORTMUX_DRIVE_MIN); -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - return 0; -} - -#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -int board_eth_init(bd_t *bi) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, - bi->bi_phy_id[0]); -} -#endif diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c deleted file mode 100644 index e45c6f4d01..0000000000 --- a/board/earthlcd/favr-32-ezkit/flash.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH -#include <asm/arch/cacheflush.h> -#include <asm/io.h> -#include <asm/sections.h> - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[1]; - -static void flash_identify(uint16_t *flash, flash_info_t *info) -{ - unsigned long flags; - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - - writew(0xaa, flash + 0x555); - writew(0x55, flash + 0xaaa); - writew(0x90, flash + 0x555); - info->flash_id = readl(flash); - writew(0xff, flash); - - readw(flash); - - if (flags) - enable_interrupts(); -} - -unsigned long flash_init(void) -{ - unsigned long addr; - unsigned int i; - - flash_info[0].size = CONFIG_SYS_FLASH_SIZE; - flash_info[0].sector_count = 135; - - flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); - - for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) - flash_info[0].start[i] = addr; - for (; i < flash_info[0].sector_count; i++, addr += 0x10000) - flash_info[0].start[i] = addr; - - return CONFIG_SYS_FLASH_SIZE; -} - -void flash_print_info(flash_info_t *info) -{ - printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", - info->flash_id >> 16, info->flash_id & 0xffff); - printf("Size: %ld MB in %d sectors\n", - info->size >> 10, info->sector_count); -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - unsigned long flags; - unsigned long start_time; - uint16_t *fb, *sb; - unsigned int i; - int ret; - uint16_t status; - - if ((s_first < 0) || (s_first > s_last) - || (s_last >= info->sector_count)) { - puts("Error: first and/or last sector out of range\n"); - return ERR_INVAL; - } - - for (i = s_first; i < s_last; i++) - if (info->protect[i]) { - printf("Error: sector %d is protected\n", i); - return ERR_PROTECTED; - } - - fb = (uint16_t *)uncached(info->start[0]); - - dcache_flush_unlocked(); - - for (i = s_first; (i <= s_last) && !ctrlc(); i++) { - printf("Erasing sector %3d...", i); - - sb = (uint16_t *)uncached(info->start[i]); - - flags = disable_interrupts(); - - start_time = get_timer(0); - - /* Unlock sector */ - writew(0xaa, fb + 0x555); - writew(0x70, sb); - - /* Erase sector */ - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x80, fb + 0x555); - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x30, sb); - - /* Wait for completion */ - ret = ERR_OK; - do { - /* TODO: Timeout */ - status = readw(sb); - } while ((status != 0xffff) && !(status & 0x28)); - - writew(0xf0, fb); - - /* - * Make sure the command actually makes it to the bus - * before we re-enable interrupts. - */ - readw(fb); - - if (flags) - enable_interrupts(); - - if (status != 0xffff) { - printf("Flash erase error at address 0x%p: 0x%02x\n", - sb, status); - ret = ERR_PROG_ERROR; - break; - } - } - - if (ctrlc()) - printf("User interrupt!\n"); - - return ERR_OK; -} - -int write_buff(flash_info_t *info, uchar *src, - ulong addr, ulong count) -{ - unsigned long flags; - uint16_t *base, *p, *s, *end; - uint16_t word, status, status1; - int ret = ERR_OK; - - if (addr < info->start[0] - || (addr + count) > (info->start[0] + info->size) - || (addr + count) < addr) { - puts("Error: invalid address range\n"); - return ERR_INVAL; - } - - if (addr & 1 || count & 1 || (unsigned int)src & 1) { - puts("Error: misaligned source, destination or count\n"); - return ERR_ALIGN; - } - - base = (uint16_t *)uncached(info->start[0]); - end = (uint16_t *)uncached(addr + count); - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - sync_write_buffer(); - - for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; - p < end && !ctrlc(); p++, s++) { - word = *s; - - writew(0xaa, base + 0x555); - writew(0x55, base + 0xaaa); - writew(0xa0, base + 0x555); - writew(word, p); - - sync_write_buffer(); - - /* Wait for completion */ - status1 = readw(p); - do { - /* TODO: Timeout */ - status = status1; - status1 = readw(p); - } while (((status ^ status1) & 0x40) /* toggled */ - && !(status1 & 0x28)); /* error bits */ - - /* - * We'll need to check once again for toggle bit - * because the toggle bit may stop toggling as I/O5 - * changes to "1" (ref at49bv642.pdf p9) - */ - status1 = readw(p); - status = readw(p); - if ((status ^ status1) & 0x40) { - printf("Flash write error at address 0x%p: " - "0x%02x != 0x%02x\n", - p, status,word); - ret = ERR_PROG_ERROR; - writew(0xf0, base); - readw(base); - break; - } - - writew(0xf0, base); - readw(base); - } - - if (flags) - enable_interrupts(); - - return ret; -} - -#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */ diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 5fa5d6a4de..d406c83481 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -191,7 +191,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ @@ -204,11 +205,17 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* PCI_RST# (GW522x) */ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -227,36 +234,46 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), /* MIPI_DIO */ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* VID_EN */ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLED# */ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* PCI_RST# */ @@ -266,6 +283,10 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = { }; static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -522,12 +543,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = { { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -539,12 +554,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, }, .num_gpios = 2, .leds = { @@ -560,6 +569,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, .dio_cfg = { { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -571,6 +586,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, }, .num_gpios = 4, .leds = { @@ -579,6 +600,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { IMX_GPIO_NR(4, 15), }, .pcie_rst = IMX_GPIO_NR(1, 29), + .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), }, }; @@ -712,7 +734,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info) * Configure DIO pinmux/padctl registers * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions */ - for (i = 0; i < 4; i++) { + for (i = 0; i < gpio_cfg[board].num_gpios; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index b7c0e96f2d..28f58160de 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -34,10 +34,6 @@ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -46,7 +42,7 @@ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) +#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 22f3b3860b..3b7c82b1dc 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -157,20 +157,18 @@ static iomux_v3_cfg_t const usb_pads[] = { int board_ehci_hcd_init(int port) { - struct ventana_board_info *info = &ventana_info; int gpio; SETUP_IOMUX_PADS(usb_pads); - /* Reset USB HUB (present on GW54xx/GW53xx) */ - switch (info->model[3]) { - case '3': /* GW53xx */ - case '5': /* GW552x */ - SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); + /* Reset USB HUB */ + switch (board_type) { + case GW53xx: + case GW552x: gpio = (IMX_GPIO_NR(1, 9)); break; - case '4': /* GW54xx */ - SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); + case GW54proto: + case GW54xx: gpio = (IMX_GPIO_NR(1, 16)); break; default: @@ -687,8 +685,7 @@ int misc_init_r(void) memset(str, 0, sizeof(str)); for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) str[i] = tolower(info->model[i]); - if (!getenv("model")) - setenv("model", str); + setenv("model", str); if (!getenv("fdt_file")) { sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file", fdt); @@ -698,18 +695,14 @@ int misc_init_r(void) *p++ = 0; setenv("model_base", str); - if (!getenv("fdt_file1")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file1", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); if (board_type != GW551x && board_type != GW552x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; - if (!getenv("fdt_file2")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file2", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); } /* initialize env from EEPROM */ @@ -818,9 +811,11 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - /* Update partition nodes using info from mtdparts env var */ - puts(" Updating MTD partitions...\n"); - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + if (test_bit(EECONFIG_NAND, info->config)) { + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + } /* Update display timings from display env var */ if (display) { @@ -829,10 +824,6 @@ int ft_board_setup(void *blob, bd_t *bd) printf(" Set display timings for %s...\n", display); } - if (!model) { - puts("invalid board info: Leaving FDT fully enabled\n"); - return 0; - } printf(" Adjusting FDT per EEPROM for %s...\n", model); /* board serial number */ diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9f5d2b17cd..d4418e554c 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -515,10 +515,8 @@ void board_init_f(ulong dummy) setup_iomux_gpio(board_model, &ventana_info); /* provide some some default: 32bit 128MB */ - if (GW_UNKNOWN == board_model) { - ventana_info.sdram_width = 2; - ventana_info.sdram_size = 3; - } + if (GW_UNKNOWN == board_model) + hang(); /* configure MMDC for SDRAM width/size and per-model calibration */ spl_dram_init(8 << ventana_info.sdram_width, diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index beb2fac374..d76c28bd3c 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -33,6 +33,46 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD +#define OSC (V_OSCK/1000000) + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, @@ -56,6 +96,70 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, }; +const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr2 = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +static int read_eeprom(struct pepper_board_id *header) +{ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + return -ENODEV; + } + + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct pepper_board_id))) { + return -EIO; + } + + return 0; +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + struct pepper_board_id header; + + enable_i2c0_pin_mux(); + i2c_set_bus_num(0); + + if (read_eeprom(&header) < 0) + return &dpll_ddr3; + + switch (header.device_vendor) { + case GUMSTIX_PEPPER: + return &dpll_ddr2; + case GUMSTIX_PEPPER_DVI: + return &dpll_ddr3; + default: + return &dpll_ddr3; + } +} + +void sdram_init(void) +{ + const struct dpll_params *dpll = get_dpll_ddr_params(); + + /* + * Here we are assuming PLL clock reveals the type of RAM. + * DDR2 = 266 + * DDR3 = 400 + * Note that DDR3 is the default. + */ + if (dpll->m == 266) { + config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); + } + else if (dpll->m == 400) { + config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + } +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -64,14 +168,6 @@ int spl_start_uboot(void) } #endif -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -82,19 +178,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -}; -void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} #endif int board_init(void) diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h index 0512735a7b..a6df3196f4 100644 --- a/board/gumstix/pepper/board.h +++ b/board/gumstix/pepper/board.h @@ -9,6 +9,18 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#define GUMSTIX_PEPPER 0x30000200 +#define GUMSTIX_PEPPER_DVI 0x31000200 + +struct pepper_board_id { + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + char fab_revision[8]; + char env_var[16]; + char en_setting[64]; +}; + /* * We must be able to enable uart0, for initial output. We then have a * main pinmux function that can be overridden to enable all other pinmux that @@ -16,4 +28,5 @@ */ void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c index 50b12666d6..92c73f8df8 100644 --- a/board/gumstix/pepper/mux.c +++ b/board/gumstix/pepper/mux.c @@ -64,6 +64,11 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + /* * Do board-specific muxes. */ diff --git a/board/highbank/Makefile b/board/highbank/Makefile index d3eb23220b..ce7ee68d4a 100644 --- a/board/highbank/Makefile +++ b/board/highbank/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := highbank.o +obj-y := highbank.o ahci.o diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c new file mode 100644 index 0000000000..00153232f6 --- /dev/null +++ b/board/highbank/ahci.c @@ -0,0 +1,218 @@ +/* + * Copyright 2012 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <ahci.h> +#include <asm/io.h> + +#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) +#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2)) +#define CPHY_BASE 0xfff58000 +#define CPHY_WIDTH 0x1000 +#define CPHY_DTE_XS 5 +#define CPHY_MII 31 +#define SERDES_CR_CTL 0x80a0 +#define SERDES_CR_ADDR 0x80a1 +#define SERDES_CR_DATA 0x80a2 +#define CR_BUSY 0x0001 +#define CR_START 0x0001 +#define CR_WR_RDN 0x0002 +#define CPHY_TX_INPUT_STS 0x2001 +#define CPHY_RX_INPUT_STS 0x2002 +#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000 +#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000 +#define CPHY_TX_INPUT_OVERRIDE 0x2004 +#define CPHY_RX_INPUT_OVERRIDE 0x2005 +#define SPHY_LANE 0x100 +#define SPHY_HALF_RATE 0x0001 +#define CPHY_SATA_DPLL_MODE 0x0700 +#define CPHY_SATA_DPLL_SHIFT 8 +#define CPHY_SATA_TX_ATTEN 0x1c00 +#define CPHY_SATA_TX_ATTEN_SHIFT 10 + +#define HB_SREG_SATA_ATTEN 0xfff3cf24 + +#define SATA_PORT_BASE 0xffe08000 +#define SATA_VERSIONR 0xf8 +#define SATA_HB_VERSION 0x3332302a + +static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr) +{ + u32 data; + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); + return data; +} + +static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data) +{ + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); +} + +static u32 combo_phy_read(u8 phy, u32 addr) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START); + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA); +} + +static void combo_phy_write(u8 phy, u32 addr, u32 data) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START); +} + +static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) +{ + u32 tmp; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp &= ~CPHY_SATA_DPLL_MODE; + tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_tx_attenuation_override(u8 phy, u8 lane) +{ + u32 val; + u32 tmp; + u8 shift; + + shift = ((phy == 5) ? 4 : lane) * 4; + + val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf; + + if (val & 0x8) + return; + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_disable_port_overrides(u8 port) +{ + u32 tmp; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +void cphy_disable_overrides(void) +{ + int i; + u32 port_map; + + port_map = readl(0xffe08000 + HOST_PORTS_IMPL); + for (i = 0; i < 5; i++) { + if (port_map & (1 << i)) + cphy_disable_port_overrides(i); + } +} + +static void cphy_override_lane(u8 port) +{ + u32 tmp, k = 0; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + + do { + tmp = combo_phy_read(0, CPHY_RX_INPUT_STS + + lane * SPHY_LANE); + } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); + cphy_spread_spectrum_override(phy, lane, 3); + cphy_tx_attenuation_override(phy, lane); +} + +#define WAIT_MS_LINKUP 4 + +int ahci_link_up(struct ahci_probe_ent *probe_ent, int port) +{ + u32 tmp; + int j = 0; + u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) == + SATA_HB_VERSION ? 1 : 0; + + /* Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + if (is_highbank && (j == 0)) { + cphy_disable_port_overrides(port); + writel(0x301, port_mmio + PORT_SCR_CTL); + udelay(1000); + writel(0x300, port_mmio + PORT_SCR_CTL); + udelay(1000); + cphy_override_lane(port); + } + + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + return 0; + udelay(1000); + j++; + + if ((j == WAIT_MS_LINKUP) && (tmp & 0xf)) + j = 0; /* retry phy reset */ + } + return 1; +} diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index ba1beb5bbc..469ee8e114 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -14,9 +14,11 @@ #define HB_AHCI_BASE 0xffe08000 +#define HB_SCU_A9_PWR_STATUS 0xfff10008 #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 #define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 +#define HB_SREG_A15_PWR_CTRL 0xfff3c200 #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 @@ -27,8 +29,14 @@ #define PWRDOM_STAT_PCI 0x40000000 #define PWRDOM_STAT_EMMC 0x20000000 +#define HB_SCU_A9_PWR_NORMAL 0 +#define HB_SCU_A9_PWR_DORMANT 2 +#define HB_SCU_A9_PWR_OFF 3 + DECLARE_GLOBAL_DATA_PTR; +void cphy_disable_overrides(void); + /* * Miscellaneous platform dependent initialisations */ @@ -56,6 +64,7 @@ void scsi_init(void) { u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + cphy_disable_overrides(); if (reg & PWRDOM_STAT_SATA) { ahci_init((void __iomem *)HB_AHCI_BASE); scsi_scan(1); @@ -111,9 +120,31 @@ int ft_board_setup(void *fdt, bd_t *bd) } #endif +static int is_highbank(void) +{ + uint32_t midr; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); + + return (midr & 0xfff0) == 0xc090; +} + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); + if (is_highbank()) + writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS); + else + writel(0x1, HB_SREG_A15_PWR_CTRL); wfi(); } + +/* + * turn off the override before transferring control to Linux, since Linux + * may not support spread spectrum. + */ +void arch_preboot_os(void) +{ + cphy_disable_overrides(); +} diff --git a/board/mimc/mimc200/Kconfig b/board/mimc/mimc200/Kconfig deleted file mode 100644 index 18736d7f96..0000000000 --- a/board/mimc/mimc200/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MIMC200 - -config SYS_BOARD - default "mimc200" - -config SYS_VENDOR - default "mimc" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "mimc200" - -endif diff --git a/board/mimc/mimc200/MAINTAINERS b/board/mimc/mimc200/MAINTAINERS deleted file mode 100644 index 6cb51dd3cb..0000000000 --- a/board/mimc/mimc200/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MIMC200 BOARD -M: Mark Jackson <mpfj@mimc.co.uk> -S: Maintained -F: board/mimc/mimc200/ -F: include/configs/mimc200.h -F: configs/mimc200_defconfig diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile deleted file mode 100644 index 5c30c0dbca..0000000000 --- a/board/mimc/mimc200/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := mimc200.o diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c deleted file mode 100644 index f078295508..0000000000 --- a/board/mimc/mimc200/mimc200.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> -#include <atmel_lcdc.h> -#include <lcd.h> - -#include "../../../arch/avr32/cpu/hsmc3.h" - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT, - .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -#if defined(CONFIG_LCD) -/* 480x272x16 @ 72 Hz */ -vidinfo_t panel_info = { - .vl_col = 480, /* Number of columns */ - .vl_row = 272, /* Number of rows */ - .vl_clk = 5000000, /* pixel clock in ps */ - .vl_sync = ATMEL_LCDC_INVCLK_INVERTED | - ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */ - .vl_tft = 1, /* 0 = passive, 1 = TFT */ - .vl_hsync_len = 42, /* Length of horizontal sync */ - .vl_left_margin = 1, /* Time from sync to picture */ - .vl_right_margin = 1, /* Time from picture to sync */ - .vl_vsync_len = 1, /* Length of vertical sync */ - .vl_upper_margin = 12, /* Time from sync to picture */ - .vl_lower_margin = 1, /* Time from picture to sync */ - .mmio = LCDC_BASE, /* Memory mapped registers */ -}; - -void lcd_enable(void) -{ -} - -void lcd_disable(void) -{ -} -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_16BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 6, - .trp = 2, - .trcd = 2, - .tras = 6, - .txsr = 6, - /* 15.6 us */ - .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - /* Enable 26 address bits and NCS2 */ - portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - - /* de-assert "force sys reset" pin */ - portmux_select_gpio(PORTMUX_PORT_D, 1 << 15, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - - /* init custom i/o */ - /* cpu type inputs */ - portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23), - PORTMUX_DIR_INPUT); - /* main board type inputs */ - portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29), - PORTMUX_DIR_INPUT); - /* DEBUG input (use weak pullup) */ - portmux_select_gpio(PORTMUX_PORT_E, 1 << 21, - PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); - - /* are we suppressing the console ? */ - if (gpio_get_value(GPIO_PIN_PE(21)) == 1) - gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); - - /* reset phys */ - portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT); - portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - - udelay(5000); - - /* release phys reset */ - gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */ - - /* setup Data Flash chip select (NCS2) */ - hsmc3_writel(MODE2, 0x20121003); - hsmc3_writel(CYCLE2, 0x000a0009); - hsmc3_writel(PULSE2, 0x0a060806); - hsmc3_writel(SETUP2, 0x00030102); - - /* setup FRAM chip select (NCS3) */ - hsmc3_writel(MODE3, 0x10120001); - hsmc3_writel(CYCLE3, 0x001e001d); - hsmc3_writel(PULSE3, 0x08040704); - hsmc3_writel(SETUP3, 0x02050204); - -#if defined(CONFIG_MACB) - /* init macb0 pins */ - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); - portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif - -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - -#if defined(CONFIG_LCD) - portmux_enable_lcdc(1); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - gd->bd->bi_phy_id[1] = 0x03; - return 0; -} - -int board_postclk_init(void) -{ - /* Use GCLK0 as 10MHz output */ - gclk_enable_output(0, PORTMUX_DRIVE_LOW); - gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000); - return 0; -} - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return (bus == 0) && (cs == 0); -} - -void spi_cs_activate(struct spi_slave *slave) -{ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ -} -#endif /* CONFIG_ATMEL_SPI */ - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); - - return 0; -} -#endif diff --git a/board/miromico/hammerhead/Kconfig b/board/miromico/hammerhead/Kconfig deleted file mode 100644 index 1f09ef782e..0000000000 --- a/board/miromico/hammerhead/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_HAMMERHEAD - -config SYS_BOARD - default "hammerhead" - -config SYS_VENDOR - default "miromico" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "hammerhead" - -endif diff --git a/board/miromico/hammerhead/MAINTAINERS b/board/miromico/hammerhead/MAINTAINERS deleted file mode 100644 index a87ceeeb73..0000000000 --- a/board/miromico/hammerhead/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HAMMERHEAD BOARD -M: Alex Raimondi <alex.raimondi@miromico.ch> -S: Maintained -F: board/miromico/hammerhead/ -F: include/configs/hammerhead.h -F: configs/hammerhead_defconfig diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile deleted file mode 100644 index 638a9df930..0000000000 --- a/board/miromico/hammerhead/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2008 Miromico AG -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := hammerhead.o diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c deleted file mode 100644 index a0c7d3b323..0000000000 --- a/board/miromico/hammerhead/hammerhead.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2008 Miromico AG - * - * Mostly copied form atmel ATNGW100 sources - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, - bis->bi_phy_id[0]); -} -#endif - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - return 0; -} - -int board_postclk_init(void) -{ - /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ - gclk_enable_output(3, PORTMUX_DRIVE_LOW); - gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000); - return 0; -} diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 9d4ea1b3f9..420ad13a12 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -105,10 +105,6 @@ fix_start: /* r6 - maximal u-boot size */ ldr r6, imagesize - /* fix return address */ - subhi lr, lr, r5 - addlo lr, lr, r5 - /* r1 - start of u-boot after */ ldr r1, startaddr diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS index ff74627af2..779077729c 100644 --- a/board/nvidia/nyan-big/MAINTAINERS +++ b/board/nvidia/nyan-big/MAINTAINERS @@ -1,4 +1,4 @@ -NORRIN BOARD +NYAN-BIG BOARD M: Allen Martin <amartin@nvidia.com> S: Maintained F: board/nvidia/nyan-big/ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ae8874bbd2..ba96401890 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -8,7 +8,12 @@ #include <common.h> #include <errno.h> #include <asm/gpio.h> +#include <asm/io.h> #include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> +#include <asm/arch/mc.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> #include <power/as3722.h> #include <power/pmic.h> #include "pinmux-config-nyan-big.h" @@ -57,3 +62,67 @@ int tegra_lcd_pmic_init(int board_id) return 0; } + +/* Setup required information for Linux kernel */ +static void setup_kernel_info(void) +{ + struct mc_ctlr *mc = (void *)NV_PA_MC_BASE; + + /* The kernel graphics driver needs this region locked down */ + writel(0, &mc->mc_video_protect_bom); + writel(0, &mc->mc_video_protect_size_mb); + writel(1, &mc->mc_video_protect_reg_ctrl); +} + +/* + * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF, + * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks. + * Otherwise reading AHUB devices will hang when the kernel boots. + */ +static void enable_required_clocks(void) +{ + static enum periph_id ids[] = { + PERIPH_ID_I2S0, + PERIPH_ID_I2S1, + PERIPH_ID_I2S2, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_AMX0, + PERIPH_ID_AMX1, + PERIPH_ID_ADX0, + PERIPH_ID_ADX1, + PERIPH_ID_SPDIF, + PERIPH_ID_AFC0, + PERIPH_ID_AFC1, + PERIPH_ID_AFC2, + PERIPH_ID_AFC3, + PERIPH_ID_AFC4, + PERIPH_ID_AFC5, + PERIPH_ID_EXTPERIPH1 + }; + int i; + + for (i = 0; i < ARRAY_SIZE(ids); i++) + clock_enable(ids[i]); + udelay(2); + for (i = 0; i < ARRAY_SIZE(ids); i++) + reset_set_enable(ids[i], 0); +} + +int nvidia_board_init(void) +{ + clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); + clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); + + /* For external MAX98090 audio codec */ + clock_external_output(1); + setup_kernel_info(); + enable_required_clocks(); + + return 0; +} diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4aae230608..d7b9e5af88 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = { 400, 23, 1, -1, 2, -1, -1 }; +static const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { .emif_cos_config = 0x00ffffff }; +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } + + return; +} + /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index ffcd53185b..b6c17ec83f 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -15,6 +15,7 @@ #include <asm/omap_common.h> #include <asm/emif.h> #include <asm/arch/clock.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -52,23 +53,29 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; +/* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00740074, + 0x00780078, + 0x007c007c, + 0x007b007b, 0x00800080, 0x00360036, 0x00340034, @@ -90,14 +97,19 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { @@ -109,23 +121,28 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00820082, + 0x008b008b, + 0x00800080, + 0x007e007e, 0x00800080, 0x00370037, 0x00390039, @@ -145,14 +162,19 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) @@ -240,23 +262,20 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h index df658c5211..09d3650983 100644 --- a/board/ti/beagle_x15/mux_data.h +++ b/board/ti/beagle_x15/mux_data.h @@ -13,43 +13,318 @@ #include <asm/arch/mux_dra7xx.h> const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ - {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ - {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ - {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ - {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ - {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ - {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ - {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ - {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ - {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ - {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ - {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */ - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ - {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ - {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {USB1_DRVVBUS, (M0 | FSC) }, - {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ + {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */ + {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */ + {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */ + {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */ + {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */ + {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */ + {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */ + {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */ + {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */ + {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */ + {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */ + {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */ + {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */ + {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */ + {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */ + {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */ + {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */ + {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */ + {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */ + {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */ + {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */ + {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */ + {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */ + {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */ + {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */ + {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */ + {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */ + {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */ + {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ + {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */ + {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */ + {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */ + {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */ + {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */ + {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */ + {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */ + {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */ + {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ + {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ + {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ + {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ + {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ + {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */ + {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */ + {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ + {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ + {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ + {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */ + {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */ + {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */ + {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ + {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ + {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ + {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ + {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */ + {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */ + {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ + {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ + {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ + {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ + {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ + {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */ + {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */ + {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ + {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ + {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ + {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */ + {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ + {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */ + {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */ + {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */ + {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */ + {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */ + {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */ + {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */ + {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ + {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ + {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ + {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ + {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */ + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ + {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ }; + +const struct pad_conf_entry early_padconf[] = { + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */ + {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */ + {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */ + {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */ + {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */ + {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */ + {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */ + {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */ + {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */ + {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */ + {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */ + {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */ + {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */ + {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */ + {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */ + {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */ + {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */ + {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */ + {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */ + {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */ + {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */ + {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */ + {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */ + {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */ + {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ + {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ + {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif #endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d4648558ec..94a1a8c256 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -17,6 +17,7 @@ #include <usb.h> #include <linux/usb/gadget.h> #include <asm/arch/gpio.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -40,43 +41,6 @@ const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; -/* - * Adjust I/O delays on the Tx control and data lines of each MAC port. This - * is a workaround in order to work properly with the DP83865 PHYs on the EVM. - * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we - * essentially need to counteract the DRA7xx internal delay, and we do this - * by delaying the control and data lines. If not using this PHY, you probably - * don't need to do this stuff! - */ -static void dra7xx_adj_io_delay(const struct io_delay *io_dly) -{ - int i = 0; - u32 reg_val; - u32 delta; - u32 coarse; - u32 fine; - - writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); - - while(io_dly[i].addr) { - writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, - io_dly[i].addr); - delta = io_dly[i].dly; - reg_val = readl(io_dly[i].addr) & 0x3ff; - coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); - coarse = (coarse > 0x1F) ? (0x1F) : (coarse); - fine = (reg_val & 0x1F) + (delta & 0x1F); - fine = (fine > 0x1F) ? (0x1F) : (fine); - reg_val = CFG_IO_DELAY_ACCESS_PATTERN | - CFG_IO_DELAY_LOCK_MASK | - ((coarse << 5) | (fine)); - writel(reg_val, io_dly[i].addr); - i++; - } - - writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); -} - /** * @brief board_init * @@ -107,23 +71,28 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + if (is_dra72x()) { + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, + ARRAY_SIZE(iodelay_cfg_array)); + } else { + __recalibrate_iodelay(dra74x_core_padconf_array, + ARRAY_SIZE(dra74x_core_padconf_array), + dra742_iodelay_cfg_array, + ARRAY_SIZE(dra742_iodelay_cfg_array)); + } } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) @@ -257,19 +226,6 @@ int spl_start_uboot(void) #endif #ifdef CONFIG_DRIVER_TI_CPSW - -/* Delay value to add to calibrated value */ -#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) -#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) -#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) -#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) - extern u32 *const omap_si_rev; static void cpsw_control(int enabled) @@ -317,22 +273,6 @@ int board_eth_init(bd_t *bis) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; - const struct io_delay io_dly[] = { - {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, - {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, - {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, - {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, - {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, - {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, - {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, - {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, - {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, - {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, - {0} - }; - - /* Adjust IO delay for RGMII tx path */ - dra7xx_adj_io_delay(io_dly); /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 48240779c9..c9301a51c0 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -76,30 +76,30 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {VIN2A_D12, (M3) }, - {VIN2A_D13, (M3) }, - {VIN2A_D14, (M3) }, - {VIN2A_D15, (M3) }, - {VIN2A_D16, (M3) }, - {VIN2A_D17, (M3) }, - {VIN2A_D18, (IEN | M3)}, - {VIN2A_D19, (IEN | M3)}, - {VIN2A_D20, (IEN | M3)}, - {VIN2A_D21, (IEN | M3)}, - {VIN2A_D22, (IEN | M3)}, - {VIN2A_D23, (IEN | M3)}, + {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) }, + {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)}, #if defined(CONFIG_NAND) || defined(CONFIG_NOR) /* NAND / NOR pin-mux */ {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ @@ -141,4 +141,295 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USB2_DRVVBUS, (M0 | IEN | FSC) }, {SPI1_CS1, (PEN | IDIS | M14) }, }; + +const struct pad_conf_entry early_padconf[] = { +#if (CONFIG_CONS_INDEX == 1) + {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ + {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ +#elif (CONFIG_CONS_INDEX == 3) + {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ + {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ +#endif + {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */ + {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */ + {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */ + {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */ + {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */ + {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */ + {0x740, 531, 120}, /* RGMMI0_TXC_OUT */ + {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */ + {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */ + {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */ + {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */ + {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */ + {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ + {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ +}; +#endif + +const struct pad_conf_entry dra74x_core_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */ + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */ + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */ + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */ + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */ + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */ + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ + {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ + {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ + {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ + {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */ + {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */ + {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */ + {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */ + {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */ + {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */ + {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */ + {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */ + {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */ + {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */ + {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */ + {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */ + {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */ + {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */ + {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */ + {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */ + {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */ + {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */ + {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */ + {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */ + {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */ + {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */ + {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */ + {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */ + {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ + {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ + {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */ + {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */ + {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */ + {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */ + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ + {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ + {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ + {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */ + {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ + {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */ + {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */ + {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */ + {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */ + {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */ + {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */ + {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */ + {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */ + {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */ + {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */ + {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */ + {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */ + {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */ + {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */ + {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */ + {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */ + {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */ + {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */ + {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */ + {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */ + {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */ + {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */ + {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */ + {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */ + {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */ + {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */ + {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */ + {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */ + {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif + #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 551c575c9d..a1217a47bd 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -4,3 +4,7 @@ S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h F: configs/colibri_vf_defconfig +F: configs/colibri_vf_dtb_defconfig +F: arch/arm/dts/vf-colibri.dtsi +F: arch/arm/dts/vf500-colibri.dts +F: arch/arm/dts/vf610-colibri.dts diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 31ebb1935f..8618fd068c 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -20,6 +20,7 @@ #include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { + VF610_PAD_PTD4__GPIO_83, +}; + int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -146,6 +153,76 @@ static void setup_iomux_nfc(void) } #endif +#ifdef CONFIG_FSL_DSPI +static void setup_iomux_dspi(void) +{ + static const iomux_v3_cfg_t dspi1_pads[] = { + VF610_PAD_PTD5__DSPI1_CS0, + VF610_PAD_PTD6__DSPI1_SIN, + VF610_PAD_PTD7__DSPI1_SOUT, + VF610_PAD_PTD8__DSPI1_SCK, + }; + + imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); +} +#endif + +#ifdef CONFIG_VYBRID_GPIO +static void setup_iomux_gpio(void) +{ + static const iomux_v3_cfg_t gpio_pads[] = { + VF610_PAD_PTA17__GPIO_7, + VF610_PAD_PTA20__GPIO_10, + VF610_PAD_PTA21__GPIO_11, + VF610_PAD_PTA30__GPIO_20, + VF610_PAD_PTA31__GPIO_21, + VF610_PAD_PTB0__GPIO_22, + VF610_PAD_PTB1__GPIO_23, + VF610_PAD_PTB6__GPIO_28, + VF610_PAD_PTB7__GPIO_29, + VF610_PAD_PTB8__GPIO_30, + VF610_PAD_PTB9__GPIO_31, + VF610_PAD_PTB12__GPIO_34, + VF610_PAD_PTB13__GPIO_35, + VF610_PAD_PTB16__GPIO_38, + VF610_PAD_PTB17__GPIO_39, + VF610_PAD_PTB18__GPIO_40, + VF610_PAD_PTB21__GPIO_43, + VF610_PAD_PTB22__GPIO_44, + VF610_PAD_PTC0__GPIO_45, + VF610_PAD_PTC1__GPIO_46, + VF610_PAD_PTC2__GPIO_47, + VF610_PAD_PTC3__GPIO_48, + VF610_PAD_PTC4__GPIO_49, + VF610_PAD_PTC5__GPIO_50, + VF610_PAD_PTC6__GPIO_51, + VF610_PAD_PTC7__GPIO_52, + VF610_PAD_PTC8__GPIO_53, + VF610_PAD_PTD31__GPIO_63, + VF610_PAD_PTD30__GPIO_64, + VF610_PAD_PTD29__GPIO_65, + VF610_PAD_PTD28__GPIO_66, + VF610_PAD_PTD27__GPIO_67, + VF610_PAD_PTD26__GPIO_68, + VF610_PAD_PTD25__GPIO_69, + VF610_PAD_PTD24__GPIO_70, + VF610_PAD_PTD9__GPIO_88, + VF610_PAD_PTD10__GPIO_89, + VF610_PAD_PTD11__GPIO_90, + VF610_PAD_PTD12__GPIO_91, + VF610_PAD_PTD13__GPIO_92, + VF610_PAD_PTB23__GPIO_93, + VF610_PAD_PTB26__GPIO_96, + VF610_PAD_PTB28__GPIO_98, + VF610_PAD_PTC29__GPIO_102, + VF610_PAD_PTC30__GPIO_103, + VF610_PAD_PTA7__GPIO_134, + }; + + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -196,6 +273,9 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); +#ifdef CONFIG_FSL_DSPI + setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); +#endif clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, @@ -304,6 +384,14 @@ int board_early_init_f(void) setup_iomux_nfc(); #endif +#ifdef CONFIG_VYBRID_GPIO + setup_iomux_gpio(); +#endif + +#ifdef CONFIG_FSL_DSPI + setup_iomux_dspi(); +#endif + return 0; } @@ -383,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) return 0; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + switch (port) { + case 0: + /* USBC does not have PEN, also configured as USB client only */ + break; + case 1: + gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); + gpio_direction_output(USB_PEN_GPIO, 0); + break; + } + return 0; +} +#endif diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig new file mode 100644 index 0000000000..bc1edcf3a4 --- /dev/null +++ b/board/vscom/baltos/Kconfig @@ -0,0 +1,24 @@ +if TARGET_AM335X_BALTOS + +config SYS_BOARD + default "baltos" + +config SYS_VENDOR + default "vscom" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "baltos" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0. + +endif diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile new file mode 100644 index 0000000000..804ac379db --- /dev/null +++ b/board/vscom/baltos/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README new file mode 100644 index 0000000000..f744ace997 --- /dev/null +++ b/board/vscom/baltos/README @@ -0,0 +1 @@ +BSP for VScom OnRISC Balios family devices, like Balios iR 5221. diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c new file mode 100644 index 0000000000..99ca60e2ac --- /dev/null +++ b/board/vscom/baltos/board.c @@ -0,0 +1,474 @@ +/* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 +#define DIP_S1 44 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int baltos_set_console(void) +{ + int val, i, dips = 0; + char buf[7]; + + for (i = 0; i < 4; i++) { + sprintf(buf, "dip_s%d", i + 1); + + if (gpio_request(DIP_S1 + i, buf)) { + printf("failed to export GPIO %d\n", DIP_S1 + i); + return 0; + } + + if (gpio_direction_input(DIP_S1 + i)) { + printf("failed to set GPIO %d direction\n", DIP_S1 + i); + return 0; + } + + val = gpio_get_value(DIP_S1 + i); + dips |= val << i; + } + + printf("DIPs: 0x%1x\n", (~dips) & 0xf); + + if ((dips & 0xf) == 0xe) + setenv("console", "ttyUSB0,115200n8"); + + return 0; +} + +static int read_eeprom(BSP_VS_HWPARAM *header) +{ + i2c_set_bus_num(1); + + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(BSP_VS_HWPARAM))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header->Magic != 0xDEADBEEF) { + + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->Magic); + + /* fill default values */ + header->SystemId = 211; + header->MAC1[0] = 0x00; + header->MAC1[1] = 0x00; + header->MAC1[2] = 0x00; + header->MAC1[3] = 0x00; + header->MAC1[4] = 0x00; + header->MAC1[5] = 0x01; + + header->MAC2[0] = 0x00; + header->MAC2[1] = 0x00; + header->MAC2[2] = 0x00; + header->MAC2[3] = 0x00; + header->MAC2[4] = 0x00; + header->MAC2[5] = 0x02; + + header->MAC3[0] = 0x00; + header->MAC3[1] = 0x00; + header->MAC3[2] = 0x00; + header->MAC3[3] = 0x00; + header->MAC3[4] = 0x00; + header->MAC3[5] = 0x03; + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +static const struct ddr_data ddr3_baltos_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_baltos_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return (serial_tstc() && serial_getc() == 'c'); +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_baltos = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int sil_rev; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + i2c_set_bus_num(1); + + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { + puts("i2c: cannot access TPS65910\n"); + return; + } + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + + writel(0x000010ff, PRM_DEVICE_INST + 4); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); + + return &dpll_ddr_baltos; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_baltos = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + + config_ddr(400, &ioregs_baltos, + &ddr3_baltos_data, + &ddr3_baltos_cmd_ctrl_data, + &ddr3_baltos_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int node, ret; + unsigned char mac_addr[6]; + BSP_VS_HWPARAM header; + + /* get production data */ + if (read_eeprom(&header)) + return 0; + + /* setup MAC1 */ + mac_addr[0] = header.MAC1[0]; + mac_addr[1] = header.MAC1[1]; + mac_addr[2] = header.MAC1[2]; + mac_addr[3] = header.MAC1[3]; + mac_addr[4] = header.MAC1[4]; + mac_addr[5] = header.MAC1[5]; + + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + /* setup MAC2 */ + mac_addr[0] = header.MAC2[0]; + mac_addr[1] = header.MAC2[1]; + mac_addr[2] = header.MAC2[2]; + mac_addr[3] = header.MAC2[3]; + mac_addr[4] = header.MAC2[4]; + mac_addr[5] = header.MAC2[5]; + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + printf("\nFDT was successfully setup\n"); + + return 0; +} + +static struct module_pin_mux dip_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ + {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ + {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ + {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ + {-1}, +}; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + BSP_VS_HWPARAM header; + char model[4]; + + /* get production data */ + if (read_eeprom(&header)) { + sprintf(model, "211"); + } else { + sprintf(model, "%d", header.SystemId); + if (header.SystemId == 215) { + configure_module_pin_mux(dip_pin_mux); + baltos_set_console(); + } + } + setenv("board_name", model); +#endif + + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 7, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .active_slave = 1, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; + + /* + * Note here that we're using CPSW1 since that has a 1Gbit PHY while + * CSPW0 has a 100Mbit PHY. + * + * On product, CPSW1 maps to port labeled WAN. + */ + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the first instance. + */ +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + const char *devname; + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); +#endif + return n; +} +#endif diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h new file mode 100644 index 0000000000..bcdb6485d2 --- /dev/null +++ b/board/vscom/baltos/board.h @@ -0,0 +1,90 @@ +/* + * board.h + * + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * TI AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +typedef struct _BSP_VS_HWPARAM // v1.0 +{ + uint32_t Magic; + uint32_t HwRev; + uint32_t SerialNumber; + char PrdDate[11]; // as a string ie. "01.01.2006" + uint16_t SystemId; + uint8_t MAC1[6]; // internal EMAC + uint8_t MAC2[6]; // SMSC9514 + uint8_t MAC3[6]; // WL1271 WLAN +} __attribute__ ((packed)) BSP_VS_HWPARAM; + +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_i2c1_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c new file mode 100644 index 0000000000..8783b25b5f --- /dev/null +++ b/board/vscom/baltos/mux.c @@ -0,0 +1,194 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_i2c1_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); +} + +void enable_board_pin_mux() +{ + /* Baltos */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif +} diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds new file mode 100644 index 0000000000..315ba5b99a --- /dev/null +++ b/board/vscom/baltos/u-boot.lds @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/vscom/baltos/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 90625ab9e0..0af63d291f 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) +#define REV_DETECTION IMX_GPIO_NR(2, 28) int dram_init(void) { @@ -105,6 +106,10 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static iomux_v3_cfg_t const rev_detection_pad[] = { + IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); @@ -393,6 +398,17 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +static bool is_revc1(void) +{ + SETUP_IOMUX_PADS(rev_detection_pad); + gpio_direction_input(REV_DETECTION); + + if (gpio_get_value(REV_DETECTION)) + return true; + else + return false; +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE @@ -404,6 +420,11 @@ int board_late_init(void) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); + + if (is_revc1()) + setenv("board_name", "C1"); + else + setenv("board_name", "B1"); #endif return 0; } @@ -424,7 +445,10 @@ int board_init(void) int checkboard(void) { - puts("Board: Wandboard\n"); + if (is_revc1()) + puts("Board: Wandboard rev C1\n"); + else + puts("Board: Wandboard rev B1\n"); return 0; } diff --git a/board/warp/README b/board/warp/README index db3100edba..22f9055eb6 100644 --- a/board/warp/README +++ b/board/warp/README @@ -34,7 +34,7 @@ Then U-boot should start and its messages will appear in the console program. Use the default environment variables: => env default -f -a -=> save +=> saveenv Run the DFU command: => dfu 0 mmc 0 |
